JPH11219905A - Thin film semiconductor device, method for manufacturing the same, method for manufacturing thin film transistor, thin film transistor, and liquid crystal display device - Google Patents
Thin film semiconductor device, method for manufacturing the same, method for manufacturing thin film transistor, thin film transistor, and liquid crystal display deviceInfo
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- JPH11219905A JPH11219905A JP2175998A JP2175998A JPH11219905A JP H11219905 A JPH11219905 A JP H11219905A JP 2175998 A JP2175998 A JP 2175998A JP 2175998 A JP2175998 A JP 2175998A JP H11219905 A JPH11219905 A JP H11219905A
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- semiconductor
- thin film
- manufacturing
- film transistor
- semiconductor device
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Abstract
(57)【要約】 (修正有)
【課題】薄膜半導体装置を製造する際に、他の製造工程
に悪影響を及ぼさない手法で結晶性半導体の結晶粒径を
拡大させる。
【解決手段】レーザ4を照射する半導体の表面を加工し
て、レーザ照射時に下地基板に平行な温度勾配の成分が
ある一方向に生じる形状にする。冷却時に結晶成長はこ
の温度勾配に平行な方向に起、結晶は下地基板に平行に
成長し、垂直方向に成長する場合と異なり下地酸化シリ
コン膜2との界面や表面で成長が止められることはない
ので、結晶粒径が1μmと大きい高品質な多結晶シリコ
ン5が形成できる。
(57) [Summary] (Modified) [PROBLEMS] To increase the crystal grain size of a crystalline semiconductor by a method that does not adversely affect other manufacturing steps when manufacturing a thin film semiconductor device. A surface of a semiconductor to be irradiated with a laser is processed into a shape in which a temperature gradient component parallel to a base substrate is generated in one direction during laser irradiation. During cooling, crystal growth occurs in a direction parallel to this temperature gradient, and the crystal grows parallel to the underlying substrate, and unlike the case where it grows in the vertical direction, the growth stops at the interface or surface with the underlying silicon oxide film 2 Therefore, high-quality polycrystalline silicon 5 having a large crystal grain size of 1 μm can be formed.
Description
【0001】[0001]
【発明の属する技術分野】本発明は薄膜半導体装置およ
びその製造方法に関するものである。The present invention relates to a thin film semiconductor device and a method for manufacturing the same.
【0002】[0002]
【従来の技術】半導体にエネルギービームを照射して結
晶性半導体を製造する方法に関して、結晶性を制御する
手法としては特開昭61−241909号公報に記載されている
ように、エネルギービームを照射する半導体の下地の絶
縁体に溝を形成することで、特定の面方位の結晶を選択
的に作製する手法がある。2. Description of the Related Art With respect to a method of manufacturing a crystalline semiconductor by irradiating a semiconductor with an energy beam, a method of controlling the crystallinity is described in Japanese Patent Application Laid-Open No. 61-241909. There is a method of selectively forming a crystal having a specific plane orientation by forming a groove in an insulator underlying a semiconductor to be formed.
【0003】[0003]
【発明が解決しようとする課題】上記従来技術では下地
の絶縁膜の溝の段差が2000Åあり、この手法で作製
した結晶性半導体を、液晶表示装置の画素駆動もしくは
回路駆動用薄膜トランジスタに使用する場合、半導体を
除去した領域で、露出したこの段差によって金属配線の
切断が起きやすくなり、製造歩留まりが低下する。In the above-mentioned prior art, the step of the groove of the underlying insulating film is 2,000.degree., And the crystalline semiconductor manufactured by this method is used for a thin film transistor for driving a pixel or a circuit of a liquid crystal display device. In the region where the semiconductor is removed, the metal wiring is likely to be cut due to the exposed step, and the manufacturing yield is reduced.
【0004】[0004]
【課題を解決するための手段】上記課題を解決するため
本発明の特徴は、下地絶縁膜には手を加えず、レーザを
照射する半導体の表面を加工して、レーザ照射時に表面
に平行な温度勾配の成分がある一方向に生じる形状にす
ることにある。In order to solve the above-mentioned problems, the feature of the present invention is that the surface of a semiconductor to be irradiated with a laser is processed without modifying the underlying insulating film so that the surface is parallel to the surface when the laser is irradiated. The purpose of the present invention is to provide a shape in which a component of a temperature gradient is generated in one direction.
【0005】[0005]
【発明の実施の形態】以下、本発明について説明した第
一実施例について図面を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
【0006】図1Aに示すようにガラス基板1上にテト
ラエチルオルソシリケイト(TEOS)と酸素ガスを原料と
したプラズマCVD法で下地酸化シリコン膜2を形成す
る。その上にジシランを原料ガスとした減圧CVD法で
70nmの非晶質シリコン3を成膜する。次に図1Bが
示すようにフォトリソグラフィー法と4フッ化メタンと
酸素ガスを用いた異方性ドライエッチングにより深さ2
0nm,幅1μmの溝を1ミクロンピッチで形成する。As shown in FIG. 1A, an underlying silicon oxide film 2 is formed on a glass substrate 1 by a plasma CVD method using tetraethylorthosilicate (TEOS) and oxygen gas as raw materials. A 70 nm-thick amorphous silicon film 3 is formed thereon by a low pressure CVD method using disilane as a source gas. Next, as shown in FIG. 1B, a photolithography method and anisotropic dry etching using methane tetrafluoride and oxygen gas are performed to a depth of 2
A groove having a thickness of 0 nm and a width of 1 μm is formed at a pitch of 1 μm.
【0007】そして、図1Cが示すようにエネルギー密
度が450mJ/cm2 のXeClエキシマレーザ4を非
晶質シリコン3に照射すると、非晶質シリコン3の膜厚
が70nmと50nmの隣あう領域で膜厚の差からくる
熱容量の違いで、溶融時に温度差が生じ基板に対して平
行な温度勾配が生じる。When the XeCl excimer laser 4 having an energy density of 450 mJ / cm 2 is irradiated on the amorphous silicon 3 as shown in FIG. Due to the difference in heat capacity resulting from the difference in film thickness, a temperature difference occurs during melting, and a temperature gradient parallel to the substrate occurs.
【0008】冷却時に結晶成長はこの温度勾配に平行な
方向に起るので、図1Dが示すように結晶は下地基板に
平行に成長し、垂直方向に成長する場合と異なり下地酸
化シリコン膜2との界面や表面で成長が止められること
はないので、結晶粒径が1μmと大きい高品質な多結晶
シリコン5が形成できる。Since crystal growth occurs in the direction parallel to this temperature gradient during cooling, the crystal grows parallel to the underlying substrate as shown in FIG. The growth is not stopped at the interface or the surface of the high-quality polycrystalline silicon 5 having a large crystal grain size of 1 μm.
【0009】この多結晶シリコン5の表面形状を原子間
力顕微鏡(AFM)で調査すると図2が示すように、レ
ーザ照射により表面の段差は20nmから10nmに減
少している。この段差は、表面を加工しない場合に生じ
る50nm程度の凹凸と比較して、大幅に小さくなって
いる。加工による段差が減少したのは、シリコンが溶融
再結晶化する際に、表面張力が若干働いたためと考えら
れる。また、従来と異なり、結晶が下地基板に対して平
行に成長すると、大きな突起の成長が抑制されると考え
られる。When the surface shape of the polycrystalline silicon 5 is examined with an atomic force microscope (AFM), as shown in FIG. 2, the step on the surface is reduced from 20 nm to 10 nm by laser irradiation. This step is much smaller than the unevenness of about 50 nm that occurs when the surface is not processed. It is probable that the step due to the processing was reduced because a slight surface tension acted when the silicon was melted and recrystallized. Also, unlike the conventional case, when the crystal grows in parallel with the underlying substrate, it is considered that the growth of large projections is suppressed.
【0010】このように本発明によって、結晶粒径の大
きい品質の良い結晶性半導体を製造できる。なお上記実
施例では、非晶質シリコン3の表面形状を深さ20n
m、幅1μmの溝が1ミクロンピッチで並んだものとし
たが、エネルギービーム照射時に半導体の下地基板に対
して平行な温度勾配の成分がある一方向に生じさせうる
形状であれば、その形状の種類は限定されるものではな
い。また本発明はシリコンのみならず、エネルギービー
ムの照射によって溶融再結晶化する半導体材料であれ
ば、その種類を選ばない。As described above, according to the present invention, a high-quality crystalline semiconductor having a large crystal grain size can be manufactured. In the above embodiment, the surface shape of the amorphous silicon 3 is set to a depth of 20 n.
Although grooves having a width of 1 μm and a width of 1 μm are arranged at a pitch of 1 μm, the shape may be any shape that can generate a temperature gradient component parallel to a semiconductor base substrate in one direction when irradiated with an energy beam. Is not limited. In addition, the present invention is not limited to silicon, and may be any semiconductor material that can be melted and recrystallized by irradiation with an energy beam.
【0011】次に本発明をコプレナー構造でn型の薄膜
トランジスタの製造に適用した第2実施例について説明
する。第1実施例で説明した通り、図1に示したように
ガラス基板1上に下地酸化シリコン膜2,非晶質シリコ
ン膜3を成膜し、非晶質シリコン3の表面に深さ20n
m、幅1μmの溝を1ミクロンピッチで形成した後、X
eClエキシマレーザ4を照射して、多結晶シリコン5
を作製する。Next, a description will be given of a second embodiment in which the present invention is applied to the manufacture of an n-type thin film transistor having a coplanar structure. As described in the first embodiment, the base silicon oxide film 2 and the amorphous silicon film 3 are formed on the glass substrate 1 as shown in FIG.
After forming a groove having a width of 1 μm and a pitch of 1 μm, X
Irradiate with eCl excimer laser 4 to obtain polycrystalline silicon 5
Is prepared.
【0012】そして、図3Aが示すようにホトリソグラ
フィー法とドライエッチング法により、多結晶シリコン
5を島状にパターニングする。次いでTEOSと酸素ガ
スを原料としたプラズマCVD法で100nmの酸化シ
リコンからなるゲート絶縁膜6を成膜する。次いで、ス
パッタ法で100nmのニオブ(Nb)7を成膜する。
次に図3Bが示すようにホトリソグラフィー法とドライ
エッチング法により、ニオブ7とゲート絶縁膜6をエッ
チングしゲート電極8を形成する。次に図3Cが示すよ
うにプラズマドーピング法により不純物リン(P)を注
入した後、XeClエキシマレーザ4を照射して活性化し、
ソース領域9およびドレイン領域10を形成する。Then, as shown in FIG. 3A, the polycrystalline silicon 5 is patterned into an island shape by photolithography and dry etching. Next, a gate insulating film 6 made of 100 nm silicon oxide is formed by a plasma CVD method using TEOS and oxygen gas as raw materials. Next, a 100-nm niobium (Nb) 7 film is formed by a sputtering method.
Next, as shown in FIG. 3B, the gate electrode 8 is formed by etching the niobium 7 and the gate insulating film 6 by photolithography and dry etching. Next, as shown in FIG. 3C, after implanting impurity phosphorus (P) by a plasma doping method, it is activated by irradiation with a XeCl excimer laser 4,
A source region 9 and a drain region 10 are formed.
【0013】次に図3Dが示すように300nmの酸化
シリコンからなる保護膜11を成膜しホトリソグラフィ
ー法とドライエッチング法によりコンタクトホール12
をあける。次に図3Eが示すようにスパッタ法で300
nmのクロム(Cr)を成膜した後、ホトリソグラフィ
ー法とウェットエッチング法によりパターニングしてソ
ース電極13とドレイン電極14を形成して薄膜トラン
ジスタは完成する。Next, as shown in FIG. 3D, a protective film 11 made of silicon oxide having a thickness of 300 nm is formed, and contact holes 12 are formed by photolithography and dry etching.
Open. Next, as shown in FIG.
After forming a film of chromium (Cr) with a thickness of nm, the thin film transistor is completed by forming a source electrode 13 and a drain electrode 14 by patterning by photolithography and wet etching.
【0014】以上のように本発明による結晶粒径の大き
な高品質な多結晶シリコンを能動層に用いることによ
り、移動度が300cm2 /V・s以上の高性能薄膜トラ
ンジスタを製造できる。なお上記実施例では、薄膜トラ
ンジスタの構造をコプレナー型としたが、本発明は正ス
タガー構造や逆スタガー構造の薄膜トランジスタ等、適
用されるトランジスタのタイプを選ばない。As described above, by using high-quality polycrystalline silicon having a large crystal grain size according to the present invention for the active layer, a high-performance thin film transistor having a mobility of 300 cm 2 / V · s or more can be manufactured. In the above embodiment, the structure of the thin film transistor is a coplanar type. However, the present invention does not limit the type of a transistor to be applied, such as a thin film transistor having a forward stagger structure or a reverse stagger structure.
【0015】次に本発明による薄膜トランジスタをアク
ティブマトリクス型液晶表示装置の表示部画素の駆動素
子に適用した第三実施例について説明する。Next, a description will be given of a third embodiment in which the thin film transistor according to the present invention is applied to a drive element of a display pixel of an active matrix type liquid crystal display device.
【0016】図4は本発明の一実施例であるアクティブ
マトリクス型の液晶表示装置の構成を示す。同図では、
マトリクス状に配置された複数の液晶セル(LC)に対
して、それぞれ薄膜トランジスタ(TFT)を設け、こ
のTFTのスイッチング動作によって各液晶セルを駆動
するようにしたものである。ここで、ガラス基板1上で
横方向に並んだTFTの各ゲートから共通に引き出した
電極であるゲートラインG1〜GMに対して順次ゲート
電圧を印加し、各ゲートライン毎にゲートをオンしてい
く。FIG. 4 shows the configuration of an active matrix type liquid crystal display device according to an embodiment of the present invention. In the figure,
A thin film transistor (TFT) is provided for each of a plurality of liquid crystal cells (LC) arranged in a matrix, and each liquid crystal cell is driven by a switching operation of the TFT. Here, a gate voltage is sequentially applied to the gate lines G1 to GM, which are electrodes commonly extracted from the gates of the TFTs arranged in the horizontal direction on the glass substrate 1, and the gate is turned on for each gate line. Go.
【0017】一方、縦方向に並んだTFTの各ドレイン
から共通に引き出した電極であるドレインラインD1〜
DNに対して、上記オンされたゲートライン毎のデータ
電圧を順次印加し、各液晶セルに与えていく。一つの液
晶セルとTFTからなる一画素の平面構造を図5に示
す。さらに図5中の破線X−X′における断面構造を図
6に示す。On the other hand, drain lines D1 to D1, which are electrodes commonly extracted from the respective drains of the TFTs arranged in the vertical direction,
The data voltage for each of the turned on gate lines is sequentially applied to DN, and is applied to each liquid crystal cell. FIG. 5 shows a planar structure of one pixel including one liquid crystal cell and a TFT. FIG. 6 shows a cross-sectional structure taken along a broken line XX 'in FIG.
【0018】ドレイン配線Dとゲート配線Gの交点の近
くに形成されたTFTとそれにソース電極13を介して
接続された液晶セルLCが配置からなる。TFTの断面
構造は第二実施例とほぼ同じである。本構造は同実施例
に記載の製造方法により得られるが、前記のプロセスと
の変更点のみ記すと以下のようになる。ゲート配線Gを
ゲート電極8と同時に成膜,エッチング加工して形成し
た。A TFT formed near the intersection of the drain wiring D and the gate wiring G and a liquid crystal cell LC connected to the TFT via a source electrode 13 are arranged. The sectional structure of the TFT is almost the same as that of the second embodiment. This structure can be obtained by the manufacturing method described in the same embodiment, but only the points different from the above-described process are as follows. The gate wiring G was formed simultaneously with the gate electrode 8 by film formation and etching.
【0019】また、ソース,ドレイン電極13,14を
形成した後、SiNからなる層間絶縁膜15を成膜し
た。これを加工してソース電極13へのコンタクトホー
ルを開けた後、ITOを成膜しパターニングして画素電
極16を形成した。次に、この他液晶等TFT以外の部
分について以下に記す。After forming the source and drain electrodes 13 and 14, an interlayer insulating film 15 made of SiN was formed. After processing this to form a contact hole to the source electrode 13, ITO was deposited and patterned to form the pixel electrode 16. Next, other portions such as liquid crystal other than the TFT will be described below.
【0020】TN型液晶17はTFTを形成したガラス
基板と対向するガラス基板(対向基板)18間に封入さ
れる。対向基板上には不要な光線を遮蔽するためのブラ
ックマトリクス19とITO製の対向電極20が形成さ
れている。The TN liquid crystal 17 is sealed between a glass substrate on which a TFT is formed and a glass substrate (opposite substrate) 18 facing the TFT. On the counter substrate, a black matrix 19 for blocking unnecessary light rays and a counter electrode 20 made of ITO are formed.
【0021】液晶は、対向基板18の対向電極20とT
FT基板の画素電極16の間の電圧により駆動され、画
素ごとに表示する明度をかえて画素のマトリクス上で画
像を表示する。ガラス基板1,18のいずれにも光を偏
向させるための偏光板21が貼付けられている。この2
枚の偏向板の偏向軸を直交、又は平行配置させると、そ
れぞれノーマリーブラック,ノーマリーホワイトの表示
モードとなる。The liquid crystal is formed between the counter electrode 20 of the counter substrate 18 and the T.
It is driven by a voltage between the pixel electrodes 16 of the FT substrate, and displays an image on a pixel matrix by changing the brightness to be displayed for each pixel. A polarizing plate 21 for deflecting light is attached to each of the glass substrates 1 and 18. This 2
If the deflecting axes of the deflecting plates are arranged orthogonally or in parallel, the display modes are normally black and normally white, respectively.
【0022】また、液晶を配向させるための配向膜22
が、液晶と接する面すなわちガラス基板1側では層間絶
縁膜15と画素電極16の表面に、対向基板18側では
対向電極20の表面に塗布されている。配向膜は塗布後
に表面をラビング法により処理され、液晶分子を配向さ
せるための異方性を与えられている。Also, an alignment film 22 for aligning the liquid crystal.
However, it is applied to the surface of the interlayer insulating film 15 and the pixel electrode 16 on the surface in contact with the liquid crystal, that is, on the glass substrate 1 side, and on the surface of the counter electrode 20 on the counter substrate 18 side. The surface of the alignment film is treated by a rubbing method after coating to give anisotropy for aligning liquid crystal molecules.
【0023】このように本発明により製造したTFTを
アクティブマトリクス型液晶表示装置の表示部画素の駆
動素子として用いれば、能動層の移動度が大きい分、薄
膜トランジスタを小型化できるので、高精細かつ低消費
電力の液晶表示装置の製造が可能となる。また本発明に
よる薄膜トランジスタで周辺回路を構成すれば、額縁領
域の縮小により液晶表示装置を小型化できる。When the TFT manufactured according to the present invention is used as a driving element for a pixel in a display section of an active matrix type liquid crystal display device, the thin film transistor can be reduced in size due to the high mobility of the active layer, and thus high definition and low resolution can be achieved. It is possible to manufacture a liquid crystal display device with low power consumption. Further, when a peripheral circuit is formed by the thin film transistor according to the present invention, the size of the liquid crystal display device can be reduced by reducing the frame area.
【0024】[0024]
【発明の効果】本発明により、結晶粒径の大きい高品質
な結晶性薄膜半導体装置を製造できる。According to the present invention, a high quality crystalline thin film semiconductor device having a large crystal grain size can be manufactured.
【図1】本発明による半導体のレーザ光による結晶化法
を説明した図である。FIG. 1 is a diagram illustrating a crystallization method using a laser beam of a semiconductor according to the present invention.
【図2】本発明により作製した結晶性半導体の表面形状
をAFMで調べた結果を示した図である。FIG. 2 is a diagram showing a result of examining a surface shape of a crystalline semiconductor manufactured according to the present invention by AFM.
【図3】本発明を適用した薄膜トランジスタの製造プロ
セスを示す図である。FIG. 3 is a diagram showing a manufacturing process of a thin film transistor to which the present invention is applied.
【図4】本発明による薄膜トランジスタを画素駆動素子
に適用したアクティブマトリクス型の液晶表示装置の構
成を示す図である。FIG. 4 is a diagram showing a configuration of an active matrix type liquid crystal display device in which a thin film transistor according to the present invention is applied to a pixel driving element.
【図5】本発明による薄膜トランジスタを画素駆動素子
に適用した液晶表示装置の一画素の平面構造を示した図
である。FIG. 5 is a diagram showing a planar structure of one pixel of a liquid crystal display device in which a thin film transistor according to the present invention is applied to a pixel driving element.
【図6】本発明による薄膜トランジスタを画素駆動素子
に適用した液晶表示装置の一画素の断面を示した図であ
る。FIG. 6 is a diagram showing a cross section of one pixel of a liquid crystal display device in which a thin film transistor according to the present invention is applied to a pixel driving element.
1…ガラス基板、2…下地酸化シリコン膜、3…非晶質
シリコン、4…XeClエキシマレーザ、5…多結晶シリコ
ン、6…ゲート絶縁膜、7…ニオブ(Nb)、8…ゲー
ト電極、9…ソース領域、10…ドレイン領域、11…
保護膜、12…コンタクトホール、13…ソース電極、
14…ドレイン電極、15…層間絶縁膜、16…画素電
極、17…液晶、18…対向基板、19…ブラックマト
リクス、20…対向電極、21…偏光板、22…配向
膜。DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Underlying silicon oxide film, 3 ... Amorphous silicon, 4 ... XeCl excimer laser, 5 ... Polycrystalline silicon, 6 ... Gate insulating film, 7 ... Niobium (Nb), 8 ... Gate electrode, 9 ... source region, 10 ... drain region, 11 ...
Protective film, 12: contact hole, 13: source electrode,
14 drain electrode, 15 interlayer insulating film, 16 pixel electrode, 17 liquid crystal, 18 counter substrate, 19 black matrix, 20 counter electrode, 21 polarizing plate, 22 alignment film.
Claims (10)
結晶化させて結晶性半導体を作製する薄膜半導体装置の
製造方法において、エネルギービーム照射前の半導体表
面の形状をレーザ照射時に半導体の下地基板に対して平
行な温度勾配の成分がある一方向に生じる形状に加工す
ることを特徴とする薄膜半導体装置の製造方法。In a method of manufacturing a thin film semiconductor device in which a semiconductor is irradiated with an energy beam and melt-crystallized to produce a crystalline semiconductor, a semiconductor surface shape before the energy beam irradiation is applied to a semiconductor base substrate during laser irradiation. A method of manufacturing a thin film semiconductor device, comprising processing a shape in which a component of a temperature gradient parallel to one direction occurs in one direction.
結晶化させて結晶性半導体を作製する薄膜半導体装置の
製造方法において、エネルギービーム照射前の半導体表
面の形状をある基準位置に対して高い領域と低い領域が
ある一方向に交互に現れる形状に加工することを特徴と
する薄膜半導体装置の製造方法。2. A method for manufacturing a thin film semiconductor device in which a semiconductor is irradiated with an energy beam and melt-crystallized to produce a crystalline semiconductor, wherein the semiconductor surface shape before the energy beam irradiation is higher than a certain reference position. A thin film semiconductor device, which is formed into a shape that alternately appears in one direction with a low region.
結晶化させて結晶性半導体を作製する薄膜半導体装置の
製造方法において、エネルギービーム照射前の半導体表
面の形状をある基準位置に対して高い面と低い面がある
一方向に交互に現れる形状に加工することを特徴とする
薄膜半導体装置の製造方法。3. A method for manufacturing a thin film semiconductor device in which a semiconductor is irradiated with an energy beam and melt-crystallized to produce a crystalline semiconductor, wherein the shape of the semiconductor surface before the energy beam irradiation is higher than a certain reference position. A thin film semiconductor device, which is formed into a shape which alternately appears in one direction with a low surface.
結晶化させて結晶性半導体を作製する薄膜半導体装置の
製造方法において、エネルギービーム照射前の半導体表
面の形状をある基準位置に対して高い領域と低い領域が
ある一方向に周期性をもって交互に現れる形状に加工す
ることを特徴とする薄膜半導体装置の製造方法。4. A method for manufacturing a thin film semiconductor device in which a semiconductor is irradiated with an energy beam and melt-crystallized to produce a crystalline semiconductor, wherein the semiconductor surface shape before the energy beam irradiation is higher than a certain reference position. A thin film semiconductor device, which is formed into a shape that alternately appears in one direction with a low area having a low area.
結晶化させて結晶性半導体を作製する薄膜半導体装置の
製造方法において、エネルギービーム照射前の半導体表
面の形状をある基準位置に対して高い面と低い面がある
一方向に周期性をもって交互に現れる形状に加工するこ
とを特徴とする薄膜半導体装置の製造方法。5. A method for manufacturing a thin film semiconductor device in which a semiconductor is irradiated with an energy beam and melt-crystallized to produce a crystalline semiconductor, wherein the semiconductor surface shape before the energy beam irradiation is higher than a certain reference position. A thin film semiconductor device, which is formed so as to alternately appear in one direction with a low surface.
いて、半導体がシリコンであることを特徴とする薄膜半
導体装置の製造方法。6. The method according to claim 1, wherein the semiconductor is silicon.
電極、絶縁物からなるゲート絶縁膜、半導体からなる能
動層、半導体に不純物を注入して形成されたオーミック
コンタクト層および電気伝導物質からなるソース・ドレ
イン電極から構成される薄膜トランジスタの製造方法に
おいて、能動層の製造することを特徴とする請求項1な
いし6のいずれか1項記載の薄膜トランジスタの製造方
法。7. A gate electrode made of an electrically conductive material, a gate insulating film made of an insulator, an active layer made of a semiconductor, an ohmic contact layer formed by injecting impurities into a semiconductor, and an electrically conductive material on a supporting substrate. 7. The method for manufacturing a thin film transistor according to claim 1, wherein an active layer is manufactured in the method for manufacturing a thin film transistor including a source / drain electrode.
電極、絶縁物からなるゲート絶縁膜、半導体からなる能
動層、半導体に不純物を注入して形成されたオーミック
コンタクト層および電気伝導物質からなるソース・ドレ
イン電極から構成される薄膜トランジスタにおいて、能
動層の表面の形状がある基準位置に対して高い領域と低
い領域が少なくともある一方向に交互に現れる形状であ
ることを特徴とする薄膜トランジスタ。8. A gate electrode made of an electrically conductive material, a gate insulating film made of an insulator, an active layer made of a semiconductor, an ohmic contact layer formed by injecting impurities into a semiconductor, and an electrically conductive material on a supporting substrate. A thin film transistor comprising a source / drain electrode, wherein a shape of a surface of an active layer is higher and lower than a certain reference position at least in a certain direction alternately in one direction.
電極、絶縁物からなるゲート絶縁膜、半導体からなる能
動層、半導体に不純物を注入して形成されたオーミック
コンタクト層および電気伝導物質からなるソース・ドレ
イン電極から構成される薄膜トランジスタにおいて、能
動層の表面の形状がある基準位置に対して高い領域と低
い領域が少なくともある一方向に周期性をもって交互に
現れる形状であることを特徴とする薄膜トランジスタ。9. A gate electrode made of an electrically conductive material, a gate insulating film made of an insulator, an active layer made of a semiconductor, an ohmic contact layer formed by implanting impurities into a semiconductor, and an electrically conductive material on a supporting substrate. A thin film transistor comprising a source / drain electrode, wherein a shape of a surface of an active layer has a shape in which a high region and a low region with respect to a certain reference position alternately appear periodically in at least one direction. .
ランジスタを用いた液晶表示装置において、薄膜トラン
ジスタを使用していることを特徴とする請求項8又は9
項記載の液晶表示装置。10. A liquid crystal display device using a thin film transistor for driving a pixel or driving a peripheral circuit, wherein the thin film transistor is used.
The liquid crystal display device according to the item.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2175998A JPH11219905A (en) | 1998-02-03 | 1998-02-03 | Thin film semiconductor device, method for manufacturing the same, method for manufacturing thin film transistor, thin film transistor, and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2175998A JPH11219905A (en) | 1998-02-03 | 1998-02-03 | Thin film semiconductor device, method for manufacturing the same, method for manufacturing thin film transistor, thin film transistor, and liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11219905A true JPH11219905A (en) | 1999-08-10 |
Family
ID=12064004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2175998A Pending JPH11219905A (en) | 1998-02-03 | 1998-02-03 | Thin film semiconductor device, method for manufacturing the same, method for manufacturing thin film transistor, thin film transistor, and liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11219905A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7745822B2 (en) | 2003-06-27 | 2010-06-29 | Nec Corporation | Thin film transistor and thin film transistor substrate including a polycrystalline semiconductor thin film having a large heat capacity part and a small heat capacity part |
-
1998
- 1998-02-03 JP JP2175998A patent/JPH11219905A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7745822B2 (en) | 2003-06-27 | 2010-06-29 | Nec Corporation | Thin film transistor and thin film transistor substrate including a polycrystalline semiconductor thin film having a large heat capacity part and a small heat capacity part |
| US8017507B2 (en) | 2003-06-27 | 2011-09-13 | Nec Corporation | Method of manufacturing a polycrystalline semiconductor thin film |
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