JPH11161467A - Data transfer control device - Google Patents

Abstract

(57) [Problem] To provide a data transfer control device capable of efficiently using a memory without delaying data transfer request processing. A memory includes a buffer controller.
Thus, two (first BLK, second BLK) first-in first-out memories (FIFOs) are caused to function. The data controller unit 4 has a function part that outputs a value indicating the remaining memory amount (transferable amount) by subtracting the number of valid data from the boundary pointer value. Then, the remaining memory capacity is compared with the packet size A. This comparison result is given to the first write control unit 3A. The first write control unit 3A returns a Busy signal to the data write request source based on the comparison result. That is, if the packet size of the received data is larger than the remaining amount of memory, the write control unit 3A issues a Busy signal. In the following cases, the write control unit 3A performs a process of transferring the received data to the first BLK. . Thereby, the memory 2
The overflow can be prevented beforehand while allowing a to function as two first-in first-out memories (FIFO).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device using a first-in first-out memory (FIFO).

[0002]

2. Description of the Related Art Japanese Patent Publication No. 3-75906 discloses a FI
There is disclosed a buffer memory control device in which the use efficiency of FO is improved. This device reads / writes buffer memory
A data transfer request signal is output when the count value of the counter is increased or decreased in response to the write command and the amount of data in the buffer memory becomes equal to or less than a certain value, and
In order to be able to correspond to the main storage device of the interleave configuration,
The counter value of the counter can be added by the number of interleaving stages.

[0003] Japanese Patent Publication No. 7-77881 discloses an information transmission method when data is transferred using a transfer buffer. This method acquires the status of the transfer buffer in data transfer, the source knows this status, determines whether the destination can receive, and waits for data transfer until the source becomes available. Technology.

[0004]

However, according to the technique disclosed in Japanese Patent Publication No. 3-75906, when a format such as packet data is predetermined in one or more types and it is necessary to perform processing in packet units,
If the above-mentioned fixed value is smaller than the data size of the packet, an overflow will be found after writing data halfway, and the data transfer request processing may be delayed. Further, if data reading processing is performed before packet data is stored in the buffer memory, there is a disadvantage that an underflow may occur on the data reading side.

The technique disclosed in Japanese Patent Publication No. 7-77881 cannot cope with a case where a transfer source is configured to transfer write data continuously, such as a serial bus interface. There is a disadvantage that.

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention improves the use efficiency of a buffer memory, does not delay data transfer request processing, and allows a data transfer source to transfer write data continuously. It is an object of the present invention to provide a data transfer control device that can cope with the case where the data transfer control device is configured as follows.

[0007]

In order to solve the above-mentioned problems, a data transfer control device according to the present invention is provided between a data transfer source and a data transfer destination to write transfer data into a buffer memory. A data transfer control device for performing a process of reading data from a buffer memory, wherein a boundary pointer for holding an address indicating a boundary between the buffer memory and the one FIFO block is provided for the buffer memory to function as two FIFO blocks. A first counter incremented for each write and decremented for each read, and a second counter provided for the other FIFO block, decremented for each write and incremented for each read, The lower address of the buffer memory is set to the start address for one FIFO block. A first write / read control means for accessing to the address indicated by the boundary pointer and,
For the other FIFO block, the upper address of the buffer memory is used as a start address and the boundary pointer +
And second write / read control means for accessing the address indicated by 1.

According to the above configuration, the buffer memory can function as two FIFO blocks, and in accessing each FIFO block for such a function, one of the FIFO blocks starts from the lower address. And the other FIFO block performs the increment operation from the upper address, so that the circuit configuration of the write / read control means can be less complicated.

A first calculating means for calculating a data storable amount in one FIFO block from a value of the first counter and a value of the boundary pointer; a value of the second counter, the boundary pointer and a buffer; Second calculating means for calculating a data storable amount in the other FIFO block from a value based on the last address of the memory;
Means for extracting a data size in a format of transfer data to be written, first comparing means for comparing the data storable amount of the one FIFO block with the data size, and data storable of the other FIFO block Second comparison means for comparing the amount with the data size, wherein the first write / read control means and the second write / read control means are capable of writing based on the respective comparison results It may be configured to determine whether or not it is possible.

According to the above configuration, it is determined whether or not an overflow occurs before actually writing the transfer data to the buffer memory, and when it is determined that the overflow does not occur, the writing process is performed. It becomes possible. Therefore, even when a format such as packet data is determined and processing of a packet is required, the data can be reliably written to the buffer memory. That is, an overflow does not occur during the data writing and the data transfer processing is not interrupted (the meaningless access to the buffer memory is performed), and the data transfer processing speed can be improved.

Means for extracting the data size in the format of the transfer data to be written, first adding means for adding the value of the first counter and the data size, and means for adding the value of the second counter to the value of the second counter. A second adding means for adding the data size; and a first adding means for comparing an addition result of the first adding means with a value based on the boundary pointer.
, And second comparing means for comparing the addition result of the second adding means with a value based on the boundary pointer and the last address of the buffer memory, wherein the first write / read control is performed. The means and the second write / read control means may be configured to determine writable / impossible based on the respective comparison results.

According to the above configuration, it is determined whether or not an overflow occurs before actually writing the transfer data to the buffer memory, and when it is determined that the overflow does not occur, the writing process is performed. It becomes possible. Therefore, even when a format such as packet data is determined and processing of a packet is required, the data can be reliably written to the buffer memory. That is, an overflow does not occur during the data writing and the data transfer processing is not interrupted (the meaningless access to the buffer memory is performed), and the data transfer processing speed can be improved.

[0013] First boundary address holding means for detecting the maximum address of valid data stored in the one FIFO block and storing the same as a first boundary address, and stored in the other FIFO block. Second boundary address holding means for detecting a minimum address of valid data and holding the same as a second boundary address, wherein the first write / read control means includes a write pointer value indicating the write address. Is equal to the second boundary address, the write pointer value is
When the write pointer value indicating the write address coincides with the first boundary address, the second write / read control unit returns the write pointer value to the other FIFO block. It may be configured to return to the start address.

According to the above configuration, the size of each FIFO block dynamically fluctuates in accordance with the use status of the FIFO block, thereby increasing the efficiency of memory use and improving the system throughput.

[0015] A first limit means capable of externally setting a limit value of a value which can be taken as the first boundary address, and a limit value of a value which can be taken as a second boundary address are set externally. Second limit means capable of holding, wherein the first boundary address holding means sets the limit value to the first value when the maximum address is lower than the limit value.
The second boundary address holding means may be configured to hold the limit value as a second boundary address when the minimum address exceeds the limit value.

According to the above configuration, the size of each FIFO block dynamically fluctuates in accordance with the use condition thereof, and a minimum area as each FIFO block is secured, so that access to each FIFO block is restricted. Can be guaranteed.

[0017]

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

The memory 2a is caused to function as two (first BLK, second BLK) first-in first-out memories (FIFO) by the buffer controller 2. That is, the buffer controller 2 controls to access the memory 2a like two FIFOs. In this example, the first BL
K is accessed from the lowest address of the memory 2a to the boundary address, and the second BLK is accessed from the highest address of the memory 2a to the boundary address + 1. Memory 2
a and a data write request source (for example, an interface connected to a communication bus) which is a data transfer source, two write control units 3A and 3B are interposed between the memory 2a and the data transfer destination. Some data read requester (eg, host)
The read control units 1A and 1B are interposed between the two. Note that the data bus connected to the memory 2a is not shown in the figure.

The write control units 3A and 3B are provided with a write pointer 3A which is incremented each time data is written.
a, 3Ba, and generates write addresses for the first BLK and the second BLK, respectively, generates data write timings, and supplies them to the buffer controller 2. Then, if the write request (Writereq) as a write request from the data write request source is permitted to write data to the first BLK and the second BLK, the received data is written to the first BLK and the second BLK. If they are transferred and writing is not permitted, a Busy signal is returned to the data write request source. The determination as to whether or not to permit data writing is made based on the output of the data controller 4 described later.

A data bus (not shown) connected to a data write request source is connected to the packet size detectors 3Ab and 3Bb provided in the write controllers 3A and 3B. Extract the packet size from the write data. FIG. 11 is an explanatory diagram showing a format example of the write data (IEEE 1394 PACKET). 1394 PACKET is a 32-bit (1 quadlet)
) Unit, as shown in FIG.
The packet size is constant without data field (5 quadlet including CRC);
A data field (data) as shown in FIG.
field), the packet size is classified as non-constant. The aforementioned packet size detectors 3Ab and 3B
b shows “tcode: ttransaction” in the first quadlet of the write data in the format of FIG.
The packet size is detected by decoding “code, 4 bits”. For the write data in the format of FIG. 11B, “datalength: 16 bits, bytes” in the fourth quadlet
The packet size is detected by referring to "unit".

The read control units 1A and 1B are provided with a read pointer 1A which is incremented each time data is read.
a, 1Bb, respectively, generates read addresses for the first BLK and the second BLK, generates data read timings, and supplies them to the buffer controller 2. If the read request (Readreq), which is a read request from the data read request side, is permitted to read data from the first BLK and the second BLK, permission of data read from the first BLK and the second BLK is indicated. Return the ReadRdy signal to the host side.
Delay the return of the adRdy signal.

The boundary controller 5 comprises a first BLK and a second BLK.
A boundary pointer 5a indicating the boundary of the BLK,
Control the boundary between the LK and the second BLK.

FIG. 2 is a block diagram showing a specific configuration of the data controller unit 4. Then, FIG.
Is a circuit corresponding to the first BLK and the first write control unit 3A, and the component of FIG. 13B is a circuit corresponding to the second BLK and the second write control unit 3B.

In FIG. 2A, the data counting unit 1
Reference numeral 7 is connected to the read control unit 1A and the write control unit 3A.
Is decremented each time a read access to the buffer controller 2A occurs, and is incremented each time a write access to the buffer controller 2 occurs in the write controller 3A. The counter initial value is “000”
The count value in the data counting unit 17 indicates the number of valid data stored in the first BLK by the above-described increment and decrement processing.

The subtracter 18 has one input terminal connected to the count output unit of the data count unit 17 and the other input terminal connected to the output unit of the boundary pointer 5a. By subtracting the number of valid data from the value + 1 (indicating the maximum storage capacity in the first BLK), a value indicating the remaining memory amount (transferable amount) is output.

The comparator 19 has one input terminal connected to the output unit of the subtractor 18 and the other input terminal connected to the output unit of the packet size detection unit 3Ab. And the packet size A. The comparison result A1 is provided to the first write control unit 3A, and the first write control unit 3A performs the Busy based on the comparison result A1.
The signal is returned to the data write request source. That is, if the packet size of the received data is larger than the remaining amount of memory, the write control unit 3A issues a Busy signal. In the following cases, the write control unit 3A performs a process of transferring the received data to the first BLK. . Thereby, overflow can be prevented beforehand.

The adder 20 has one input terminal connected to the count output unit of the data count unit 17 and the other input terminal connected to the output unit of the packet size detection unit 3Ab. By adding the size A and the number of valid data, the expected number of valid data when packet data is stored is output.

The comparator 21 has one input terminal connected to the output of the boundary pointer 5a and the other input terminal connected to the output of the adder 20. The maximum storage capacity in the first BLK) and the planned number of valid data. This comparison result A
2 is given to the first write control unit 3A, and the first write control unit 3A returns a Busy signal to the data write request source based on the comparison result A2. That is, the write control unit 3A issues a Busy signal when the planned number of valid data exceeds the boundary pointer value + 1.
The process of transferring the received data to the BLK will be performed. Thereby, overflow can be prevented beforehand.

Although the comparison results A1 and A2 are output in FIG. 2A, in practice, any one of the comparison results may be output.

In FIG. 2B, the data counting unit 2
6 is connected to the read control unit 1B and the write control unit 3B, and the buffer controller 2 is connected to the read control unit 1B.
Is decremented each time a read access to the buffer controller 2 occurs, and is incremented each time a write access to the buffer controller 2 occurs in the write control unit 3B. The counter initial value is “000”
0h ". The count value in the data count unit 26 indicates the number of valid data stored in the second BLK by the above-described increment and decrement processing.

The subtracter 22 has one input terminal connected to the count output portion of the data counting portion 26 and the other input terminal connected to the output portion of the boundary controller 5. Is the maximum address of "FF
By subtracting the number of valid data from the value (indicating the maximum storage capacity in the second BLK) obtained by subtracting the boundary pointer value from "FFh"("FFFFh" for simplicity of explanation), the remaining memory amount (transferable amount) ) Is output.

The comparator 23 has one input terminal connected to the output unit of the subtractor 22 and the other input terminal connected to the output unit of the packet size detection unit 3Bb. And the packet size B. The comparison result B1 is provided to the second write control unit 3B, and the second write control unit 3B performs the Busy operation based on the comparison result B1.
The signal is returned to the data write request source. That is, if the packet size of the received data is larger than the remaining memory amount, the write control unit 3B issues a Busy signal, and if not, performs the process of transferring the received data to the second BLK. . Thereby, overflow can be prevented beforehand.

The adder 24 has one input terminal connected to the count output unit of the data count unit 26 and the other input terminal connected to the packet size detection unit 3Bb output unit. By adding the size B and the number of valid data, the expected number of valid data when packet data is stored is output.

The comparator 25 has one input terminal connected to the output of the boundary controller 5 and the other input terminal connected to the output of the adder 24.
The value obtained by subtracting the boundary pointer value from FFh "is compared with the expected number of valid data. The comparison result B2 is given to the second write control unit 3B, and the second write control unit 3B compares the comparison result B2 In other words, the write control unit 3B returns the Busy signal to the source of the data write request based on the maximum valid storage capacity in the second BLK.
A Busy signal will be output, and if
The transfer processing of the received data is performed. Thereby, overflow can be prevented beforehand.

In FIG. 2B, the comparison results B1 and B2 are output, but in practice, any one of the comparison results may be output.

(Embodiment 2) The overall configuration is the same as in FIG. 1, but the boundary controller 5 is configured as shown in FIG. 3, and the data controller 4 is configured as shown in FIG. In FIG. 4, for convenience of explanation, FIG.
The same functional portions as those described above are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 3, the first boundary pointer 5a ₁
Indicates the maximum address of valid data written in the first BLK. First limit pointer 5a ₂ holds the address that the user has arbitrarily set. Second boundary pointer 5a ₃ shows the minimum address of the valid data written to the 2BLK. Second limit pointer 5a ₄ holds the address that the user has arbitrarily set.

FIG. 5 is a flowchart showing a method for generating the boundary address A. First, the write pointer value A and the read pointer value A are compared (step 1). If the larger of the two values are equal to or write pointer value A, the first value of the boundary pointer 5a ₁ put the write pointer value A-1 (Step 3), the flow returns to step 1. On the other hand, if the direction of the write pointer value A is small, it is determined whether the read pointer value A-1 is equal to the first value of the boundary pointer 5a ₁ (Step 2). If they do not match, proceed to step 1; if they do match, step 3
Proceed to. With this processing, the first boundary pointer 5a
The value of ₁ becomes the boundary address A.

FIG. 6 is a flowchart showing a method of generating the boundary address B. First, the write pointer value B and the read pointer value B are compared (step 4). If towards the two values are equal to or write pointer value B is small, as the value of the second boundary pointer 5a ₂ placed write pointer value B + 1 (step 6), the flow returns to step 4. On the other hand, if the direction of the write pointer value B is large, it is determined whether or not a read pointer value B + 1 is equal to the second value of the boundary pointer 5a ₂ (Step 5). If they do not match, proceed to step 4; if they do match, step 6
Proceed to. With this processing, the second boundary pointer 5a
The value of ₂ becomes the boundary address B.

The determination as to whether writing is possible for the first BLK and the second BLK is made based on the comparison result output shown in FIG. The difference between FIG. 4 and FIG. 2 is that the value input to one input terminal of the subtractor 18 is the pointer value B.
And the value input to one input terminal of the subtractor 22 is FFFFh-boundary pointer value A.

FIG. 7 is a flowchart showing a process for determining the write pointer 3Aa related to the first BLK.
First, it is determined whether or not data can be written to the first BLK (step 11). If not, the process proceeds to step 11, if possible, data is written and the write pointer 3Aa
Is incremented (step 12). Next, it is determined whether the value of the write pointer 3Aa matches the value of the second boundary pointer 5a ₃ (step 13), the process proceeds to step 11 if no match, the value its initial value of the write pointer 3Aa if matches "0000h".

FIG. 8 is a flowchart showing a process for determining the write pointer 3Ba involved in the second BLK.
First, it is determined whether data can be written to the second BLK (step 15). If not, the process proceeds to step 15; if possible, data is written and the write pointer 3Ba is written.
Is decremented (step 16). Next, it is determined whether the value of the write pointer 3Ba matches the first value of the boundary pointer 5a ₁ (step 17), the process proceeds to step 15 if no match, the value its initial value of the write pointer 3Ba if matches "FFFFh".

By performing the above processing,
One memory 2a is divided into two FIFOs (first BLK, second
When used as BLK), those boundaries can be made variable and it is possible to cope with a change in access. Therefore, the use efficiency of the memory 2a is improved.

In the above example, the first BLK and the second BK
In the LK, for example, the first BLK may use all areas of the memory 2a. In some cases, it is desirable to secure a minimum constant area as the first BLK and the second BLK. To cope with such a case, as shown in FIG. 3, it is provided with a first limit pointer 5a ₂ and a second limit pointer 5a _4. The user can use these first limit pointers 5a ₂
It can be set to any value with respect to and the second limit pointer 5a _4.

FIGS. 9 and 10 show examples of control for generating a boundary address when the first limit pointer 5a ₂ and the second limit pointer 5a ₄ are used. FIG. 9 shows the first B
5 shows the process for LK, and steps 31 and 32 are added to FIG. FIG. 10 shows the process for the second BLK.
3, 34 are added. Such additional steps, the value of the first limit pointer 5a ₂ is placed as the first value of the boundary pointer 5a ₁ (step 31), also,
So that the value of the second limit pointer 5a ₄ is placed as a second value of the boundary pointer 5a ₂ (Step 3
3).

[0046] Then, if the write pointer value A first limit pointer 5a ₂ value or more, the first boundary pointer 5a ₁ value (boundary address A) is dynamically by the processing of steps 1, 2 and 3 described above will vary, the write pointer value a falls below the value of the first limit pointer 5a _2, the
The first value of the boundary pointer 5a ₁ becomes possible to hold the value at step 31, the minimum constant region is secured as the 1BLK.

Further, if the write pointer value B is less than the value of the second limit pointer 5a _4, the value of the second boundary pointer 5a ₃ (boundary address B) is dynamically by the processing of steps 4, 5, and 6 mentioned above will vary, the write pointer value B exceeds the value of the second limit pointer 5a _4, the
The value of the second boundary pointer 5a ₃ becomes possible to hold the value at step 33, the minimum constant region is secured as the 2BLK.

[0048]

According to the above configuration, the buffer memory can function as two FIFO blocks with a relatively simple configuration. Then, in each of these two FIFO blocks, it is possible to determine in advance whether writing is possible or not, and it is possible to prevent a situation such as overflow. Also, the boundary between the two FIFO blocks can be dynamically changed to improve the memory use efficiency. In addition, even when the boundary is dynamically changed, an effect is obtained in that access can be guaranteed by securing a minimum area for each FIFO block.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transfer control device of the present invention.

FIG. 2 is a block diagram showing a specific configuration (in the case of Embodiment 1) of the data controller of FIG. 1;

FIG. 3 is a block diagram showing a specific configuration (in the case of Embodiment 2) of the boundary controller of FIG. 1;

FIG. 4 is a block diagram showing a specific configuration (in the case of Embodiment 2) of the data controller of FIG. 1;

FIG. 5 is a flowchart showing a method of generating a boundary address A according to the present invention.

FIG. 6 is a flowchart illustrating a method of generating a boundary address B according to the present invention.

FIG. 7 is a flowchart illustrating a process of determining a write pointer value related to the first BLK according to the present invention.

FIG. 8 is a flowchart showing a process of determining a write pointer value related to the second BLK of the present invention.

FIG. 9 is a flowchart illustrating a control example of boundary address generation when the value of the first limit pointer is used according to the present invention.

FIG. 10 is a flowchart showing a control example of boundary address generation when the value of the second limit pointer is used according to the present invention.

FIGS. 11A and 11B are format examples of write data (IEEE 1394 PACKE); FIGS.
It is explanatory drawing which shows T).

[Explanation of symbols]

 1A First Read Control Unit 1B Second Read Control Unit 2 Buffer Controller 2a Buffer Memory 3A First Write Control Unit 3B Second Write Control Unit 4 Data Controller 5 Boundary Controller 5a Boundary Pointer

Claims (5)

[Claims] A process for interposing a data transfer source and a data transfer destination to write transfer data to a buffer memory;
In a data transfer control device for performing a process of reading data from a buffer memory, a boundary pointer for holding an address indicating a boundary between the buffer memory and the one FIFO block is provided so that the buffer memory functions as two FIFO blocks; A first counter that is incremented for each write and decremented for each read, a second counter provided for the other FIFO block, decremented for each write, and incremented for each read; First write / read control means for accessing the address indicated by the boundary pointer using the lower address of the buffer memory as a start address for the FIFO block of the above, and the upper address of the buffer memory for the other FIFO block Address as the start address and the boundary And a second write / read control means for accessing up to an address +1 indicated by a pointer. 2. A first calculating means for calculating a data storable amount in one FIFO block from a value of the first counter and a value of the boundary pointer, and a value of the second counter and the boundary pointer. A second calculating means for calculating a data storable amount in the other FIFO block from a value based on the last address of the buffer memory and a means for extracting a data size in a format of transfer data to be written; A first comparing means for comparing the data storable amount of the FIFO block with the data size, and a second comparing means for comparing the data storable amount of the other FIFO block with the data size
And the first writing / reading control means and the second writing / reading control means are configured to determine writable / impossible based on the respective comparison results. The data transfer control device according to claim 1, wherein: 3. A means for extracting a data size in a format of transfer data to be written, a first adding means for adding the value of the first counter and the data size, and a value of the second counter Second adding means for adding the data size and the data size, first comparing means for comparing the addition result of the first adding means with a value based on the boundary pointer, and addition of the second adding means. Second comparing means for comparing a result with a value based on the boundary pointer and the last address of the buffer memory;
2. The writing / reading control means and the second writing / reading control means are configured to judge whether writing is possible or not based on respective comparison results. Data transfer control device. 4. A method for detecting a maximum address of valid data stored in said one FIFO block and storing the detected maximum address in the first FIFO block.
First boundary address holding means for holding the minimum address of valid data stored in the other FIFO block, and holding the same as a second boundary address. The first write / read control means, when the write pointer value indicating the write address matches the second boundary address, stores the write pointer value in one FIFO
When the write pointer value indicating the write address coincides with the first boundary address, the second write / read control unit returns the write pointer value to the other FIFO block. The data transfer control device according to claim 1, wherein the data transfer control device is configured to return to a start address. 5. A first limiter capable of externally setting a limit value of a value that can be taken as the first boundary address, and externally setting a limit value of a value that can be taken as a second boundary address. The first boundary address holding means holds the limit value as a first boundary address when the maximum address is lower than the limit value, and the second boundary address holds the second boundary address. 5. The data transfer control device according to claim 4, wherein the holding unit is configured to hold the limit value as a second boundary address when the minimum address exceeds the limit value.