JPH11145318A - Cps and its connection with socket - Google Patents
Cps and its connection with socketInfo
- Publication number
- JPH11145318A JPH11145318A JP30182197A JP30182197A JPH11145318A JP H11145318 A JPH11145318 A JP H11145318A JP 30182197 A JP30182197 A JP 30182197A JP 30182197 A JP30182197 A JP 30182197A JP H11145318 A JPH11145318 A JP H11145318A
- Authority
- JP
- Japan
- Prior art keywords
- socket
- csp
- socket pin
- connection
- electrical connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＣＰＳの電気的特
性検査及びバーンイン時におけるソケットとの接続に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to inspection of electrical characteristics of a CPS and connection with a socket at the time of burn-in.
【０００２】[0002]
【従来の技術】従来、ＬＳＩのような半導体装置の製造
は、シリコンウエハーに多数の集積回路を形成した後に
これをダイシングし、得られたチップをパッケージング
するのが一般的である。パッケージの形状は半導体装置
の用途に応じて多種多用であるが、近年の高密度実装に
対応するため、小型化、薄型化、ファイン・ピッチ化が
進んでいる。ＣＰＳ（Chip Scale Package）はそのよう
なパッケージの一種であって、使用頻度の高いものであ
る。2. Description of the Related Art Conventionally, in the manufacture of a semiconductor device such as an LSI, it is general to form a large number of integrated circuits on a silicon wafer, dice them, and package the obtained chips. Although there are various types of package shapes depending on the application of the semiconductor device, miniaturization, thinning, and fine pitch are progressing in order to respond to recent high-density mounting. CPS (Chip Scale Package) is a kind of such a package and is frequently used.
【０００３】パッケージングされた半導体装置は、通
常、電機的特性選別工程及びバーンイン工程に入り、そ
の性能をチェックされる。バーンインとは、パッケージ
ングされた半導体装置に温度、電圧、電気信号等のスト
レスを印加する加速寿命試験である。これらの試験工程
は、それを経ることによって最終製品の信頼性向上を図
るものである。[0003] The packaged semiconductor device usually undergoes an electrical characteristic selection process and a burn-in process, and its performance is checked. Burn-in is an accelerated life test in which a packaged semiconductor device is subjected to stress such as temperature, voltage, and electric signal. These test steps are intended to improve the reliability of the final product by passing through these test steps.
【０００４】このような試験工程においては、パッケー
ジングされた半導体装置を試験用の装置に実装するため
に、各種ソケットが使用されている。ＣＳＰにおいても
同様に、パッケージをソケットに装着して各種試験が行
われている。装着の実際の方法について図３を用いて以
下に説明する。ＣＰＳとソケットの電気的接続は、ＣＰ
Ｓ基板１１上のパッド１２及びソケットピン１４を介し
て得られる。従って適正な電気的接続を得るためには、
パッド１２とソケットピン１４の正確な位置合わせが必
要である。従来技術においては、パッド１２上にバンプ
１３を形成し、このバンプ１３にソケットピン１４を引
っかけ、かつ押し付けて位置合わせ及び電気的接続を行
っていた。すなわち、位置合わせおよび電気的接続はバ
ンプ１３の存在に負うものであった。[0004] In such a test process, various sockets are used to mount the packaged semiconductor device on a test device. Similarly, in the CSP, a package is mounted on a socket and various tests are performed. The actual mounting method will be described below with reference to FIG. The electrical connection between CPS and socket is CP
It is obtained via the pads 12 and the socket pins 14 on the S substrate 11. Therefore, in order to obtain a proper electrical connection,
Accurate alignment between the pad 12 and the socket pin 14 is required. In the prior art, a bump 13 is formed on a pad 12, and a socket pin 14 is hooked and pressed on the bump 13 to perform positioning and electrical connection. That is, the alignment and the electrical connection depend on the presence of the bump 13.
【０００５】[0005]
【発明が解決しようとする課題】しかし上記の方法にお
いては、バンプ１３にソケットピン１４を引っかけ、か
つ押し付ける操作を行う上で、その力加減の制御が難し
い点に問題があった。つまり、力が強すぎる場合にはバ
ンプ１３がパッド１２から脱落し、弱すぎる場合には電
気的接続が十分に得られない点に問題があった。However, in the above-mentioned method, there is a problem in that it is difficult to control the force in the operation of hooking and pressing the socket pin 14 on the bump 13. That is, if the force is too strong, the bump 13 falls off the pad 12, and if it is too weak, there is a problem in that sufficient electrical connection cannot be obtained.
【０００６】そこで、本発明の課題は、ソケットピンと
の正確な位置合わせ及び電気的接続が容易なＣＳＰを提
供することである。また、そのような特徴を有し、かつ
接続時のバンプ脱落が無い接続方法を提供することであ
る。SUMMARY OF THE INVENTION It is an object of the present invention to provide a CSP in which accurate positioning and electrical connection with a socket pin are easy. It is another object of the present invention to provide a connection method having such features and preventing the bumps from dropping off during connection.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
の、本発明のＣＳＰは、基板上にソケットピンと嵌合す
る凹部を有することを特徴とする。According to another aspect of the present invention, there is provided a CSP having a recess for fitting a socket pin on a substrate.
【０００８】また、本発明のＣＳＰは、基板上にソケッ
トピンと嵌合する貫通孔を有することを特徴とする。Further, the CSP of the present invention is characterized in that the CSP has a through-hole on a substrate, which is fitted with a socket pin.
【０００９】また、本発明のＣＳＰは、ソケットピンと
嵌合する部分の表面及びその外周囲にパッドを設けてな
ることを特徴とする。Further, the CSP of the present invention is characterized in that pads are provided on the surface of the portion to be fitted with the socket pin and on the outer periphery thereof.
【００１０】また、本発明のＣＳＰとソケットの接続方
法は、ＣＳＰ基板上へのバンプ形成前にソケットを接続
することを特徴とする。[0010] The method of connecting a CSP to a socket according to the present invention is characterized in that the socket is connected before bumps are formed on the CSP substrate.
【００１１】また、本発明のＣＳＰとソケットの接続方
法は、ＣＳＰ基板上に設けた凹部にソケットピンを嵌合
させることを特徴とする。[0011] The method of connecting a CSP to a socket according to the present invention is characterized in that socket pins are fitted into recesses provided on the CSP substrate.
【００１２】また、本発明のＣＳＰとソケットの接続方
法は、ＣＳＰ基板上に設けた貫通孔にソケットピンを嵌
合させることを特徴とする。Further, the method for connecting a CSP to a socket according to the present invention is characterized in that socket pins are fitted into through holes provided on the CSP board.
【００１３】また、本発明のＣＳＰとソケットの接続方
法は、ソケットピンとの嵌合部の表面およびその外周囲
にパッドを設けることを特徴とする。The method of connecting a CSP to a socket according to the present invention is characterized in that pads are provided on the surface of the fitting portion with the socket pin and on the outer periphery thereof.
【００１４】[0014]
【発明の実施の形態】本発明の一実施の形態を図１に示
すとともに以下に説明する。セラミック製又はエポキシ
樹脂製等のＣＳＰ基板１１の表面に凹部１５を設け、そ
の表面及び外周囲に導電性材料のパッド１２を形成す
る。パッド１２は、従来使用されている金、銅、ニッケ
ル等を用いる。パッド１２を形成した凹部１５にソケッ
トピン１４を嵌合することにより、確実な位置合わせ及
び電気的接続が可能になる。また、接続時にバンプを必
要としないので、バンプ脱落の恐れが無い。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention is shown in FIG. 1 and will be described below. A recess 15 is provided on the surface of a CSP substrate 11 made of ceramic or epoxy resin, and a pad 12 of a conductive material is formed on the surface and the outer periphery. The pad 12 is made of conventionally used gold, copper, nickel or the like. By fitting the socket pins 14 into the recesses 15 in which the pads 12 are formed, reliable positioning and electrical connection can be achieved. In addition, since no bump is required at the time of connection, there is no possibility that the bump will fall off.
【００１５】本発明の別の実施の形態について図２に示
すとともに以下に説明する。前述の場合と同様のＣＳＰ
基板１１の表面に貫通孔１６を設け、その表面及び外周
囲に導電性材料のパッド１２を形成する。この貫通孔１
６にソケットピン１４を嵌合することによって正確な位
置合わせおよび電気的接続が可能となる。また、バンプ
脱落の恐れが無い。Another embodiment of the present invention is shown in FIG. 2 and will be described below. CSP same as above
A through hole 16 is provided on the surface of the substrate 11, and a pad 12 of a conductive material is formed on the surface and the outer periphery. This through hole 1
By fitting the socket pin 14 into the connector 6, accurate positioning and electrical connection can be achieved. Also, there is no possibility of bumps falling off.
【００１６】[0016]
【発明の効果】本発明によれば、ＣＳＰとソケットの正
確な位置合わせ及び電気的接続が容易になる。また、接
続時のバンプ脱落による製品不良が無くなり、生産性が
向上する。According to the present invention, accurate positioning and electrical connection between the CSP and the socket are facilitated. In addition, product defects due to bumps falling off during connection are eliminated, and productivity is improved.
【図１】 本発明の一実施の形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】 本発明の別の実施形態を示す断面図である。FIG. 2 is a cross-sectional view showing another embodiment of the present invention.
【図３】 従来の方法を示す断面図である。FIG. 3 is a sectional view showing a conventional method.
１１ ＣＳＰ基板 １２ パッド １３ バンプ １４ ソケットピン １５ 凹部 １６ 貫通孔 11 CSP board 12 pad 13 bump 14 socket pin 15 recess 16 through hole
Claims (7)
有することを特徴とするＣＳＰ。1. A CSP having a recess on a substrate for fitting with a socket pin.
を有することを特徴とするＣＳＰ。2. A CSP having a through hole on a substrate for fitting a socket pin.
その外周囲にパッドを設けてなることを特徴とする請求
項１又は請求項２に記載のＣＳＰ。3. The CSP according to claim 1, wherein a pad is provided on a surface of a portion to be fitted with the socket pin and an outer periphery thereof.
トを接続することを特徴とするＣＳＰとソケットの接続
方法。4. A method for connecting a CSP and a socket, wherein the socket is connected before bumps are formed on the CSP substrate.
ンを嵌合させることを特徴とする請求項４に記載のＣＳ
Ｐとソケットの接続方法。5. The CS according to claim 4, wherein a socket pin is fitted into a recess provided on the CSP board.
Connection method between P and socket.
ピンを嵌合させることを特徴とする請求項４に記載のＣ
ＳＰとソケットの接続方法。6. The C according to claim 4, wherein socket pins are fitted into through holes provided on the CSP board.
How to connect SP and socket.
の外周囲にパッドを設けることを特徴とする請求項４〜
６に記載のＣＳＰとソケットの接続方法。7. A pad is provided on a surface of a fitting portion to be fitted to a socket pin and on an outer periphery thereof.
6. The method for connecting a CSP and a socket according to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30182197A JPH11145318A (en) | 1997-11-04 | 1997-11-04 | Cps and its connection with socket |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30182197A JPH11145318A (en) | 1997-11-04 | 1997-11-04 | Cps and its connection with socket |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11145318A true JPH11145318A (en) | 1999-05-28 |
Family
ID=17901578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30182197A Pending JPH11145318A (en) | 1997-11-04 | 1997-11-04 | Cps and its connection with socket |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11145318A (en) |
-
1997
- 1997-11-04 JP JP30182197A patent/JPH11145318A/en active Pending
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