JPH11103251A - Frequency synthesizer with correction circuit - Google Patents

Abstract

(57) [Summary] (With correction) [PROBLEMS] To provide a frequency synthesizer capable of accurately compensating a ripple current. In a frequency synthesizer according to the present invention, a control signal output from a charge pump circuit includes a compensation circuit.
When superimposing the compensation current output from 7 and canceling the ripple current, the amount of the compensation current changes according to the reference voltage input from the correction circuit 10. Since the amount of ripple current is proportional to the amount of output current of the charge pump circuit 35, if the magnitude of the reference voltage is configured to change according to the change in the amount of output current,
The charge amount of the compensation current follows the change in the charge amount of the ripple current, and can be accurately canceled. In the case where the generation of the ripple current is performed by charging and discharging the first capacitor 46, if the generation of the reference voltage is performed by charging or discharging the second capacitor 23 with the output current, the influence of the capacitance change disappears, Be able to cancel accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the technical field of frequency synthesizers, and more particularly to a frequency synthesizer capable of accurately compensating for a ripple current.

[0002]

2. Description of the Related Art A cellular telephone is a frequency multi-channel access system, and a frequency synthesizer capable of high-speed lock-up is required to shift a used frequency to an empty channel.

[0005] Reference numeral 101 in FIG. 5 shows a prior art of such a frequency synthesizer.
An LL circuit is used.

The frequency synthesizer 101 is provided in a semiconductor integrated circuit device constituting a transmitting / receiving circuit of a cellular telephone, and includes an oscillator 131, a frequency divider 132, a reference clock signal generator 133, a phase comparator 134, a charge pump. A circuit 135, a low-pass filter 136, a compensation circuit 137, and a control circuit 138 are provided. Oscillator 131
Outputs the external signal OUT, and outputs the external signal OU.
T is a frequency divider 132 and the frequency synthesizer 101
Are input to other circuits in the semiconductor integrated circuit device provided with

The frequency divider 132 divides the frequency of the input external output signal OUT to generate a comparison signal.
, And the phase comparator 134 includes a frequency divider 132
Comparison signal input from the reference clock signal generator 1
33. Compare the phase of the reference clock signal input from 33,
The charge pump circuit 135 is controlled to generate a control signal, and the control signal is output to the oscillator 131 via the low-pass filter 136.

The oscillator 131 operates so as to change the frequency of the external output signal OUT according to the input control signal and to match the phase of the comparison signal with the phase of the reference clock signal. As a result, the frequency of the external signal OUT becomes a value obtained by multiplying the frequency of the reference clock signal by the frequency division value of the frequency divider 132.

[0007] The frequency divider 132 is controlled by a control circuit 138, and is configured so that the frequency division value changes periodically.
In the case of kHz, the frequency division value is 5000 in the period of 7 cycles (35 μsec) and 5 in the period of 1 cycle (5 μsec).
In the case of 001, the average division value obtained by averaging eight periods is 50
0.125 (= 5000 + ／), and the frequency of the external output signal OUT is locked at 1000025 kHz, which is twice the average frequency division value of the reference clock signal.

If the frequency division value of two of the eight periods is 4001, the average frequency division value is 400.25, and the frequency of the external output signal OUT is 800.050 MHz.

As described above, if the average frequency division value has a value to the decimal place, a high frequency such as 800 MHz or 1 GHz can be used at a narrow channel interval such as 25 kHz or 12.5 kHz.

However, when the frequency division value is periodically changed as described above, even after the external output signal OUT is locked at the desired frequency, the phase of the comparison signal does not match the phase of the reference clock signal. , A phase difference occurs. Therefore, the control signal output from the phase comparator 134 includes a ripple current.

Reference symbol a in FIG. 6 shows the waveform of the comparison signal input from the frequency divider 132 after the external output signal OUT is locked when the frequency division value is changed between N and N + 1. I have. Symbol b indicates the waveform of the reference clock signal, and symbol c indicates the waveform of the ripple current included in the control signal output from the charge pump circuit 135 because the phase of the comparison signal does not match the phase of the reference clock signal. It is.

The ripple current included in the control circuit generates spurious components in the output signal OUT, not only deteriorating the receiving characteristics of a communication device such as a cellular telephone, but also becoming a disturbing component during transmission. It is a very big problem.

The frequency synthesizer 101 is provided with a compensation circuit 137 having a DA converter 141 and a capacitor 142. The compensation circuit 137 changes the voltage applied to the capacitor 142 by the DA converter 141, and has the same charge amount as the ripple current. Generates a compensation current of the opposite polarity and superimposes it on the control signal output from the charge pump circuit 135,
The ripple current is canceled, and as a result, an output signal OUT having no spurious component is obtained.

As described above, when the frequency of the output signal OUT is 1000025 kHz, the charge pump circuit 135
Is a constant current of +1 mA or -1 mA, the amount of charge of the generated ripple current is represented by the following Q _r ,

Q _r = (1/8) × (1/1000025 kHz) × 1 mA × 1/2 = 62.5 × 10 ⁻¹⁵ (Coulomb) (101) is defined as a unit charge amount, and ± 1 times the maximum to ± 1 7 times (± 7
In the amount of charge _{Q r), + 7Q r →} + 5Q r → + 3Q r → + 1Q r
→ in order of _{-1Q r → -3Q r → -5Q r} → -7Q r, generated at the same period as the reference clock signal.

[0016] and to compensate for such a ripple current, if the capacitance of the capacitor 142 and the C _t, the voltage V _e which satisfies the following equation, and _{C t · V e = Q r} ...... the (102) units , DA converter 141 is -7V _e , -5
_{V e, -3V e, -1V e} , + 1V e, + 3V e, + 5V e,
When the output voltage is changed with the magnitude of +7 V _e , it is possible to generate a compensation current having the same charge amount as the ripple current and having the opposite polarity.

However, as can be seen from the above equation (101), the amount of ripple current depends on the charge pump circuit 13.
The output current is proportional to the output current of No. 5, and the output current fluctuates due to the influence of temperature change or the like, so that there is a problem that the ripple current cannot be accurately compensated.

Further, the as can be seen from (102), the current amount of the compensation current is proportional to the capacitance C _t of the capacitor 142, its capacitance C _t fluctuates by the influence of such aging, manufacturing initially compensated Even if it is possible, there is a problem that spurious is generated in the output signal OUT due to a change over time.

[0019]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and an object of the present invention is to provide a technique capable of accurately compensating for a ripple current.

[0020]

According to a first aspect of the present invention, there is provided an oscillator for outputting an external output signal, and an oscillator for dividing the external output signal while periodically changing a frequency division value. A frequency divider that generates a comparison signal, compares the phase of the input reference clock signal with the phase of the comparison signal, and flows or outputs a constant current output current to the charge pump circuit according to the phase difference. And a phase comparator for generating a control signal, wherein the oscillator changes the frequency of the external output signal based on the control signal, and changes the frequency of the external output signal to the frequency of the reference clock signal. What is claimed is: 1. A frequency synthesizer configured to multiply an average division value of said division value by a compensation circuit for superimposing a compensation current on said control signal and canceling a ripple current included in said control signal. Controlling the road, and having a correction circuit for following the current amount of the compensation current to the change in the output current amount of the charge pump circuit.

The compensation circuit of the frequency synthesizer has a first capacitor having one end connected to a path through which the control signal is transmitted, and a voltage generator connected to the other end of the first capacitor. In the case where the voltage generator is configured to change the voltage applied to the first capacitor by the voltage generator to generate the compensation current, the correction circuit may be configured as described in claim 2. Providing a second capacitor, charging or discharging the second capacitor by the output current, converting the amount of the output current into a voltage value, and outputting the voltage value as a reference voltage to the voltage generator;
The voltage generator may be configured to change a voltage applied to the first capacitor based on the reference voltage.

In the frequency synthesizer according to the second aspect, as in the third aspect, the correction circuit includes:
The charging or discharging of the second capacitor may be performed at least twice with different charging / discharging times, and the conversion may be performed based on a difference in voltage appearing on the second capacitor in each charging / discharging. .

The present invention is configured as described above, and the frequency divider frequency-divides the external output signal output from the oscillator while periodically changing the frequency division value to generate a comparison signal.
The comparison signal and the reference clock signal are output to the phase comparator.

The phase comparator operates the charge pump circuit, compares the phase of the input reference clock signal with the phase of the comparison signal, and outputs a constant current from the charge pump circuit according to the phase difference. Inflow or outflow, thereby generating a control signal.

A control signal output from the charge pump circuit is input to the oscillator via a low-pass filter. Based on the control signal, the oscillator controls the frequency of the external output signal in a direction to reduce the phase difference. To change.
As a result, the frequency of the external output signal is multiplied by the average frequency division value of the frequency of the reference clock signal, thereby increasing the frequency of the external output signal and shortening the channel interval.

The frequency synthesizer is provided with a compensation circuit, which is configured to generate a compensation current having a polarity opposite to that of the ripple current included in the control signal.
When the compensation current is superimposed on the control signal, the ripple current is canceled, and the spurious component is removed from the external output signal OUT.

However, the amount of charge of the ripple current fluctuates,
If it does not match the charge amount of the compensation circuit, the ripple current cannot be accurately canceled.

Therefore, the frequency synthesizer of the present invention includes:
A correction circuit for controlling the compensation circuit is provided, and the amount of the compensation current follows the change in the amount of output current of the charge pump circuit. Since the amount of charge of the ripple current is proportional to the amount of output current, once the amount of charge of the compensation current matches the amount of charge of the ripple current, the compensation current follows it even if the ripple current changes. The amount of charge of the current is exactly equal to the amount of charge of the ripple current with the opposite polarity.

The compensation circuit of the frequency synthesizer has a first capacitor and a voltage generator, one end of the first capacitor is connected to a control signal transmission path, and the other end is connected to the voltage generator. A voltage generator changes a voltage applied to the first capacitor based on the input reference voltage;
When a compensation current is generated, a second capacitor is provided in the correction circuit, the second capacitor is charged or discharged by the output current of the charge pump circuit, and the amount of the output current is converted into a voltage value. When the voltage value is used as the reference voltage, the amount of the compensation current follows the amount of the output current, and as a result, the charge amount of the compensation current can follow the charge amount of the ripple current.

In this case, if the first and second capacitors are made of the same material and structure, if the capacitance changes due to the influence of aging or the like, the change in the capacitance of the first capacitor and the change in the second capacitor will occur. Since the capacitance changes of the capacitors cancel each other, the amount of the compensation current does not change independently of the ripple current.

The charging or discharging time is made different to charge or discharge the second capacitor twice or more, and the voltage appearing on the second capacitor in each charging and discharging is stored, and the output current of the output capacitor is calculated from the difference between the voltages. When the current value is converted to a voltage value and used as a reference voltage, the error in the voltage value caused by the difference between the time when the switch controlling charge and discharge changes from the conductive state to the cut-off state and the time from the cut-off state to the conductive state changes. Since it can be removed from the reference voltage, the amount of charge of the compensation current can be made exactly equal (with opposite polarity) to the amount of charge of the ripple current.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, reference numeral 1 denotes a first example of a frequency synthesizer according to the present invention, which is provided in a semiconductor integrated circuit device.

This frequency synthesizer 1 includes an oscillator 31
(Voltage-controlled oscillator), a frequency divider 32, a reference clock signal generator 33, a phase comparator 34, a charge pump circuit 35, a low-pass filter 36, and a control circuit 38, and an external output signal OUT output from the oscillator 31. Is supplied to other circuits in the semiconductor integrated circuit device, and the frequency divider 32
Is also output.

The frequency divider 32 is controlled by the control circuit 38 and is configured to periodically change the frequency division value. The frequency divider 32 divides the input external output signal OUT by the frequency division value and compares the frequency. Generating a signal.

The reference clock signal generator 33 generates a reference clock signal of a predetermined frequency. The reference clock signal and the comparison signal are input to the phase comparator 34.

The phase comparator 34 compares the phases of both signals to obtain a phase difference, and controls the charge pump circuit 35 based on the phase difference.
Converts the input phase difference into a current, and as a control signal,
The signal is output to the oscillator 31 via the low-pass filter 36.

When the oscillator 31 changes the frequency of the external output signal OUT in a direction to reduce the phase difference in accordance with the input control signal, the frequency of the external output signal OUT eventually becomes equal to the frequency of the frequency divider 32 Is locked when the value is multiplied by the average frequency division value.

If the frequency division value of the frequency divider 32 is N for seven periods of the reference clock signal and N + 1 for one period, the average frequency division value is N + 1/8. When the reference clock signal is 200 kHz and the N is 5000, the external output signal OUT has a frequency of 1000025 kHz.
Becomes

The output stage of the charge pump circuit 35 is shown in FIG.
As shown in, the constant current circuit 41 for the source, the constant current circuit 42 of the sink, a switch 44 ₁ on the source side, and a switch 44 ₂ of the sink side, the phase comparator 3
₁ the switches 44, 44 ₂ is controlled by 4,
Constant current circuit 41 for source and constant current circuit 42 for sink
Is connected to the output terminal for a time corresponding to the phase difference between the reference clock signal and the comparison signal, and as a result,
The charge pump circuit 35 is configured so that a constant current flows in / out for a time corresponding to the phase difference.

The frequency synthesizer 1 includes a compensation circuit 37, a correction circuit 10, and a crystal oscillator 11 (the crystal oscillator 11 is temperature-compensated). , A voltage generator 45 composed of a D / A converter and a first capacitor 46 for generating a compensation current.

The correction circuit 10, as shown in FIG.
, A second switch 22, and a second capacitor 23. One end of the second capacitor 23 is connected to the ground potential. The other end of the second capacitor is connected to the line of the power supply voltage _Vcc and the sink constant current circuit 4 via the first switch 21 and the second switch 22.
2 when the first switch 21 is closed and the second switch 22 is open.
Second voltage V ₂₃ is _the power supply voltage V _cc of the second end of the capacitor 23
Charged until.

On the other hand, when the first switch 21 is open,
Switch 22 is at the closed state, is a constant current discharge at an output current I _out of the constant current circuit 42 of the sink, the voltage at a rate per unit of time I _out / C _t drops.

The correction circuit 10 includes an AD converter 25
, First and second latches 26 and 27, and a subtraction circuit 28
And a DA converter 29. The voltage of the second capacitor 23 is converted into a digital value by the AD converter 25, and the first latch 26 or the second latch 2 is provided.
7 is stored.

The contents stored in the first latch 26 and the second latch 27 are subtracted by a subtraction circuit 28,
9 and as a result, the difference between the digital value stored in the first latch 26 and the digital value stored in the second latch 27 is reconverted into a voltage, which is used as a reference voltage. Is output to

Such a series of operations is configured to be completed before the frequency synthesizer 1 starts operation. The operation sequence will be described with reference to the timing chart of FIG. The switch 22 is in the closed state, the switch 22 is in the open state, and the voltage V ₂₃ of the second capacitor 23 is
_{Are set} to the power supply voltage _Vcc .

Next, the first switch 21 is opened (see FIG. 3).
(A), when the second switch 22 is closed (b), the second capacitor 23 is connected to the constant current circuit 4 for sinking.
2 and the output current I of the constant current circuit 42 for sinking.
_out discharges a constant current.

A crystal oscillator 11 is connected to the correction circuit 10, and a temperature-compensated clock signal output from the crystal oscillator 11 is input to the correction circuit 10. During the period when the second switch 22 is kept closed, It is controlled to be an integral multiple of the cycle of the clock signal.

Let the frequency of the temperature compensated clock signal be f
_r, the capacitance of the second capacitor 23 and C _t, the only two cycles time shall maintain the closed state, the voltage V ₂₃ of the second capacitor _{23, V 23 = V cc - {} I out × _{(2 / f r) / C} t + V err} expressed as ... (1). V _err is an error voltage due to a difference between a time when the second switch 22 shifts from the closed state to the open state and a time when the second switch 22 shifts from the open state to the closed state, and other causes.

[0049] After a period of 2 / f _r has elapsed, the second switch 22 is opened, AD converter 25 starts operating to convert the voltage V ₂₃ of the second capacitor 23 to a digital value ( Sign d). The digital value is stored in the first latch 26 (reference e).

After the second switch 22 is opened,
When the first switch 21 is closed again (code f), the second capacitor 23 is charged, the voltage V ₂₃ is the power supply voltage V _cc.

From this state, when the first switch 21 is opened and the second switch 22 is closed (reference g,
h), the second capacitor 23 is a constant current circuit 4 for sinking.
2 and the second capacitor 23 starts constant current discharge (reference i). At this time, the second switch 22, assuming that only maintain the closed state one cycle time of the crystal oscillator 11, voltage V ₂₃ of the second capacitor _{23, V 23 = V cc - {} I out · a _{(1 / f r) / C} t + V err} ...... (2).

[0052] period of 1 / f _r has elapsed, after the second switch 22 is turned to an open state, AD converter 25 starts operating to convert the voltage V ₂₃ of the second capacitor 23 into a digital value (Sign j). The digital value is stored in the second latch 27 (reference k).

After the digital values are stored in the first and second latches 27, the difference between the digital values stored in the first and second latches 26 and 27 is obtained by the subtraction circuit 28. . Assuming that the voltage value stored in the first latch 26 is V ₁ and the voltage value stored in the second latch 27 is V ₂ , the difference voltage V _d is V _d = V ₁ −V ₂ = I _out · (1 / _fr ) / C _t (3), and the error voltage V _err is eliminated.

[0054] Thus, not included in the error voltage V _err is a digital value indicating the voltage V _d output from the subtracting circuit 29. The digital value is converted by a DA converter 29 into an actual voltage. Compensation circuit as a reference voltage V _d 3
7 is output.

When the frequency of the output signal OUT is F when the average frequency division value of the frequency divider 32 is N + ／, the amount of charge of the ripple current is as follows: Q _r , Q _r = (１ ／) · (1 / F) · I _out · (1/2) (4) is the unit charge amount, and the charge amount is an integral multiple of the unit charge amount.

Assuming that the capacity of the first capacitor 46 in the compensation circuit 37 is C ₀ and the amount of voltage change of the voltage generator 45 is V _AD , the charge amount of the compensation current is C ₀ · V _AD . The voltage change amount V _AD of the AD converter 45 is based on the input reference voltage V
_If it is assumed to be an integral multiple of _d , the minimum value of the voltage change amount V _AD is equal to the reference voltage V _d, and the charge amount Q ₀ of the compensation current in that case is: Q ₀ = C ₀ · V _d. ).

The charge amount Q ₀ is the unit charge amount of the compensation current, and in order to accurately cancel the ripple current,
The unit charge amount Q _0, should be equal to the unit charge amount Q _r of the ripple current. Therefore, it is necessary to satisfy the following equation: Q ₀ = Q _r (6)

[0058] The output current of the constant current circuit 41 for the source is assumed to be equal to the output current I _out of the constant current circuit 42 of the sink, the (3) is simultaneous to (6) and rearranging Q _0,
Q _r , I _out and V _d are eliminated, and the following conditional expression is derived. C ₀ / C _t = ( _fr / F) · (1/16) (7) In order to satisfy the conditional expression (7), the ratio C ₀ / C of the capacitances C ₀ and C _{t on} the left side is required. First, so that _t becomes the value on the right side,
The second capacitors 46 and 23 may be set.

When the first and second capacitors 46 and 23 are formed in the semiconductor integrated circuit device, it is difficult to set the capacitances C ₀ and C _t to the design values. , 23 are made of the same material and have the same structure, the capacitance ratio C ₀ / C _t can be easily made constant. In particular, when the second capacitor 23 is a variable capacitor capable of being trimmed, the above equation (7) is easily satisfied.

Further, the capacitances C ₀ and C _t are affected by the temperature and the like.
Of the first and second capacitors 4 even when the value of
In the case where 6, 23 are formed of the same material and structure in the same semiconductor integrated circuit device, the rate of capacitance change is the same, and the capacitance ratio C ₀ / C _t does not change.
There is no deviation from equation (7).

The term of the output current I _out of the charge pump circuit 34 is not included in the conditional expression (7).
Therefore, when the current amount of the output current _Iout fluctuates,
The amount of the compensation current follows the change, and the ripple current can be accurately canceled.

The output current I _out is ± 1 mA, the frequency of the reference clock signal is 200 kHz, and the average frequency division value is 50.
For 00 + 1/8, as described above, unit electric charge Q _r of the ripple current is 62.5 × 10 ^-15 (Coulomb),
At this time, assuming that the capacitance C ₀ is 0.05 × 10 ⁻¹² (farad) and the frequency of the crystal oscillator 11 is 19.2 MHz, the reference voltage V _d is 1.25 (volt), and the capacitance C _t is 41. .7
× 10 ^-12 (farad).

Although the case where the compensating circuit 37 applies a voltage to one capacitor (the first capacitor 46) has been described above, the present invention is limited to the frequency synthesizer 1 having such a compensating circuit 37. Not something.

For example, a frequency synthesizer 2 using a compensating circuit 37 'shown in FIG.
(Second example of the present invention) is also included in the present invention. This frequency synthesizer 2 has the same configuration as that of the frequency synthesizer 1 of the first example, except for the compensation circuit 37 ', and a description of the overall operation will be omitted.

The compensation circuit 37 ′ has a plurality of second capacitors 53, a plurality of switches 54, and a voltage generator 51. The voltage generator 51 has two power supplies 51 ₁ ,
Has 51 _2, one end of each capacitor 53 are respectively connected via a switch 54 to the two power supply 51 _1, 51 _2, and the other end is connected to the output terminal of the charge pump circuit 35.

The reference voltage V _d input from the correction circuit 10
Is input to the voltage generator 51, the voltage generator 51, the two power 51 _1, 51 ₂ of the output voltage is varied by the magnitude of the reference voltage V _d.

[0067] Switch 54, each capacitor 53, two of which are configured to connect to either one of the power supply 51 _1, 51 _2, and the capacitance of the capacitor 53 and C _0, 1 single Connecting the capacitor 53 to the power supply 51 ₁ , 5
By switching from one of the 1 ₂ to the _{other, ± C 0 · V d (} =
A compensation current of the charge amount of Q _r ) can be generated. Therefore, when the connection of the M capacitors 53 is switched,
It is possible to generate a compensation current of a charge amount ± M · Q _r.

In the compensation circuit 37 'and the correction circuit 10,
The ripple current can be accurately canceled without being affected by the fluctuation of the output current I _out of the charge pump circuit 35 and the fluctuation of the capacitances C ₀ and C _t .

In the correction circuit 10, the second capacitor 23 is connected to the line of the power supply voltage _Vcc and the constant current circuit 4 for sinking by the first and second switch elements 21 and 22.
2 respectively, one end of the second capacitor is connected to the line of the power supply voltage _Vcc , and the other end is connected to the first and second capacitors.
May be connected to the ground potential line and the source constant current circuit 41 to form a correction circuit.

[0070]

The ripple current can be accurately canceled without being affected by the fluctuation of the output current of the charge pump circuit or the fluctuation of the capacitance of the capacitor in the compensation circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first example of a frequency synthesizer of the present invention.

FIG. 2 is an internal block diagram of a charge pump circuit and a correction circuit of the frequency synthesizer.

FIG. 3 is a timing chart for explaining the operation of the correction circuit;

FIG. 4 is a partial block diagram showing a second example of the frequency synthesizer of the present invention.

FIG. 5 is a block diagram illustrating a prior art frequency synthesizer.

FIG. 6 is a timing chart for explaining a ripple current.

[Explanation of symbols]

1, 2 ... frequency synthesizer 10 ... correction circuit
23 ... second capacitor 31 ... oscillator 3
2 ... frequency divider 34 ... phase comparator 35 ... charge pump circuit 37, 37 '... compensation circuit 45,
51 voltage generator 46, 53 first capacitor

Claims (3)

[Claims] An oscillator for outputting an external output signal; a frequency divider for dividing the external output signal while periodically changing a frequency dividing value to generate a comparison signal; A phase comparator that compares a phase with the phase of the comparison signal, flows or outputs a constant current output current to or from the charge pump circuit in accordance with the phase difference, and generates a control signal. A frequency synthesizer that changes the frequency of the external output signal based on a control signal, and sets the frequency of the external output signal to a value obtained by multiplying the frequency of the reference clock signal by an average frequency division value. A compensation circuit that superimposes a compensation current on the control signal and cancels a ripple current included in the control signal; and controls the compensation circuit to reduce a current amount of the compensation current to the charge pump circuit. Frequency synthesizer, characterized in that it comprises a correction circuit which follow the change in force current. 2. The compensation circuit has a first capacitor having one end connected to a path through which the control signal is transmitted, and a voltage generator connected to the other end of the first capacitor, 2. The frequency synthesizer according to claim 1, wherein the voltage applied to the first capacitor is changed by the first voltage generator to generate the compensation current. 2. Wherein the output current charges or discharges the second capacitor, converts the amount of the output current into a voltage value, and outputs the voltage value to the voltage generator as a reference voltage, A frequency synthesizer, wherein the voltage generator is configured to change a voltage applied to the second capacitor based on the reference voltage. 3. The correction circuit performs charging or discharging of the second capacitor at least twice with different charging / discharging times, and performs the conversion based on a difference between voltages appearing on the second capacitor in each charging / discharging. The frequency synthesizer according to claim 2, wherein the frequency synthesizer is configured to perform the following.