JPH10209122A - Sidewall formation method - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] The conventional sidewall forming method has a problem that a large variation occurs in the sidewall film thickness. Since variations in the formed sidewall dimensions are directly linked to variations in device characteristics such as variations in the threshold voltage of transistor operation, it is particularly important to suppress variations in sidewall dimensions in miniaturizing devices and reducing operating voltages. there were. SOLUTION: The silicon oxide film 4 is etched using an etching gas containing a fluorocarbon-based gas containing carbon and fluorine, thereby forming the gate electrode 3.
The above problem was solved by setting the temperature of the substrate 1 from −40 ° C. to −80 ° C. in the step of forming the sidewall on the side wall of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a sidewall of a semiconductor device or the like, and more particularly, to a method for forming a sidewall of a silicon oxide film.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for portable models of computers and communication devices, and high performance and low power consumption of devices have been promoted. For this reason, large-scale integrated circuits (hereinafter referred to as LSIs) which are used in these portable devices and are an important part directly related to the performance of the entire device.
There is a strong demand for a semiconductor device having high performance and low power consumption.

In order to improve the performance and reduce the power consumption of an LSI, miniaturization of the transistor element and reduction of the power supply voltage are effective. However, in order to reduce the operating voltage of the transistor element,
It is particularly important to suppress variations in pattern dimensions, which is a cause of variations in transistor element characteristics.Since miniaturization of elements, that is, pattern miniaturization, is rapidly progressing, there is an increasing demand for higher precision of pattern dimensions. It has become tough.

As a technique for insulating a pattern of a conductive film of a transistor element in a self-aligning manner, a side wall formation method is known.
In the case of a microstructured transistor having a structure in which a gate electrode is covered with a sidewall, as typified by a D-structure MOS transistor, variations in the formed sidewall dimensions may cause variations in the threshold voltage of transistor operation and the like. Since this is directly related to the variation in the element characteristics, it is particularly important to suppress the variation in the side wall dimension in miniaturizing the element and reducing the operating voltage.

[0005] A conventional sidewall forming technique will be described in the process of manufacturing a MOS transistor. FIG. 5 shows a cross-sectional view of a conventional side wall forming process.

First, as shown in FIG. 5A, a gate insulating film 2 is formed on a surface of a region on a substrate 1 where a transistor is to be formed, and a gate electrode 3 made of polysilicon is formed on the gate insulating film 2. To form Next, a silicon oxide film 4 is deposited so as to cover the gate electrode 3.

Next, as shown in FIG. 5B, the silicon oxide film 4 is etched back by anisotropic dry etching until the silicon substrate surface 5 in the region where the source and drain are to be formed is exposed. I do.

Further, by performing over-etching for several tens of% of the etching time (hereinafter referred to as "over-etch amount several tens%"), side walls 6 made of silicon oxide are formed on the side surfaces of gate electrode 3 at this time. Is done. Thus, the sidewall shown in FIG. 5C is formed.

For etching back the silicon oxide film, a reactive ion etching (RIE) apparatus or the like is usually used, and a plasma of a gas containing fluorine or carbon such as CF ₄ or CHF ₃ is used. Normally, etching is performed at a silicon substrate temperature of normal temperature.

[0010]

However, the conventional method for forming a sidewall has a problem that a large variation occurs in the thickness of the sidewall. FIG. 6 shows a change in the thickness of the sidewall when the sidewall is formed.
As shown in FIG. 6A, when a silicon oxide film 4 having a thickness T2 is deposited on a gate electrode 3 having a thickness T1 by a CVD method (chemical vapor deposition method), The thickness of the silicon oxide film 4 is substantially equal to T2 at T3. Next, when the silicon oxide film 4 is etched back to expose the underlying silicon substrate surface 5, a sidewall 6 is formed as shown in FIG. 6B. At this time, the thickness T4 of the formed sidewall 6 becomes T4 = T3, and it is desirable from the viewpoint of easy control of the thickness that the sidewall thickness T4 can be controlled by the deposited thickness T2 of the silicon oxide film 4. However, actually, T4 <T2. Such a change in the film thickness increases the variation in the sidewall dimension more than the uniformity of the deposited film thickness and the etching rate in the formation of the silicon oxide film 4 in the wafer surface.

The reason that the formed sidewall film thickness T4 becomes smaller than the initial silicon film thickness T2 is due to the decrease in the silicon oxide film thickness on the side surface of the gate, that is, the progress of the re-side etching. This is due to the dependence on the ion incident angle. This is because, generally, in the etching by ion bombardment of a solid surface, the etching rate is higher when the ions are incident obliquely at an angle than when the ions are incident vertically, and in the case of the silicon oxide film, The inclined portion (shoulder portion) obliquely incident than the horizontal portion vertically incident has a higher etching rate, that is, the retreat of the shoulder portion is faster.

Conventionally, as a general method for increasing the anisotropy of etching, there is a method of increasing the bias power applied to the wafer stage to increase the energy and directionality of ions. Due to the dependence on the angle of incidence of ions, the problem of retraction of the shoulder cannot be solved even if the directionality of ions is improved. In addition, when the ion energy is increased, when the silicon oxide film is etched to expose the underlying silicon substrate surface 5, damage 7 to the substrate is increased, causing a problem such as deterioration of element characteristics. Another method is known in which the reaction product is deposited on the pattern side wall to utilize the side wall protection effect of the deposited film.However, ion bombardment such as a wall perpendicular to the substrate or a wall immediately below the etching mask is also known. This effect cannot be expected in a shoulder that is easily affected by ion bombardment, not in a place that is not easily affected by ion bombardment.

As for the retreating speed of the shoulder, that is, the speed of side etching, for example, if the cross-sectional shape or size of the gate electrode 3 changes, the shape (curvature or angle) of the shoulder of the silicon oxide film changes. Therefore, even if the etching rate on the horizontal surface in the wafer surface is uniform, the retreat speed of the shoulder is not constant due to the difference in shape, and the formed sidewall width T4 varies. In particular, the speed of side etching tends to increase when performing over-etching, and the recession of the shoulder during over-etching is a major cause of the variation in the sidewall film thickness T4.

The variation in the thickness T4 of the side wall also depends on the ratio of the thickness T2 of the silicon oxide 4 to the thickness T1 of the gate electrode 3.
As 2 increases, the shoulder of the silicon oxide film 4 increases, and the vertical portion of the silicon oxide film 4 along the side surface of the gate electrode 3 decreases, so that the recession of the etching shoulder becomes remarkable.

Further, in order to prevent a decrease in the operating speed due to a reduction in the transistor power supply voltage, it is preferable that the capacitance of the polysilicon gate electrode is small, and for that purpose, it is desirable that the thickness T1 of the polysilicon gate electrode is small. On the other hand,
In order to suppress a short channel effect which causes a variation in device characteristics when a transistor is miniaturized, the thickness T4 of the sidewall cannot be necessarily reduced. Accordingly, the film thickness T2 tends to be larger than the film thickness T1 with miniaturization.

As described above, in the formation of the sidewall, the etching of the shoulder (side etch) is suppressed, and the thickness T4 of the sidewall is not affected by the variation in the shape of the shoulder and the amount of overetching. It is desired to establish a highly accurate formation method that can be determined by the deposited film thickness of the film 4.

[0017]

According to the present invention, there is provided a method for forming a side wall, comprising: forming a silicon oxide film on a substrate on which a gate electrode is formed; and forming an etching gas containing a fluorocarbon-based gas containing carbon and fluorine. Forming a sidewall on the side wall of the gate electrode by etching the silicon oxide film, wherein the temperature of the substrate is reduced by etching the silicon oxide film. -40
It is characterized in that the temperature is set at from -80 ° C to -80 ° C.

The step is a gate electrode.

The etching gas is characterized in that at least one of a halogen compound gas and oxygen is added to the fluorocarbon-based gas containing carbon and fluorine.

The fluorocarbon system containing carbon and fluorine is C ₄ F ₈ , and the halogen compound gas is HBr.

In the step of etching the silicon oxide film, the etching is performed using an etching gas obtained by adding a halogen compound to a fluorocarbon-based gas, and the etching is performed using an etching gas consisting of only the fluorocarbon-based gas. And a process.

The step of etching the silicon oxide film includes the step of performing etching using an etching gas obtained by adding a halogen compound to a fluorocarbon-based gas, and the step of etching using an etching gas obtained by adding oxygen to the fluorocarbon-based gas. And a step of performing the following.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments.

(Embodiment 1) FIG. 1 is a process sectional view for explaining a pattern forming method manufactured by the pattern forming method of the present invention.

On the surface of a region where a transistor is to be formed on the substrate 1, a gate insulating film 2 (made of silicon oxide) having a thickness of 3 nm is formed, and a gate electrode 3 made of polysilicon is further formed thereon with a width of 0 nm. .2 .mu.m and 150 nm in thickness. Next, a silicon oxide film 4 having a thickness of 120 nm is deposited by a CVD method. FIG. 1 shows a cross-sectional view up to this step.
(A).

Next, the silicon oxide film 4 shown in FIG.
In the step of etching back, a gas obtained by adding, for example, Cl ₂ as a halogen-based gas containing bromine or chlorine to C ₄ F ₈ was used as an etching gas, and an ECR plasma etching device was used as an etching device. The gas flow rates are 30 sccm for C ₄ F _{8 and 3} sccm for Cl ₂ . The wafer size is 6 inches, the bias power applied to the stage is 100 W, and the discharge pressure is 1 mTorr. When the substrate temperature at the time of etching was −60 ° C., the etching rate of the silicon oxide film 4 was 180 nm / min. The etching time for forming the sidewall was set as an overetch amount of 50%.

In the present embodiment, the ratio T2 / T1 of the deposited film thickness (T2) of the silicon oxide film 4 to the thickness (T1) of the polysilicon gate electrode 3 is as large as 0.8, and is along the side surface of the gate electrode 3. The vertical portion of the silicon oxide film 4 is 3
Although it is small at nm or less, when the silicon oxide film 4 is etched, as shown in FIG. 1C, the retreat of the shoulder is suppressed, and the formed sidewall width T4 maintains the initial film thickness at the time of deposition. And remained at 120 nm.

The substrate cooling effect of the present invention will be described with reference to FIG.

As shown in FIG. 2A, a 3 nm-thick gate insulating film 2 (made of silicon oxide) is formed on the surface of a region where a transistor is to be formed on the substrate 1, and further thereon. The gate electrode 3 made of polysilicon has a width of 0.
2 μm, 150 nm thick, and 12 μm thick
The substrate on which the 0 nm silicon oxide film 4 is formed is etched.

When C ₄ F ₈ is used as an etching gas and the substrate temperature is cooled to -40 ° C. or less, the carbon polymer composed of elements such as Si contained in the etching gas and a material to be etched, such as Si or the like, has a concave portion, a wrinkle portion. The pattern is strengthened at the bottom 21, side wall 22, and shoulder 23 of the pattern, and the upper surface 2
4, the etching rate is lower. This state is shown in FIG.
(B).

Although the etching rate of the bottom 21 also decreases,
As a result, the side etch can be almost eliminated not only at the side wall portion 22 but also at the shoulder portion 23. FIG. 2C shows the sidewall formed in the process until the etching is performed until the gate electrode 3 is exposed.

In this embodiment, Cl ₂ is added as a halogen-based gas containing bromine or chlorine to the etching gas. While maintaining the side-etching suppression effect at the shoulder 23 to some extent, the negative side is effective in preventing the lowering of the etching rate of the bottom 21 due to the carbon-based polymer deposition. As described above, for example, a small amount of Cl ₂ is added. By doing so, while suppressing the side etch of the side wall 22 and the shoulder 23,
The etching rate of the bottom part 21 can be kept substantially equal to that of the top part 24. However, if the addition amount increases, the selectivity to silicon decreases, so the addition amount is preferably 10% or less.

As described above, the present invention utilizes the fact that the effect of depositing the carbon-based polymer on the bottom portion 21 of the silicon oxide film is higher than that on the upper portion 24 of the silicon oxide film by cooling the substrate. For this reason, according to the present invention, even if the underlying silicon substrate is exposed by etching the silicon oxide film,
Since the effect of deposition on the silicon substrate (1) is also enhanced, it is also effective in reducing damage to the underlying substrate when the sidewall is formed.

In the present embodiment, C ₄ F ₈ is used as the fluorocarbon-based gas. However, the present invention is not limited to this, and CF _X which contributes to the deposition of the carbon-based polymer is used.
( _X = 1,2,3) Other C / F that easily generates radicals
Gases with a high composition ratio, such as C ₂ F ₆ , C ₃ F ₆ , CH
It is clear that the same effect can be obtained by using F ₃ , C ₃ F _{8 and the} like.

In this embodiment, the etching apparatus is provided with E
Although a CR plasma etching apparatus was used, the present invention is not limited to this, and the same effect can be obtained by using another plasma etching apparatus such as a parallel plate plasma etching apparatus or an ICP (inductively coupled) plasma etching apparatus. Clearly what can be expected.

FIG. 3 shows the dependency of the sidewall width on the amount of overetch. As described above, since the sidewall width is easily changed with respect to the overetch, a comparison is made between the conventional pattern forming method and the case where the substrate temperature of the present invention is set to -60 ° C. with respect to the change in the sidewall width during the overetch. Was done. In the conventional method, the side wall width is smaller than the overetch amount, but is hardly changed in the method of the present invention.

FIG. 4 shows the measurement of the substrate cooling temperature dependency of the retreat speed of the shoulder 23 in FIG. 2 (defined by the amount of etching in the vertical direction when etching is performed until the underlying gate electrode is exposed on the pattern upper surface 24). However, it can be seen that the amount of etching of the shoulder portion is sharply reduced by lowering the substrate temperature to -40 ° C or lower. Side wall 22
The effect of suppressing side etch of the shoulder 23 is more effective as the temperature is lowered. However, when the cooling temperature is lowered below -80 ° C., the adsorption of the etching gas to the inner wall of the chamber and the stage round surface increases, and the discharge pressure and the gas composition are maintained. It is not preferable because it becomes difficult to perform.

(Embodiment 2) As in Embodiment 1,
A gate insulating film having a thickness of 3 nm is formed on a surface of a region where a transistor is to be formed, and a gate electrode made of, for example, polysilicon is formed thereon with a width of 0.2 μm and a thickness of (T1) 1.
It is formed with a thickness of 50 nm. Next, a silicon oxide film having a thickness (T2) of, for example, 120 nm is deposited by a CVD method.
In the embodiment of the present invention, in the step of etching back the silicon oxide film, C ₄ F _{8 is used} as an etching gas.
A gas obtained by adding 6% of HBr as a halogen-containing gas containing bromine was used, and an ECR plasma etching apparatus was used as an etching apparatus. Substrate temperature during etching
At 50 ° C., the etching rate of the silicon oxide film is about 160 nm / min. The etching time for forming the sidewall was set as an overetch amount of 50%.

In this embodiment, the ratio T2 / T1 of the deposited thickness (T2) of the silicon oxide film to the thickness (T1) of the polysilicon gate electrode is as large as 0.8, and the silicon oxide film along the side surface of the gate electrode. The vertical portion becomes smaller at 3 nm or less, but when the silicon oxide film is etched, the retreat of the shoulder portion is suppressed, and the formed sidewall width maintains the initial film thickness at the time of deposition, and is 120 nm.
m.

In the present embodiment, C ₄ F ₈ was used as the fluorocarbon-based gas. However, the present invention is not limited to this, and CF _X which contributes to the accumulation of carbon-based polymer is used.
( _X = 1,2,3) Other C / F that easily generates radicals
Gases with a high composition ratio, such as C ₂ F ₆ , C ₃ F ₆ , CH
It is clear that the same effect can be obtained by using F ₃ , C ₃ F _{8 and the} like.

In this embodiment, for example, HBr is added as a halogen-based gas to the etching gas. However, when HBr containing hydrogen is used, excess fluorine radicals are trapped by hydrogen radicals generated in plasma, and H
F is generated, resulting in an increase in the C / F ratio,
It has the effect of accelerating the deposition of the carbon-based polymer. Therefore, when HBr containing hydrogen is used, it is also effective in improving the anisotropy of etching and preventing a decrease in selectivity to underlying silicon, that is, reducing damage.

In this embodiment, an ECR plasma etching apparatus is used as an etching apparatus. However, the present invention is not limited to this, and a parallel plate type plasma etching apparatus, an ICP (inductive coupling type) plasma etching apparatus, and the like can be used. It is clear that the same effect can be expected by using the plasma etching apparatus described above.

(Embodiment 3) As in Embodiment 1,
On the surface of the region where the transistor is to be formed, for example, a thickness of 3 n
m, and a gate electrode made of, for example, polysilicon having a width of 0.2 μm and a film thickness (T
1) Form 150 nm. Next, by the CVD method,
For example, a silicon oxide film having a thickness (T2) of 120 nm is deposited. In the third embodiment of the present invention, in the step of etching back the silicon oxide film, a gas obtained by adding 6% of HBr and 6% of O ₂ to C ₄ F ₈ is used as an etching gas, and ECR plasma etching is used as an etching apparatus. The device was used. When the substrate humidity at the time of etching is −50 ° C., the etching rate of the silicon oxide film is about 170 nm.
/ Min. The etching time for forming the sidewall was set as an overetch amount of 50%.

In the present embodiment, the ratio T2 / T1 of the deposited film thickness (T2) of the silicon oxide film to the thickness (T1) of the polysilicon gate electrode is as large as 0.8, and the silicon oxide film along the side surface of the gate electrode. The vertical portion was small at 3 nm or less, but when the silicon oxide film was etched, the retreat of the shoulder was suppressed, and the formed sidewall width was 120 nm, maintaining the initial film thickness at the time of deposition. .

In the present embodiment, C ₄ F ₈ was used as the fluorocarbon-based gas. However, the present invention is not limited to this, and CF _X that contributes to the deposition of the carbon-based polymer is used.
( _X = 1,2,3) Other C / F that easily generates radicals
Gases with a high composition ratio, such as C ₂ F ₆ , C ₃ F ₆ , CH
It is clear that the same effect can be obtained by using F ₃ , C ₃ F _{8 and the} like.

In this embodiment, the halogen-based gas and oxygen are added to the etching gas. However, compared to Embodiments 1 and 2 in which only the halogen-based gas is added, the lowering of the bottom etching rate due to the deposition of the carbon-based polymer is reduced. In particular, even when the space at the bottom is very narrow due to the fine dense pattern, the lowering of the bottom etching rate was effectively suppressed, and stable processing was achieved. It is possible to process a side wall in which side etching on a gate side wall and a shoulder is suppressed. As a result, the vertical portion of the side wall portion is lengthened, so that the overetch time can be increased, and high-accuracy sidewall processing independent of the variation of the overetch time can be performed.

In this embodiment, an ECR plasma etching apparatus is used as an etching apparatus. However, the present invention is not limited to this, and a parallel plate type plasma etching apparatus, an ICP (inductive coupling type) plasma etching apparatus, and the like can be used. It is clear that the same effect can be expected by using the plasma etching apparatus described above.

(Embodiment 4) As in Embodiment 1,
A gate insulating film having a thickness of 3 nm is formed on the surface of a region where a transistor is to be formed, and a gate electrode made of polysilicon is formed thereon with a width of 0.2 μm and a thickness (T1) of 150 n.
m. Next, a silicon oxide film having a thickness (T2) of, for example, 120 nm is deposited by a CVD method. In the fourth embodiment of the present invention, in the step of etching back the silicon oxide film, in the first step, C ₄ F ₈ is used as a fluorocarbon-based gas as an etching gas and HBr is used as a halogen-based gas containing bromine or chlorine at a concentration of 7%. In the second step, C ₄ F ₈ was used as a fluorocarbon-based gas. An ECR plasma etching apparatus was used as the etching apparatus. When the substrate temperature at the time of etching is −40 ° C., the etching rate of the silicon oxide film is about 160 nm / min in the first step, and the etching rate of the silicon oxide film is about 50 n in the second step.
m / min. In the first step, 85% etching was performed, in the second step, the remaining 15% etching was performed, and the overetch amount was etched 50%.

In the present embodiment, the ratio T2 / T1 of the deposited thickness (T2) of the silicon oxide film to the thickness (T1) of the polysilicon gate electrode is as large as 0.8, and the silicon oxide film along the side surface of the gate electrode Although the vertical portion is small at 3 nm or less, when the silicon oxide film is etched, the retreat of the shoulder is suppressed, and the formed sidewall width maintains the initial film thickness at the time of deposition, and is 120 nm. Was.

The first step in this embodiment is the second step.
The third embodiment aims at the same effect as that of the second embodiment and performs the same operation as the second embodiment. In the present embodiment, a second step of etching only with C ₄ F ₈ is provided. In the second step, since a halogen-based gas containing bromine or chlorine is not added, compared to the second embodiment in which etching is performed only in the first step, the side wall and the shoulder in the side wall and the shoulder formed by carbon-based polymer deposition are used. Since the effect of suppressing the etch can be enhanced, and the effect of depositing the carbon-based polymer on the bottom can be enhanced in the second step, the selectivity and the damage can be reduced when the underlying silicon substrate is exposed.

However, in the second step, since a halogen-based gas containing bromine or chlorine is not added, the lowering of the bottom etching rate due to the accumulation of the carbon-based polymer is apt to be caused. Since the particles are likely to be generated, the etching of the silicon oxide film in the second step is 30% of the whole.
Hereinafter, it is desirable that the overetch amount is also suppressed to 50% or less.

In this embodiment, in the first step and the second step, C is used as the fluorocarbon-based gas.
_{Although 4} F ₈ was used, the present invention is not limited to this, and CF _X ( _X = 1,
2,3) The same effect can be obtained by other gases that easily generate radicals and have a high C / F ratio, such as C ₂ F ₆ , C ₃ F ₆ , CHF ₃ , and C ₃ F _8. it is obvious.

In this embodiment, an ECR plasma etching apparatus is used as an etching apparatus. However, the present invention is not limited to this, and a parallel plate type plasma etching apparatus, an ICP (inductive coupling type) plasma etching apparatus, or the like may be used. It is clear that the same effect can be expected by using the plasma etching apparatus described above.

(Embodiment 5) In the same manner as in the first embodiment, a gate insulating film having a thickness of, for example, 3 nm is formed on the surface of a region where a transistor is to be formed, and further made of polysilicon, for example. 0.2 μm wide gate electrode,
It is formed with a thickness (T1) of 150 nm. Next, a silicon oxide film having a thickness (T2) of, for example, 120 nm is deposited by a CVD method.

In the fifth embodiment of the present invention, in the step of etching back the silicon oxide film, C ₄ F ₈ is used as an etching gas in the first step, and fluorocarbon is used in the second step. It was used as the HBr added as the halogen-based gas containing bromine or chlorine using a C ₄ F ₈ in the system gas. The addition of HBr was set at 7%. An ECR plasma etching apparatus was used as the etching apparatus. When the substrate temperature at the time of etching was −50 ° C., the etching rate of the silicon oxide film in the first step was about 50 nm / min, and the etching rate of the silicon oxide film in the second step was about 160 nm / min. In the first step, the silicon oxide film was etched by 20%, and in the second step, the remaining 80% etching and 50% overetching were performed.

In the present embodiment, the ratio T2 / T1 of the deposited film thickness (T2) of the silicon oxide film to the thickness (T1) of the polysilicon gate electrode is as large as 0.8, and the silicon oxide film along the side surface of the gate electrode. The vertical portion becomes smaller when the thickness is 3 nm or less, but when the silicon oxide film is etched, the retreat of the shoulder is suppressed, and the formed sidewall width maintains the initial film thickness at the time of deposition.
m.

In the present embodiment, the second step aims at the same effect as in the second embodiment, and is performed in the same manner as in the first embodiment. In the present embodiment, the first
Is provided with a step of etching only with C ₄ F ₈ , which enhances the carbon-based polymer deposition effect on the side wall and shoulder as compared with the case where a halogen-based gas containing bromine or chlorine is added. As a result, it is possible to process a sidewall in which side etching of a shoulder portion is particularly suppressed as compared with the second embodiment.

As a result, the vertical portion of the side wall becomes longer, so that the overetching time can be increased, and a highly accurate sidewall processing can be performed without depending on the variation of the overetching time.

In the first step of the present embodiment, since a halogen-based gas containing bromine or chlorine is not added, a lowering of the bottom etching rate due to the accumulation of the carbon-based polymer is likely to occur. The etching of the silicon oxide film is desirably 30% or less of the whole. In the second step, since a halogen-based gas containing bromine is added, particles are hardly generated, and the amount of overetch can be increased as compared with the fourth embodiment.

In this embodiment, in the first step and the second step, C is used as the fluorocarbon-based gas.
_{Although 4} F ₈ was used, the present invention is not limited to this, and CF _X ( _X = 1,
2,3) The same effect can be obtained by other gases that easily generate radicals and have a high C / F ratio, such as C ₂ F ₆ , C ₃ F ₆ , CHF ₃ , and C ₃ F _8. it is obvious.

In this embodiment, an ECR plasma etching apparatus is used as an etching apparatus. However, the present invention is not limited to this, and a parallel plate type plasma etching apparatus, an ICP (inductively coupled type) plasma etching apparatus, or the like may be used. It is clear that the same effect can be expected by using the plasma etching apparatus described above.

(Embodiment 6) In the same manner as in Embodiment 1, a gate insulating film having a thickness of, for example, 3 nm is formed on the surface of a region where a transistor is to be formed, and a gate electrode made of, for example, polysilicon is further formed thereon. Is formed with a width of 0.2 μm and a thickness (T1) of 150 nm. Next, a silicon oxide film having a thickness (T2) of, for example, 120 nm is deposited by a CVD method. In the sixth embodiment of the present invention, in the step of etching back the silicon oxide film, in the first step, C ₄ F ₈ was used as a fluorocarbon-based gas as an etching gas, and O ₂ was added to this at 7%. Was used. In the second step, C ₄ F ₈ is used as a fluorocarbon-based gas as an etching gas, and HBr is used as a halogen-based gas containing bromine. The addition of HBr was 7%. An ECR plasma etching apparatus was used as the etching apparatus. When the substrate temperature during the etching was -50 ° C., the etching rate of the silicon oxide film was about 110 nm / min in the first step, and the etching rate of the silicon oxide film was about 160 nm / min in the second step. In the first step, 50% etching was performed, and in the second step, the remaining 50% etching and 50% overetching were performed.

In the present embodiment, the ratio T2 / T1 of the deposited film thickness (T2) of the silicon oxide film to the thickness (T1) of the polysilicon gate electrode is as large as 0.8, and the silicon oxide film along the side surface of the gate electrode. The vertical portion becomes smaller when the thickness is 3 nm or less, but when the silicon oxide film is etched, the retreat of the shoulder is suppressed, and the formed sidewall width maintains the initial film thickness at the time of deposition.
m.

In the first step of this embodiment, O ₂ was added to the etching gas. However, as compared with the fourth embodiment in which only the fluorocarbon-based gas was used in the first step, the carbon-based polymer was deposited. This is effective in suppressing the lowering of the bottom etching rate, and in particular, even when the space at the bottom is extremely narrowed with a fine pattern, the lowering of the bottom etching rate is suppressed, and stable processing can be performed.

[0065]

According to the present invention, since the decrease in the width of the sidewall is suppressed, the variation in the width of the sidewall is suppressed. Therefore, variation in characteristics of the formed transistor can be suppressed.

By adding either a halogen compound or oxygen, the change in the width of the sidewall can be further reduced.

Further, by dividing the process into a process using an etching gas to which a halogen compound is added and a process using an etching gas to which a halogen compound is not added, formation of a sidewall with even more controllability can be achieved. A method could be provided.

[Brief description of the drawings]

FIG. 1 is a view showing a step of forming a sidewall according to the present invention.

FIG. 2 is a diagram illustrating a substrate cooling effect of the present invention.

FIG. 3 is a diagram showing a change in a sidewall film thickness with respect to an overetch amount.

FIG. 4 is a diagram showing a shoulder etching amount with respect to a substrate temperature.

FIG. 5 is a view showing a conventional sidewall forming process.

FIG. 6 is a diagram showing a change in a sidewall film thickness in a conventional sidewall formation process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate insulating film 3 Gate electrode 4 Silicon oxide film 5 Silicon substrate surface 21 Bottom 22 Side wall 23 Shoulder 24 Top surface

Claims (7)

[Claims] A step of forming a silicon oxide film on a substrate having a step formed thereon, and etching the silicon oxide film using an etching gas containing a fluorocarbon-based gas containing carbon and fluorine. Forming a sidewall on the side wall of the semiconductor device, wherein the temperature of the substrate is set to -40 ° C. to −80 ° C. in the step of etching the silicon oxide film. The method of forming the wall. 2. The method according to claim 1, wherein the step is a gate electrode. 3. The sidewall forming method according to claim 1, wherein the etching gas includes at least one of a halogen compound and oxygen added to the fluorocarbon-based gas. 4. The method according to claim 1, wherein the fluorocarbon-based gas is C ₄ F ₈ . 5. The method according to claim 3, wherein the halogen compound gas is HBr. 6. The step of etching the silicon oxide film includes a first step of performing etching using an etching gas obtained by adding a halogen compound to a fluorocarbon-based gas, and a step of performing etching using an etching gas composed of a fluorocarbon-based gas. The method according to claim 1, further comprising: performing a second step. 7. The step of etching the silicon oxide film includes a first step of performing etching using an etching gas obtained by adding a halogen compound to a fluorocarbon-based gas, and an etching gas obtained by adding oxygen to a fluorocarbon-based gas. 3. The method of forming a sidewall according to claim 1, further comprising: performing a second etching step.