JPH10198409A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mainly accelerate the processing of basic instruction processing process by performing the separation of program memory for ladder sequence and data memory and the pipeline processing of ladder program instruction. SOLUTION: A basic instruction dedicated processor 6 lets a program memory 5A and a data memory 5B separately have interfaces, provides multistage registers 61 , 62 and 63 at the read part of program memory 5A and attains pipeline processing. Namely, while the operation of current instruction is executed, at a data memory interface 64 , the operated of instruction next to the current one is read and at a program memory interface, the instruction following the current one at the interval of two is read. Thus, the buses of program memory 5A for ladder sequence and data memory 5B are separated and they can be simultaneously accessed from the basic instruction dedicated processor 6. Thus, operation can be accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller and, more particularly, to a configuration of an arithmetic unit for performing an arithmetic operation at high speed.

[0002]

2. Description of the Related Art A programmable controller sequentially reads and analyzes a sequence of user program instructions stored in a program memory, and executes a high-speed operation based on the result. In particular, the operation of the ladder sequence requires high speed.

[0003] Instructions of a programmable controller are roughly classified into basic instructions such as contact instructions and applied instructions such as numerical operations. In a ladder sequence program, the appearance ratio of basic instructions is high, and this operation can be processed at high speed.
It leads to the realization of high-speed operation as a whole.

FIG. 2 shows a configuration of an arithmetic unit of a general programmable controller. The arithmetic unit uses a general-purpose microprocessor (or general-purpose DSP) 1 and memories 2 and 3 for processing applied instructions such as numerical operations, and a dedicated processor (or dedicated LSI) 4 for processing basic instructions such as contact instructions.
Reference numeral 5 denotes a ladder sequence program memory and data memory.

In this configuration, as described above, the basic instruction has a simple operation but a high appearance ratio, and the applied instruction has a low operation ratio and a complicated operation process as compared with the basic instruction. This is because it has excellent performance. Also, there is an instruction fetch as an element that greatly affects the operation performance in the programmable controller.

[0006] In the configuration of FIG. 2, the decoding dedicated processor, main elements of the memory interface unit 4 ₁ for reading data sequentially read and operands of the user program instruction, for analyzing the user command to perform the basic instruction processing such as contact instruction It comprises a unit 4 ₂ and an operation unit 4 ₃ .

A dedicated processor 4 for performing the basic instruction processing
Reads out and decodes a program instruction in response to a start instruction from the general-purpose microprocessor 1, reads out operand data based on the decoded content, and performs an operation. Since these are simple repetitive processes, it is easy to realize only a hardware circuit.

[0008]

[0005] With the times, programmable controllers have been required to further improve arithmetic performance.

However, in the conventional configuration, the access time to the memory element such as the reading of the program instruction and the reading of the operand in the processing of the basic instruction processing (dedicated) processor becomes a bottleneck in the high-speed operation. In addition, the processing switching time between a general-purpose microprocessor and a dedicated processor for basic instruction processing due to random encounter with application instructions in sequential reading of a program memory becomes a bottleneck, and a significant improvement in arithmetic performance cannot be expected.

An object of the present invention is to provide a programmable controller which mainly speeds up the processing of a basic instruction processor.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a programmable controller that performs applied instruction processing such as numerical operation by a general-purpose microprocessor and performs basic instruction processing such as contact instructions by a dedicated processor. A memory bus is separated, the dedicated processor can simultaneously access the program memory and the data memory, and performs pipeline processing in which data read from the program memory is multi-staged.

In the pipeline processing, when the arithmetic processing of the instruction of the ladder program has a plurality of steps,
In the last step of all instructions, reading of the program memory, incrementing of its counter, reading of operand data, and decoding are performed.

The general-purpose microprocessor processes application instructions such as complicated numerical operation instructions and block instructions, and the special-purpose processor reads a register readable from the general-purpose microprocessor when decoding an internal instruction code. And the data indicating the processing program storage address of the instruction and the data indicating the processing instruction of the dedicated processor or the processing instruction of the general-purpose microprocessor, and cause the general-purpose microprocessor to perform polling, and the general-purpose microprocessor recognizes the instruction in that section. Then, using the data indicating the processing program storage address of the read instruction, branching to the processing program of the instruction and performing the processing, the dedicated processor reads the prefetched operand data and the like to perform the arithmetic processing. .

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a configuration of an arithmetic unit of a programmable controller according to an embodiment of the present invention, in which a ladder sequence program memory and a data memory bus are separated and can be simultaneously accessed from a processor dedicated to basic instructions. And

The processor 6 exclusively for basic instructions has separate interfaces for the program memory 5A and the data memory 5B. Registers 6 ₁ , 6 ₂ , and 6 ₃ are provided in multiple stages in the read section of the program memory, and pipeline processing is performed. Enable. That is, when performing the calculation of the current instruction, reads the operand data memory interface 6 ₄ In the current of the next instruction in the program memory interface unit, when leading the instruction after two current That's it.

Basic instructions such as contact instructions are simple in processing, require only one-step operation, and are easy to implement in hardware.
In the present invention, small-scale microcode processing is performed, and even simple numerical processing instructions are processed by the dedicated processor 6.

As shown in the following table, the matching of the pipeline processing is performed by reading the program memory and the operand data at the last step of all user instructions. Thus, the processing start step of the current instruction, aligns and data operands, immediately and ready for operation in the arithmetic circuit 6 _5, operation performance of the spurious is only operational step.

[0018]

[Table 1]

Further, application instructions such as complicated numerical operation instructions and block instructions are processed by the general-purpose microprocessor 1, and when decoding the instruction code inside the special-purpose processor 6, the general-purpose microprocessor 1 stores the instruction code in a readable register. The general-purpose microprocessor 1 is polled by adding data indicating the processing program storage address of the instruction and data indicating whether the instruction is the processing instruction of the dedicated processor 6 or the general-purpose microprocessor 1.

When the general-purpose microprocessor 1 recognizes the instruction of the category of the general-purpose microprocessor, it uses the read data indicating the processing program storage address of the instruction and branches to the processing program of the instruction to perform processing. In the processing, the dedicated processor 6 reads the operand data and the like pre-fetched from the dedicated processor and performs an arithmetic processing.

[0021]

As described above, according to the present invention, by separating the ladder sequence program memory from the data memory and by pipeline processing of the ladder program instruction, only the operation processing step becomes an apparent operation time, and the In the case of an instruction, one step is an apparent operation time, and the operation can be speeded up.

Also, simple numerical calculations can be taken into the dedicated processor, and a lean process specialized for ladder instructions can be performed, thereby realizing high-speed calculations.

Further, when the general-purpose microprocessor is switched from the dedicated processor to the processing, the general-purpose microprocessor can immediately branch to the processing program of the instruction, and the operation data is also available, so that high-speed processing can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an arithmetic unit of a programmable controller according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a calculation unit of a conventional general programmable controller.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... General-purpose microprocessor 4 ... Dedicated processor 5 ... Ladder sequence program memory / data memory 5A ... Program memory 5B ... Data memory 6 ... Dedicated processor 6 _{1 to} 6 ₃ ... Register 6 ₄ ... Interface 6 ₅ ... Operation circuit

Claims (3)

[Claims] In a programmable controller, a general-purpose microprocessor performs an application instruction processing such as a numerical operation and a basic processor processes a basic instruction such as a contact instruction, a ladder sequence program memory and a data memory bus are separated. A programmable controller, wherein the dedicated processor enables simultaneous access to the program memory and the data memory, and performs a pipeline process in which data read from the program memory is multi-staged. 2. In the pipeline processing, when arithmetic processing of an instruction of a ladder program is performed in a plurality of steps, reading of a program memory, incrementing of a counter thereof, reading and decoding of operand data are performed at the last step of all instructions. The programmable controller according to claim 1, wherein: 3. The general-purpose microprocessor processes application instructions such as complicated numerical operation instructions and block instructions,
When decoding the internal instruction code, the dedicated processor stores data indicating the processing program storage address of the instruction in a register readable by the general-purpose microprocessor and whether the processing instruction is a processing instruction of the dedicated processor or a processing instruction of the general-purpose microprocessor. The general-purpose microprocessor uses the data indicating the processing program storage address of the read instruction when the general-purpose microprocessor recognizes the instruction of the category,
3. The programmable controller according to claim 1, wherein the processor branches to a processing program of the instruction and performs processing, and the dedicated processor reads operand data or the like prefetched and performs arithmetic processing. 4.