JPH10188563A - Semiconductor memory circuit - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory circuit capable of preventing data of an address in a previous cycle from being erroneously written to a memory cell 3. SOLUTION: In a semiconductor memory circuit provided with a plurality of memory cells 3 connected to input / output lines 7, 8 and bit lines 4, 5, a precharge drive signal generation circuit 12 is based on a write data signal / WE. , Data into memory cell 3
, And generates and outputs precharge driving signals A and / A. Next, the precharge PMOS transistors 13a and 13b, which are precharge circuits, precharge the input / output lines 7 and 8 and the bit lines 4 and 5 based on the precharge drive signal. Therefore, after the data is written, the levels of the input / output lines 7 and 8 and the bit lines 4 and 5 can be raised more quickly than in the conventional example, and the data of the address in the previous cycle is erroneously written to the memory cell 3. Can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor memory circuit including a plurality of memory cells connected to a bit line, such as a circuit.

[0002]

2. Description of the Related Art FIG. 9 is a circuit diagram of a conventional example of a semiconductor memory circuit such as an SRAM circuit. In the specification and the drawings of the present application, a signal to be enabled by data L, that is, a low enable signal (excluding the drive signal A in the embodiment) is replaced with a bar (overline) instead of, for example, / WE. , "/" Is added before the code.

In FIG. 9, a plurality of memory cells 3 for storing data and an equalizing signal / BEQB for shortening an access time have a gate between bit lines 4 and 5 transmitting data. P turned on
The source and drain of the MOS transistor 20 are connected. One end of the bit line 4 is a PMOS for precharging.
Power supply Vc via the drain / source of transistor 2a
c, while the other end of the / bit line 5 is connected to the power supply Vcc via the drain and source of the PMOS transistor 2b for precharging. The gates of the PMOS transistors 2a and 2b are grounded.

On the other hand, a Y gate circuit 6 for selecting a bit line is connected to the other ends of the bit lines 4 and 5. The Y gate circuit 6 includes a PMOS transistor 21 and an NMOS transistor 22 whose sources and drains are connected to each other, a PMOS transistor 23 and an NMOS transistor 24 whose sources and drains are connected to each other, and an inverter 25. You. The other end of the bit line 4 is connected to a PMOS transistor 21 and an NMO
I / I via each source / drain of S transistor 22
The other end of the / bit line 5 is connected to a PMOS
The source / drain of the transistor 23 and the NMOS transistor 24 are connected to the / I / O1 line 8.
Here, the pair of I / O1 lines 7 and / I / O1 lines 8 are combined to form an input / output line (hereinafter, referred to as an I / O line) 7,
8 For example, the Y gate signal / YDEC1 is PMO
The NMOS transistor 2 is applied to each gate of the S transistors 21 and 23, and
2 and 24 are applied to each gate. With the circuit configured as described above, the memory cell line circuit ML1 for the pair of bit lines 4 and 5 is configured, and further, for example, 15 memory cell line circuits having similar circuits are provided. Sixteen memory cell line circuits ML1 to ML16 are provided for a pair of I / O lines 7 and 8.

The data to be written to the memory cell 3 is input to an input buffer circuit 11 and the input buffer circuit 11
Delays the input data by a predetermined time and
In addition to outputting to the signal generation circuit 10, it generates a / WD signal (write data signal) indicating inverted write data and outputs it to the write driver circuit 9. The DTD signal generation circuit 10 detects a data transition and generates a DTD (Data Transition Detection) signal for activating a write period for a predetermined period based on the input delayed input data, and also writes data. A / WE signal (write enable signal) is generated and output to a write driver circuit 9 that controls the I / O1 line 7 and / I / O1 line 8 at the time of data writing. In response to this, when the / WE signal is low enable, the write driver circuit 9 outputs an I / O line control signal corresponding to the / WD signal to the I / O line.
Output to the O1 line 7 or the / I / O1 line 8.

The I / O1 line 7 and the / I / O1 line 8
Further, for example, seven pairs of I / O lines having the same configuration as that of are provided, so that a total of eight pairs of I / O lines are provided for one memory cell block.

Next, the operation of the conventional semiconductor memory circuit configured as described above will be described with reference to FIGS. Here, FIG. 10 is a timing chart showing an operation when writing data L to the memory cell 3 in the semiconductor memory circuit of FIG. 9, and FIG.
10 is a timing chart showing an operation when writing data H to a memory cell 3 in the semiconductor memory circuit of FIG. 9;

In FIG. 10, when data L is input to input buffer circuit 11 after a write cycle,
The WD signal goes high. At this time, the DTD signal becomes D
The signal is generated by the TD signal generation circuit 10, and in response thereto, the / WE signal at L level is generated. When the / WE signal is low enable, the write driver circuit 9
The I / O1 line 7 is changed from H level to L level in response to the / WD signal. This L level signal is transmitted to the bit line 4 via the Y gate circuit 6, and the L level data is written and stored in the memory cell 3.

In FIG. 11, similarly, when data H is input to input buffer circuit 11, the / WD signal goes low. At this time, the DTD signal is generated by the DTD signal generation circuit 10, and in response to this, the L-level /
A WE signal is generated. The write driver circuit 9 is provided with / W
When the E signal is low enable, the / I / O1 line 8 is changed from H level to L level in response to the / WD signal. This L-level signal is output via the Y gate circuit 6 to /
The data is transmitted to bit line 5 and H-level data is written and stored in memory cell 3.

[0010]

In the conventional semiconductor memory circuit, if the wiring from the I / O1 line 7 to the bit line 4 is long during the operation of writing the input data L in FIG. 10, the stray capacitance becomes large. . Preferably, after L level data is stored in memory cell 3, bit line 4
And the level of the I / O1 line 7 must be quickly raised to the level of Vcc-Vth. Here, Vcc is a power supply voltage of, for example, 5 V, and Vth is the bit line 4 or /
This is the threshold level of the bit line 5. However, I
Due to the relatively large stray capacitance in the wiring from the / O1 line 7 to the bit line 4, the charging period becomes long as shown by 100 in FIG. 10, and the next after the word line rises from the L level to the H level. There is a problem that the L-level data is erroneously written to the memory cell 3 in the address read cycle.

In the operation of writing the input data H in FIG. 11, if the wiring from the / I / O1 line 8 to the / bit line 5 is long, the stray capacitance becomes large. Preferably,
After H-level data is stored in the memory cell 3,
Each level of bit line 5 and / I / O1 line 8 is set to Vcc-V
It needs to be raised quickly to the th level. However, due to the relatively large stray capacitance in the wiring from / I / O1 line 8 to bit line 5, 101 in FIG.
As shown by, the charging period becomes longer, and the H level data is erroneously written to the memory cell 3 in the read cycle of the next address after the word line rises from the L level to the H level. Occurs.

That is, if data is written to the memory cell 3 based on the DTD signal after the write cycle, the bit lines 4 and 5 and the I / O lines 7 and 8 have a large floating capacitance. There is a case where the time for precharging to the level of Vth is delayed and the data at the address in the previous cycle is erroneously written to the memory cell 3.

An object of the present invention is to solve the above problems and to provide a semiconductor memory circuit capable of preventing data of an address in a previous cycle from being erroneously written to the memory cell 3.

[0014]

According to the present invention, there is provided a semiconductor memory circuit including a plurality of memory cells connected to an input / output line and a bit line. The semiconductor memory circuit stores data based on a write data signal. A precharge drive signal generation circuit that generates and outputs a precharge drive signal after writing to a cell; and a precharge circuit that precharges the input / output line and the bit line based on the precharge drive signal. It is characterized by having.

In the semiconductor memory circuit, preferably, the precharge circuit is connected in parallel to a load transistor connected to a power supply.

In the semiconductor memory circuit, preferably, the precharge circuit is connected to an input / output line.

In the semiconductor memory circuit, preferably, the semiconductor memory circuit includes first and second sense amplifiers respectively connected to input / output lines, and the precharge circuit includes the first sense amplifier. It is connected to an input / output line between the connected input / output line and the input / output line to which the second sense amplifier is connected.

Preferably, in the semiconductor memory circuit, the semiconductor memory circuit includes at least two memory cell blocks, and the precharge circuit includes a bit line formed between the at least two memory cell blocks. Connected to.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

The semiconductor memory circuit according to the embodiment of the present invention is, for example, an SRAM circuit, and is shown in FIGS.
As shown in FIG. 7 and (a), after data is written in the memory cell 3, the bit line 4 or the / bit line 5 and the I / O
To raise the O1 line 7 or the / I / O1 line 8 to the level of Vcc-Vth more quickly than in the conventional example,
A precharge drive signal generation circuit (hereinafter, referred to as a drive signal generation circuit) 12 that generates and outputs precharge drive signals A and / A based on the WD signal, and (b) precharge drive signals A and / A. The bit line 4 or / bit line 5 and the I / O1 line 7 or / I / O1 line 8 are
It is characterized by including PMOS transistors 13a and 13b for precharging, which are precharge circuits for rapidly increasing the voltage to the level of Vcc-Vth as compared with the conventional example.

Embodiment 1 FIG. 1 is a circuit diagram of a semiconductor memory circuit according to Embodiment 1 of the present invention. The same reference numerals as in FIG. 9 showing a conventional example denote the same parts. I have. In the semiconductor memory circuit of the first embodiment, in particular, a precharge PMOS for raising the voltage to the level of Vcc-Vth more quickly than in the conventional example after writing data to the memory cell 3.
It is characterized in that the transistors 13a and 13b are connected in parallel with the PMOS load transistors 2a and 2b, respectively.

Referring to FIG. 1, a plurality of memory cells 3 for storing data and an equalizing signal / BEQB for shortening an access time form a gate between bit lines 4 and 5 transmitting data. P turned on
The source and drain of the MOS transistor 20 are connected. One end of the bit line 4 is a PMOS for precharging.
Power supply Vc via the drain / source of transistor 2a
c, while the other end of the / bit line 5 is connected to the power supply Vcc via the drain and source of the PMOS transistor 2b for precharging. The gates of the PMOS transistors 2a and 2b are grounded. Here, the respective sources and drains of the precharge PMOS transistors 13a and 13b are connected to the respective sources and drains in parallel with the PMOS load transistors 2a and 2b, respectively. Precharge PMOS transistor 13
The signals a and 13b are turned on in response to the L-level drive signals A and / A generated by the drive signal generation circuit 12 described in detail below.

On the other hand, a Y gate circuit 6 for selecting a bit line is connected to the other ends of the bit lines 4 and / bit line 5. The Y gate circuit 6 includes a PMOS transistor 21 and an NMOS transistor 22 whose sources and drains are connected to each other, a PMOS transistor 23 and an NMOS transistor 24 whose sources and drains are connected to each other, and an inverter 25. You. The other end of the bit line 4 is connected to a PMOS transistor 21 and an NMO
I / I via each source / drain of S transistor 22
The other end of the / bit line 5 is connected to a PMOS
The source / drain of the transistor 23 and the NMOS transistor 24 are connected to the / I / O1 line 8.
For example, the Y gate signal / YDEC1 is applied to each gate of the PMOS transistors 21 and 23 and is also applied to each gate of the NMOS transistors 22 and 24 via the inverter 25. With the circuit configured as described above, the memory cell line circuit ML1 for the pair of bit lines 4 and 5 is configured, and further, for example, 15 memory cell line circuits having similar circuits are provided. Sixteen memory cell line circuits ML1 to ML16 are provided for a pair of I / O lines 7 and 8.

Data to be written to the memory cell 3 is input to the input buffer circuit 11 and
Delays the input data by a predetermined time and
In addition to outputting to the signal generation circuit 10, a / WD signal (write data signal) indicating inverted write data is generated and output to the write driver circuit 9 and the drive signal generation circuit 12. The DTD signal generation circuit 10 detects a data transition based on the input delayed input data, generates a DTD signal for activating a writing period for a predetermined period, and generates a / WE signal (WWE signal) indicating data writing. A write enable signal) is generated and output to a write driver circuit 9 and a drive signal generation circuit 12 that control the I / O1 line 7 and / I / O1 line 8 during data writing. In response to this, when the / WE signal is low enable, the write driver circuit 9 outputs the I / D signal corresponding to the / WD signal.
An O line control signal is output to the I / O1 line 7 or / I / O1 line 8.

Then, the I / O1 line 7 and the / I / O1 line 8
Further, for example, seven pairs of I / O lines having the same configuration as that of are provided, so that a total of eight pairs of I / O lines are provided for one memory cell block.

FIG. 2 is a circuit diagram showing details of the drive signal generation circuit 12 of FIG. In FIG. 2, the / WE signal (write enable signal) generated by the DTD signal generation circuit 10 is connected to a first input terminal of a NOR gate 31 and NO.
The / WD signal (write data signal) input to the first input terminal of the R gate 32 and generated by the input buffer circuit 11 is input to the second input terminal of the NOR gate 31 and passed through the inverter 30. Is input to the second input terminal of the NOR gate 32. NOR gate 31
Is input to a first input terminal of a NAND gate 46 through four inverters 41, 42, 43, and 44 connected in cascade, and is also input to a NAND gate 46 through an inverter 45. The signal is input to the second input terminal. On the other hand, the WDL signal output from the NOR gate 32 includes four cascaded inverters 51,
The signal is input to the first input terminal of the NAND gate 56 via 52, 53, 54, and is input to the second input terminal of the NAND gate 56 via the inverter 55.
The NAND gate 46 generates a driving signal A for precharging based on the two input signals and applies the driving signal A to the gate of the precharging PMOS transistor 13a. On the other hand, the NAND gate 56 generates a driving signal / A for precharging based on the two input signals and applies the driving signal / A to the gate of the precharging PMOS transistor 13b.

In the drive signal generation circuit 12 configured as described above, the / WE signal generated by the DTD signal generation circuit 10 and the input buffer are used to turn on / off the precharge PMOS transistors 13a and 13b. Based on the / WD signal generated by the circuit 11, a WDH signal and a WDL signal are generated.
The precharge driving signals A and / A are generated based on the DH signal and the WDL signal.

The operation of the semiconductor memory circuit according to the first embodiment configured as described above will be described with reference to FIGS. FIG. 3 is a timing chart showing an operation when data L is written into the memory cell 3 in the semiconductor memory circuit of FIG. 1, and FIG. 4 is a timing chart when data H is written into the memory cell 3 in the semiconductor memory circuit of FIG. 6 is a timing chart showing an operation.

Referring to FIG. 3 showing a case where data L is written after the write cycle, when data L is input to input buffer circuit 11 from an external circuit, / WE signal is low.
Level period (that is, the active period of the DTD signal) I /
O1 line 7 is at L level, and / I / O1 line 8 is at Vcc-
It remains at the Vth level. Therefore, an L-level signal is transmitted to bit line 4 while V bit is transmitted to / bit line 5.
cc-Vth level signal is transmitted to memory cell 3
At the L level is written and stored. After writing the data, the levels of the I / O1 line 7 and the bit line 4 remain at the L level until the next cycle. At this time, in order to prevent the erroneous writing of the data L in the conventional example, in the present embodiment, the drive signal A generated by the drive signal generation circuit 12 is used in the vicinity of immediately before the rising of the word line in the next cycle. By turning on the charging PMOS transistor 13a, as shown by 200 in FIG. 3, the levels of the I / O1 line 7 and the bit line 4 are rapidly changed from the L level to the level of Vcc-Vth as compared with the conventional example. Pull up. Here, the greater the precharge driving capability of the precharge PMOS transistor 13a, the greater the pulling effect.

In the drive signal generation circuit 12 shown in FIG.
In order to turn on / off the precharge PMOS transistors 13a and 13b, a WDH signal and a WDL signal are generated based on the / WE signal generated by the DTD signal generation circuit 10 and the / WD signal generated by the input buffer circuit 11. Signal, and then the / DH signal
Control the / O1 line 8 while the WDL signal is on the I / O1 line 7
Is controlling. When writing data L, the WDH signal goes low while the WDL signal goes high,
The bit line 4 is pulled down to the L level by the I / O1 line 7 that has gone to the H level. When the writing of the data L is completed, the WDL signal changes from the H level to the L level, and at that time, the drive signal A which is a pulse signal is generated. The precharge PMOS transistor 13a is turned on only when the drive signal A is at the L level, and the I / O1 line 7
And raises the bit line 4 to the level of Vcc-Vth.

Referring to FIG. 4 showing a case where data H is written after the write cycle, when data H is input to input buffer circuit 11 from an external circuit, / WE signal is low.
Level period (ie, active period of DTD signal) / I
/ O1 line 8 is at L level, and I / O1 line 7 is at Vcc-
It remains at the Vth level. Accordingly, an L-level signal is transmitted to / bit line 5, while V line is transmitted to bit line 4.
cc-Vth level signal is transmitted to memory cell 3
Is written and stored. After the writing of the data, the levels of the / I / O1 line 8 and the / bit line 5 remain at the L level until the next cycle.
At this time, in order to prevent erroneous writing of the data H in the conventional example, in the present embodiment, the drive signal / A generated by the drive signal generation circuit 12 near the rise of the word line in the next cycle. PM for precharge
By turning on the OS transistor 13b, FIG.
As indicated by reference numeral 201, the levels of the / I / O1 line 8 and the / bit line 5 are quickly raised from the L level to the level of Vcc-Vth as compared with the conventional example. Here, the higher the precharge driving capability of the precharge PMOS transistor 13b, the greater the pulling effect.

In the drive signal generation circuit of FIG. 2, when data H is written at the end of the cycle, the WDH signal goes high while the WDL signal goes low,
The / I / O1 line 8 at the level is pulled down to the L level.
When the writing of the data H is completed, the WDH signal changes from the H level to the L level, so that a drive signal / A which is a pulse signal is generated at the time of the change. Drive signal / A is L
The precharge PMOS transistor 13b is turned on only during the level period, and functions to raise the / I / O1 line 8 and the / bit line 5 to the level of Vcc-Vth.

As described above, according to the present embodiment, since the drive signal generation circuit 12 and the precharge PMOS transistors 13a and 13b are provided, the I / O1 line 7 and the bit line 4 Or / I /
O1 line 8 and / bit line 5 are changed from L level to Vcc-Vt.
It can be quickly raised to the level of h as compared with the conventional example. Therefore, it is possible to prevent the data of the address in the previous cycle from being erroneously written to the memory cell 3.

Second Embodiment FIG. 5 is a circuit diagram of a semiconductor memory circuit according to a second embodiment of the present invention. The semiconductor memory circuit according to the second embodiment is different from the first embodiment in FIG.
While the MOS transistor 13a is connected to the I / O1 line 7, the precharge PMOS transistor 13b is connected to / I
/ O1 line 8. Hereinafter, differences between the second embodiment and the first embodiment will be described.

In FIG. 5, the source of the precharging PMOS transistor 13a is connected to the power supply Vcc, the drain is connected to the I / O1 line 7, and the drive signal A is applied to the gate. The gate of the PMOS load transistor 2a is connected to the power supply Vcc. On the other hand, the source of precharge PMOS transistor 13b is connected to power supply Vcc, and its drain is / I / O1.
The drive signal / A is applied to the gate of the line 8. The gate of the PMOS load transistor 2b is connected to the power supply Vcc.

The semiconductor memory circuit according to the second embodiment configured as described above has the following structure: “After writing data L, the precharge PMOS transistor 1
3a quickly raises I / O1 line 7 from the L level to the level of Vcc-Vth, thereby raising bit line 4 from the L level to the level of Vcc-Vth more quickly than in the conventional example, while data H is raised. Is written, the precharge PMOS transistor 13b drives the / I / O1 line 8 from the L level to Vcc-Vt based on the drive signal / A.
The operation is the same as that of the first embodiment except that the bit line 5 is quickly raised from the L level to the level of Vcc-Vth as compared with the conventional example. Has an effect. Therefore, it is possible to prevent the data at the address of the previous cycle from being erroneously written to the memory cell 3.

Third Embodiment FIG. 6 is a circuit diagram of a semiconductor memory circuit according to a third embodiment of the present invention. The semiconductor memory circuit according to the third embodiment is different from the second embodiment in FIG.
The MOS transistor 13a is connected between the I / O1 line 7 to which the sense amplifier 61 is connected and the I / O1 line 7 to which the sense amplifier 62 is connected.
The MOS transistor 13b is connected between the / I / O1 line 8 to which the sense amplifier 61 is connected and the / I / O1 line 8 to which the sense amplifier 62 is connected. Hereinafter, differences between the third embodiment and the first embodiment will be described.

In FIG. 6, a sense amplifier 61 has an I / O
It is connected to the 1 line 7 and the / I / O1 line 8, detects data read from the memory cell 3 on the I / O1 line 7 and the / I / O1 line 8, and amplifies and outputs the data. The sense amplifier 62 is connected to the I / O1 line 7 and the / I / O1 line 8,
The data read from the memory cell 3 on the I / O1 line 7 and / I / O1 line 8 is detected, amplified, and output. Here, I / O1 line 7 and / I / O1 line 8 are global I
Also called / O line.

The semiconductor memory circuit of the third embodiment configured as described above operates in the same manner as the second embodiment, and has the same function and effect. Therefore, it is possible to prevent the data at the address of the previous cycle from being erroneously written to the memory cell 3.

Fourth Embodiment FIG. 7 is a circuit diagram of a semiconductor memory circuit according to a fourth embodiment of the present invention. The semiconductor memory circuit according to the fourth embodiment is different from the second embodiment in FIG.
The MOS transistors 13a and 13b are connected to the first T gate circuit 6a and the second T gate circuit 6b by a bit line 14 which is a second aluminum wiring formed between the two memory cell blocks MB1 and MB2. And / or bit line 1
5 is connected. Hereinafter, differences between the fourth embodiment and the second embodiment will be described.

In FIG. 7, a first aluminum wiring (shown by a solid line in FIGS. 7 and 8) is provided on an upper surface of a semiconductor substrate (not shown) for forming the semiconductor memory circuit.
Bit line 4 and / or bit line 5 are formed,
On the lower surface of the semiconductor substrate, a bit line 14 as a second aluminum wiring (indicated by a dashed line in FIGS. 7 and 8).
And / or bit line 15, bit line 4a and / or bit line 5
a and the I / O1 line 7a and the / I / O1 line 8a. That is, aluminum wirings having a two-layer structure are formed, and these are called T-type bit lines. Then, instead of Y gate circuit 6 of the second embodiment in FIG. 5, a first T gate circuit 6a having the same configuration as Y gate circuit 6 and selecting a bit line is provided. Here, the first T
The gate circuit 6a includes a first T signal instead of the Y gate signal.
Gate signal / BS1 is applied to each gate of inverter 25 and PMOS transistors 21 and 23.

The bit line 4 to which the memory cell 3 is connected
Each source of the bit line 4a, the PMOS transistor 21 and the NMOS transistor 22 of the first T gate circuit 6a
Drain, bit line 14, PM of second T gate circuit 6b
The source / drain of each of the OS transistor 71 and the NMOS transistor 72, the I / O1 line 7a, and the I / O
It is connected to the write driver circuit 9 via one line 7. The / bit line 5 to which the memory cell 3 is connected includes the / bit line 5a, the source / drain of the PMOS transistor 23 and the NMOS transistor 24 of the first T gate circuit 6a, the / bit line 15, and the / bit line 5 of the second T gate circuit 6b. PMO
The source / drain of each of the S transistor 73 and the NMOS transistor 74, the / I / O1 line 8a, and / I /
It is connected to the write driver circuit 9 via the O1 line 8.

The second T gate circuit 6b for selecting a bit line has a PM connected to its source and drain.
OS transistor 71 and NMOS transistor 72
, A PMOS transistor 73 and an NMOS transistor 74 whose sources and drains are connected to each other, the inverter 25, and a NAND gate 76. For example, the second T gate signal Y2Y3 signal, Y0
The Y1 signal and the / NED signal are input to the NAND gate 76, and the gate signal output from the NAND gate 76 is applied to each gate of the PMOS transistors 71 and 73, and the NMOS transistors 72 and 74 Applied to each gate.

FIG. 8 is a circuit diagram showing a circuit from the write driver circuit 9 of FIG. 7 to each of the memory cell blocks MB1 and MB2. As shown in FIG. 8, a bit line 4 as a first aluminum wiring is formed on an upper surface of a semiconductor substrate (not shown).
And / or bit lines 5 are formed, and on the lower surface of the semiconductor substrate, bit lines 14 and / or
A bit line 15, a bit line 4a and a / bit line 5a, and an I / O1 line 7a and a / I / O1 line 8a are formed.
Precharge PMOS transistors 13a and 13b are provided between two memory cell blocks MB1 and MB2, and are connected to bit lines 14 and / bit lines 15 which are second aluminum wirings.

The semiconductor memory circuit of the fourth embodiment configured as described above operates in the same manner as the second embodiment, and has the same function and effect. Therefore, it is possible to prevent the data of the address in the previous cycle from being erroneously written to the memory cell 3.

[0046]

As described above in detail, according to the semiconductor memory circuit of the present invention, in a semiconductor memory circuit having a plurality of memory cells connected to input / output lines and bit lines, a semiconductor memory circuit based on a write data signal A precharge drive signal generating circuit for generating and outputting a precharge drive signal after writing data to the memory cell; and a precharge circuit for precharging the input / output line and the bit line based on the precharge drive signal. A charge circuit is provided. Therefore, after the data is written, the levels of the input / output lines and the bit lines can be quickly raised as compared with the conventional example, thereby preventing the data of the address in the previous cycle from being erroneously written to the memory cell. it can.

In the semiconductor memory circuit, preferably, the precharge circuit is connected in parallel to a load transistor connected to a power supply. Therefore, after the data is written, the levels of the input / output lines and the bit lines can be quickly raised as compared with the conventional example, thereby preventing the data of the address in the previous cycle from being erroneously written to the memory cell. it can.

In the semiconductor memory circuit, preferably, the precharge circuit is connected to an input / output line. Therefore, after the data is written, the levels of the input / output lines and the bit lines can be quickly raised as compared with the conventional example.
It is possible to prevent the data at the address of the previous cycle from being erroneously written to the memory cell.

In the semiconductor memory circuit, preferably, the semiconductor memory circuit includes first and second sense amplifiers respectively connected to input / output lines, and the precharge circuit includes the first sense amplifier. It is connected to an input / output line between the connected input / output line and the input / output line to which the second sense amplifier is connected. Therefore, after the data is written, the levels of the input / output lines and the bit lines can be quickly raised as compared with the conventional example, thereby preventing the data of the address in the previous cycle from being erroneously written to the memory cell. it can.

In the semiconductor memory circuit, preferably, the semiconductor memory circuit includes at least two memory cell blocks, and the precharge circuit includes a bit line formed between the at least two memory cell blocks. Connected to. Therefore, after the data is written, the levels of the input / output lines and the bit lines can be quickly raised as compared with the conventional example, thereby preventing the data of the address in the previous cycle from being erroneously written to the memory cell. it can.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor memory circuit according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing details of a drive signal generation circuit 12 of FIG. 1;

FIG. 3 is a timing chart showing an operation when writing data L to a memory cell 3 in the semiconductor memory circuit of FIG. 1;

FIG. 4 is a timing chart showing an operation when writing data H to a memory cell 3 in the semiconductor memory circuit of FIG. 1;

FIG. 5 is a circuit diagram of a semiconductor memory circuit according to a second embodiment of the present invention;

FIG. 6 is a circuit diagram of a semiconductor memory circuit according to a third embodiment of the present invention;

FIG. 7 is a circuit diagram of a semiconductor memory circuit according to a fourth embodiment of the present invention;

8 is a circuit diagram showing a circuit from the write driver circuit 9 of FIG. 7 to each of the memory cell blocks MB1 and MB2.

FIG. 9 is a circuit diagram of a conventional semiconductor memory circuit.

10 shows data L in the semiconductor memory circuit of FIG. 9;
6 is a timing chart showing an operation when writing is performed in the memory cell 3.

FIG. 11 shows data H in the semiconductor memory circuit of FIG. 9;
6 is a timing chart showing an operation when writing is performed in the memory cell 3.

[Explanation of symbols]

1 power supply, 2a, 2b PMOS load transistor, 3
Memory cell, 4 bit line, 5 / bit line, 6 Y
Gate circuit, 6a first T gate circuit, 6b second T gate circuit, 7 I / O1 line, 8 / I / O1 line, 9 write driver circuit, 10 DTD signal generation circuit, 11
Input buffer circuit, 12 precharge drive signal generation circuit, 13a, 13b PMOS transistor for precharge, 14 bit line, 15 / bit line, 20, 21,
23, 71, 73 PMOS transistors, 22, 2
4, 72, 74 NMOS transistors, 25, 30,
41 to 45, 51 to 55, 75 Inverter, 3
1,32 NOR gate, 46,56,76 NAND
Gate, 61, 62 sense amplifier, MB1, MB2 memory cell block, ML1, ML2 memory cell line circuit.

Claims (5)

[Claims] In a semiconductor memory circuit having a plurality of memory cells connected to an input / output line and a bit line, a precharge drive signal is generated after writing data to the memory cell based on a write data signal. And a precharge circuit for precharging the input / output lines and the bit lines based on the precharge drive signal. 2. The semiconductor memory circuit according to claim 1, wherein said precharge circuit is connected in parallel to a load transistor connected to a power supply. 3. The semiconductor memory circuit according to claim 1, wherein said precharge circuit is connected to an input / output line. 4. The semiconductor memory circuit includes first and second sense amplifiers connected to input / output lines, respectively, wherein the precharge circuit is connected to an input / output line connected to the first sense amplifier. 2. The semiconductor memory circuit according to claim 1, wherein said input / output line is connected to an input / output line between said input / output line and said second sense amplifier. 5. The semiconductor memory circuit according to claim 1, wherein at least two
2. The semiconductor memory circuit according to claim 1, further comprising a plurality of memory cell blocks, wherein said precharge circuit is connected to a bit line formed between said at least two memory cell blocks.