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JPH10163594A - Electronic circuit board and its manufacture - Google Patents

Electronic circuit board and its manufacture

Info

Publication number
JPH10163594A
JPH10163594A JP21383397A JP21383397A JPH10163594A JP H10163594 A JPH10163594 A JP H10163594A JP 21383397 A JP21383397 A JP 21383397A JP 21383397 A JP21383397 A JP 21383397A JP H10163594 A JPH10163594 A JP H10163594A
Authority
JP
Japan
Prior art keywords
resin
high thermal
circuit board
laminated
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21383397A
Other languages
Japanese (ja)
Inventor
Yosuke Sagami
洋祐 佐上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HAISOOLE KK
Original Assignee
HAISOOLE KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HAISOOLE KK filed Critical HAISOOLE KK
Priority to JP21383397A priority Critical patent/JPH10163594A/en
Publication of JPH10163594A publication Critical patent/JPH10163594A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036Multilayers with layers of different types
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of cracks at an interface between a conductive film and a glass fiber by mixing electric insulating filler having high thermal conductivity into a void of an inner surface of the film, and filling high thermal conductive resin having low thermal expansion characteristic equivalent to that of the film, and adhering the resin to the film. SOLUTION: A resin board 201 is obtained by integrally laminating a high thermal conductive resin layer 205 mixed with electric insulating filler having high thermal conductivity at both surfaces of a core material 204 made of fiber-reinforced resin. A void 202 at an inner surface of a conductive film 203 is charged with a high thermal conductive resin having low thermal expansion characteristics, equivalent to or lower than a metal of the film, sealed. Further, one or multilayer wiring circuits 208 are laminated integrally via an insulating layer 207 on the circuit 206, and the laminated circuit 208 are laminated on the sealed void 202. As a result, a problem of cracks in the film and warping of the board is solved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は抜熱性、熱拡散性と
ビアホール内面の導通膜のクラック防止性、防水性に優
れた電子回路基板、およびその様な基板を安価に製造す
る方法に係わるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit board which is excellent in heat removal, heat diffusion, crack prevention of a conductive film on the inner surface of a via hole, and waterproofness, and a method of manufacturing such a board at low cost. It is.

【0002】[0002]

【従来の技術】昨今、半導体の高密度化が進み、電子回
路基板の多層化は世の趨勢である。この結果、基板の上
下面を導通するためのビアホールの数も大幅に増加して
いる。現在、基板材料としては、エポキシ樹脂、または
ビスマールド、イミド樹脂にガラス繊維、ケプラ繊維あ
るいは金属繊維等が混ざった、いわゆるガラス・エポキ
シ、フェノール樹脂、BT樹脂、ポリイミド樹脂等の樹
脂材料が一般的に使用され、これらの樹脂基板には必要
に応じて金属基板が適宜積層され、あるいは必要に応じ
て異なった樹脂基板が適宜積層されて使用されている
が、これら樹脂基板の厚さ方向の熱膨張係数はおしなべ
て(60〜100)×10−6に達する。ビアホールの
導通膜の金属被膜は最も大きな銅被膜でも17〜18×
10−6程度であり、基板材料とは極端に熱膨張特性が
異なる。半導体の信頼性のテスト項目の中に−60℃×
30分−155℃×30分のヒートサイルを繰り返す熱
疲労テストがあるが、この時、基板は数十ミクロン伸縮
するのにたいし、導通膜はこの1/3程度伸縮するのみ
で、基板の伸縮に十分追随することができない。この結
果、導通膜に引っ張りの熱応力が作用し、クラックが発
生し、電気特性の劣化となり、水分の吸水を招く結果と
なり、リフロー半田処理のときポップコーンの発生の原
因となる。また、基板内部のガラス繊維の界面にもクラ
ックが発生し、PCTテストで水が浸入する。また更に
基板自体に反りが発生する。また一方電子回路基板の最
近の傾向は、高電流を使用するためにチップのジャンク
ション部分の発熱が多くなり、この部分を過昇温させな
いために熱を拡散、放熱させることが重要な問題になっ
ており、現状ではチップの下面にヒートシンクやヒート
スプレッダーを装着して熱を拡散、放熱しているが、こ
のヒートシンクやヒートスプレッダーの装着は基板全体
のコスト高を招く。ヒートシンクやヒートスプレッダー
は可能な限り縮小、あるいは省略することが好ましい。
また一方、従来の電子回路基板はビアホールの部分は空
孔になっているので、配線回路を積層する場合、この空
孔部分は避けて積層させる必要があるために、配線回路
を高密度に積層することができない欠点もある。ビアホ
ールの上にいかにして配線回路を載せるかということ
は、高密度化に当たって極めて重要な課題である。
2. Description of the Related Art In recent years, the density of semiconductors has been increased, and the multilayer structure of electronic circuit boards has been a worldwide trend. As a result, the number of via holes for conducting between the upper and lower surfaces of the substrate has been greatly increased. At present, resin materials such as so-called glass-epoxy, phenolic resin, BT resin, and polyimide resin in which glass fiber, kepra fiber, or metal fiber are mixed with epoxy resin, bismald, imide resin, and the like are generally used as substrate materials. A metal substrate is appropriately laminated on these resin substrates as necessary, or a different resin substrate is appropriately laminated on the resin substrate as necessary.The thermal expansion in the thickness direction of these resin substrates is used. The coefficients generally reach (60-100) × 10 −6 . The metal film of the via hole conductive film is 17-18x even with the largest copper film.
The thermal expansion characteristic is about 10 −6 , which is extremely different from that of the substrate material. -60 ° C x in the test items of semiconductor reliability
There is a thermal fatigue test in which a heat sile is repeated for 30 minutes to 155 ° C. for 30 minutes. Can not follow enough. As a result, a tensile thermal stress acts on the conductive film, cracks are generated, electric characteristics are deteriorated, water is absorbed, and popcorn is generated during reflow soldering. In addition, cracks also occur at the interface of the glass fibers inside the substrate, and water enters in the PCT test. Further, the substrate itself is warped. On the other hand, the recent trend of electronic circuit boards is that the use of a high current increases the heat generated at the junction of the chip, and it is important to spread and dissipate the heat in order not to overheat this part. At present, a heat sink or a heat spreader is attached to the lower surface of the chip to diffuse and dissipate heat, but the attachment of the heat sink or the heat spreader increases the cost of the entire substrate. It is preferable that the heat sink and the heat spreader are reduced or omitted as much as possible.
On the other hand, conventional electronic circuit boards have holes in the via holes, so when wiring circuits are stacked, it is necessary to avoid these holes and stack them. There are disadvantages that cannot be done. How to place a wiring circuit on a via hole is a very important issue in increasing the density.

【0003】[0003]

【発明が解決しようとする課題】本発明は、かかる状況
に鑑みてなされたもので、その目的とするところは、上
記した熱疲労によるクラックの問題、水の浸入の問題、
基板の反りの問題、およびヒートシンク、ヒートスプレ
ッダーを使用することによるコストアップの問題、さら
に配線回路の高密度化の問題を同時に解決できる電子回
路基板の新しい構造およびその製造方法を提供せんとす
るものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object the following problems of cracks due to thermal fatigue, problems of water intrusion,
A new structure of an electronic circuit board and a method of manufacturing the same that can simultaneously solve the problem of substrate warpage, the problem of cost increase by using a heat sink and a heat spreader, and the problem of higher density of wiring circuits. It is.

【0004】[0004]

【課題を解決するための手段】本発明者は上記問題に関
して鋭意研究を行った結果、次の知見を得た。すなわ
ち、 1.絶縁基材を貫通するビアホール内面に導通膜が形成
されてなる電子回路基板において、該絶縁基材の構造
を、繊維強化樹脂からなる芯材の両面に高熱伝導性で電
気絶縁性フィラーが混合された高熱伝導性樹脂層を積層
一体化した構造にし、該導通膜内面の空孔に、高熱伝導
性で電気絶縁性フィラーが混合され、かつ該導通膜の金
属と同等以下の低い熱膨張特性を有する高熱伝導性樹脂
を充填して、該充填樹脂と導通膜を接着した構造にする
と、導通膜のクラック、ガラス繊維界面のクラックの問
題、基板の反りの問題が解決され、しかも基材の熱拡散
性、放熱性が顕著に改善され、この結果ヒートシンク、
ヒートスプレッダーを完全省略あるいは大巾省略できる
ことを見出だした。また、 2.樹脂基板の両面に配線回路が積層一体化され、該両
面の配線回路を導通させるために該基板を貫通するビア
ホール内面に導通膜が形成されてなる電子回路基板にお
いて、該導通膜内面の空孔を、高熱伝導性で電気絶縁性
フィラーが混合された電気絶縁性で、かつ該導通膜の金
属と同等以下の低い熱膨張特性を有する高熱伝導性樹脂
で充填して封孔してなると共に、該配線回路の上に絶縁
層を挟んでさらに一層あるいは多層の配線回路を積層一
体化させ、該積層した回路は該封孔した空孔部の上に堆
積するようにしても、充填樹脂の線膨張係数を銅回路の
それよりも小さくできるために回路との密着性に優れ、
しかも高密度に積層できることを見出だした。またこの
時、導通膜のクラック、ガラス繊維界面のクラックの問
題、基板の反りの問題、熱拡散、放熱の問題も同時に解
決できることを見出だした。また、 3.樹脂基板の両面に配線回路が積層一体化され、該両
面の配線回路を導通させるために該基板を貫通するビア
ホール内面に導通膜が形成されてなる電子回路基板にお
いて、該樹脂基板の構造を、繊維強化樹脂からなる芯材
の両面に高熱伝導性で電気絶縁性フィラーが混合された
高熱伝導性樹脂層を積層一体化した構造にし、該導通膜
内面の空孔を、高熱伝導性で電気絶縁性フィラーが混合
された電気絶縁性で、かつ該導通膜の金属と同等以下の
低い熱膨張特性を有する高熱伝導性樹脂で充填して封孔
し、さらに該配線回路の上に絶縁層を挟んでさらに一層
あるいは多層の配線回路を積層一体化させ、該積層した
回路は該封孔した空孔部の上に堆積するようにすると、
導通膜のクラック、ガラス繊維界面のクラックの問題、
基板の反りの問題、配線回路の高密度積層の問題が解決
され、しかも基材の熱拡散性、放熱性が顕著に改善さ
れ、この結果ヒートシンク、ヒートスプレッダーを完全
省略あるいは大巾省略できることを見出だした。また、 4.上記高熱伝導性で電気絶縁性フィラーには、(窒化
アルミニウム、炭化ケイ素、マグネシア、アルミナ)の
中から選ばれた一種あるいは二種以上のセラミックフィ
ラーがとくに好ましいこと。また、 5.上記高熱伝導性樹脂層の中のフィラーの量は20〜
85wt%の範囲がとくに好ましいこと。そして 6.上記充填樹脂の中のフィラーの量は、20〜85w
t%の範囲が好ましいこと。そして 7.上記高熱伝導性樹脂層は高熱伝導性樹脂のフィルム
が最も好ましいこと。 8.ビアホールの上に配線回路を載せる課題、およびヒ
ートシンクやヒートスプレッダーを縮小、あるいは省略
する課題を解決できる多層電子回路基板の新しい製法。 本発明は以上の知見に基づいてなされたもので下記の構
成よりなる。
Means for Solving the Problems The present inventor has made intensive studies on the above problems and obtained the following findings. That is, 1. In an electronic circuit board in which a conductive film is formed on an inner surface of a via hole penetrating an insulating base material, the structure of the insulating base material is mixed with a high thermal conductive and electrically insulating filler on both surfaces of a core material made of fiber reinforced resin. A high thermal conductive resin layer is laminated and integrated, and pores on the inner surface of the conductive film are mixed with an electrically insulating filler having high thermal conductivity, and have a low thermal expansion characteristic equal to or less than that of the metal of the conductive film. By filling the high thermal conductive resin with the resin and bonding the conductive film to the conductive resin, the problem of cracks in the conductive film, cracks at the glass fiber interface, and warpage of the substrate can be solved. Diffusion and heat dissipation are significantly improved, resulting in heat sink,
It has been found that the heat spreader can be omitted completely or widely. Also, 2. In an electronic circuit board in which a wiring circuit is laminated and integrated on both surfaces of a resin substrate and a conductive film is formed on an inner surface of a via hole penetrating the substrate in order to make the wiring circuits on both surfaces conductive, holes on the inner surface of the conductive film Is filled with a high thermal conductive resin having a high thermal conductivity and an electrically insulating filler mixed with an electrically insulating filler, and having a low thermal expansion characteristic equal to or less than that of the metal of the conductive film, and sealing, and Even if one or more multilayer wiring circuits are laminated and integrated on the wiring circuit with an insulating layer interposed therebetween, and the laminated circuit is deposited on the sealed hole, Because the expansion coefficient can be smaller than that of copper circuit, it has excellent adhesion to the circuit,
In addition, they have found that they can be stacked at a high density. At this time, it was also found that the problem of cracks in the conductive film, the cracks in the glass fiber interface, the problem of substrate warpage, the problem of heat diffusion, and the problem of heat dissipation can be solved at the same time. Also, 3. A wiring circuit is laminated and integrated on both sides of the resin substrate, and in an electronic circuit board in which a conductive film is formed on an inner surface of a via hole penetrating the substrate to make the wiring circuits on both sides conductive, the structure of the resin substrate is A high thermal conductive resin layer mixed with a high thermal conductive and electrically insulating filler is laminated and integrated on both sides of a core material made of fiber reinforced resin, and the holes on the inner surface of the conductive film are electrically insulated with high thermal conductivity. Filled with a high thermal conductive resin having a low thermal expansion property equal to or less than the metal of the conductive film, mixed with a conductive filler, and sealed, and further an insulating layer is sandwiched on the wiring circuit. Then, one or more wiring circuits are laminated and integrated, and the laminated circuit is deposited on the sealed hole portion.
The problem of cracks in the conductive film, cracks in the glass fiber interface,
The problem of substrate warpage and the problem of high-density lamination of wiring circuits have been solved, and the heat diffusion and heat dissipation of the substrate have been significantly improved. As a result, the heat sink and heat spreader can be omitted completely or largely. I started. Also, 4. One or more ceramic fillers selected from among (aluminum nitride, silicon carbide, magnesia, and alumina) are particularly preferable as the high thermal conductive and electrically insulating filler. Also, 5. The amount of the filler in the high thermal conductive resin layer is 20 to
The range of 85% by weight is particularly preferable. And 6. The amount of the filler in the filling resin is 20 to 85 w
The range of t% is preferable. And 7. The high thermal conductive resin layer is most preferably a film of a high thermal conductive resin. 8. A new method of manufacturing a multilayer electronic circuit board that can solve the problem of mounting wiring circuits on via holes and the problem of reducing or eliminating heat sinks and heat spreaders. The present invention has been made based on the above findings, and has the following configuration.

【0005】(1)絶縁基材<101>を貫通するビア
ホール<102>内面に導通膜<103>が形成されて
なる電子回路基板において、該絶縁基材<101>は繊
維強化樹脂からなる芯材<104>の両面に高熱伝導性
で電気絶縁性フィラーが混合された高熱伝導性樹脂層<
105>が積層一体化された構造からなり、該導通膜<
103>内面の空孔<102>は、高熱伝導性で電気絶
縁性フィラーが混合され、かつ該導通膜<103>の金
属と同等以下の低い熱膨張特性を有する高熱伝導性樹脂
を充填され、該充填樹脂と導通膜が接着されてなること
を特徴とする電子回路基板。(図1参照)
(1) In an electronic circuit board having a conductive film <103> formed on an inner surface of a via hole <102> penetrating an insulating base material <101>, the insulating base material <101> is a core made of fiber reinforced resin. High thermal conductive resin layer in which high thermal conductive and electrically insulating filler is mixed on both sides of material <104>
105> has a laminated and integrated structure, and the conductive film <
103> inner pores <102> are filled with a high thermal conductive resin having a high thermal conductivity and an electrically insulating filler mixed therein and having a low thermal expansion characteristic equal to or less than that of the metal of the conductive film <103>; An electronic circuit board, wherein the filling resin and the conductive film are bonded. (See Fig. 1)

【0006】(2)樹脂基板<201>の両面に配線回
路<206>が積層一体化され、該両面の配線回路<2
06>を導通させるために該基板<201>を貫通する
ビアホール<202>内面に導通膜<203>が形成さ
れてなる電子回路基板において、該導通膜<203>内
面の空孔<202>を、高熱伝導性で電気絶縁性フィラ
ーが混合された電気絶縁性で、かつ該導通膜<203>
の金属と同等以下の低い熱膨張特性を有する高熱伝導性
樹脂で充填して封孔してなると共に、該配線回路<20
6>の上に絶縁層<207>を挟んでさらに一層あるい
は多層の配線回路<208>を積層一体化させ、該積層
した回路<208>は該封孔した空孔部<202>の上
に堆積するようにしてなることを特徴とする電子回路基
板。(図2参照)。
(2) Wiring circuits <206> are laminated and integrated on both sides of the resin substrate <201>, and the wiring circuits <2> on both sides are integrated.
In the electronic circuit board having a conductive film <203> formed on an inner surface of a via hole <202> penetrating the substrate <201> to make the conductive film 06> conductive, a hole <202> on the inner surface of the conductive film <203> is formed. An electrically insulating material mixed with an electrically insulating filler having a high thermal conductivity, and the conductive film <203>
And filled with a high thermal conductive resin having a low thermal expansion property equal to or less than the metal of
6>, an insulating layer <207> is interposed therebetween to further integrate a single-layer or multilayer wiring circuit <208>, and the laminated circuit <208> is placed on the sealed hole portion <202>. An electronic circuit board characterized by being deposited. (See FIG. 2).

【0007】(3)樹脂基板<201>の両面に配線回
路<206>が積層一体化され、該両面の配線回路<2
06>を導通させるために該基板<201>を貫通する
ビアホール<202>内面に導通膜<203>が形成さ
れてなる電子回路基板において、該樹脂基板<201>
は繊維強化樹脂からなる芯材<204>の両面に高熱伝
導性で電気絶縁性フィラーが混合された高熱伝導性樹脂
層<205>が積層一体化された構造であって、該導通
膜<203>内面の空孔<202>が、高熱伝導性で電
気絶縁性フィラーが混合された電気絶縁性で、かつ該導
通膜の金属と同等以下の低い熱膨張特性を有する高熱伝
導性樹脂で充填されて封孔されてなり、該配線回路<2
06>の上に絶縁層<207>を挟んでさらに一層ある
いは多層の配線回路<208>を積層一体化させ、該積
層した回路<208>は該封孔した空孔部<202>の
上に堆積するようにしてなることを特徴とする電子回路
基板。(図2参照)。
(3) A wiring circuit <206> is laminated and integrated on both sides of the resin substrate <201>, and the wiring circuits <2>
06>, an electronic circuit board having a conductive film <203> formed on the inner surface of a via hole <202> penetrating through the substrate <201> to conduct the resin substrate <201>.
Has a structure in which a high thermal conductive resin layer <205> in which a high thermal conductive and electrically insulating filler is mixed is laminated and integrated on both surfaces of a core material <204> made of a fiber reinforced resin, and the conductive film <203>> The pores <202> on the inner surface are filled with a high thermal conductive resin having high thermal conductivity, an electrically insulating filler mixed with an electrically insulating filler, and having a low thermal expansion property equal to or lower than that of the metal of the conductive film. And the wiring circuit is <2
06>, an insulating layer <207> is interposed therebetween, and a one-layer or multi-layer wiring circuit <208> is laminated and integrated, and the laminated circuit <208> is placed on the sealed hole portion <202>. An electronic circuit board characterized by being deposited. (See FIG. 2).

【0008】(4)上記高熱伝導性で電気絶縁性フィラ
ーが、(窒化アルミニウム、炭化ケイ素、マグネシア、
アルミナ)の中から選ばれた一種あるいは二種以上のセ
ラミックフィラーである上記1〜3のいずれかに記載の
電子回路基板。
(4) The high thermal conductive and electrically insulating filler comprises (aluminum nitride, silicon carbide, magnesia,
4. The electronic circuit board according to any one of the above 1 to 3, which is one or more ceramic fillers selected from alumina).

【0009】(5)上記高熱伝導性樹脂層の中のフィラ
ーの量が20〜85wt%である上記1〜3のいずれか
に記載の電子回路基板。
(5) The electronic circuit board as described in any one of (1) to (3) above, wherein the amount of the filler in the high thermal conductive resin layer is 20 to 85 wt%.

【0010】(6)上記充填樹脂の中のフィラーの量が
20〜85wt%である上記1〜3のいずれかに記載の
電子回路基板。
(6) The electronic circuit board as described in any one of (1) to (3) above, wherein the amount of the filler in the filling resin is 20 to 85% by weight.

【0011】(7)上記高熱伝導性樹脂層が高熱伝導性
樹脂フィルムである上記1〜6のいずれかに記載の電子
回路基板。
(7) The electronic circuit board as described in any one of (1) to (6) above, wherein the high thermal conductive resin layer is a high thermal conductive resin film.

【0012】(8)樹脂基板<301>の両面に第1の
配線回路<306>が積層一体化され、該基板<301
>を貫通するビアホール<302>内面に該両面の第1
の配線回路<306>を導通させる導通膜<303>が
形成されてなる電子回路基板の、該ビアホールの導通膜
<303>内面の空孔部<302>に高熱伝導性で電気
絶縁性セラミックフィラーが混合された樹脂を充填する
工程(1)と、該ビアホール空孔<302>が該樹脂で
充填された電子回路基板の上に、高熱伝導性で電気絶縁
性セラミックフィラーが混合された第1の樹脂層<30
7(1)>をB−ステージ化させた状態で積層一体化さ
せる工程(2)と、該第1の樹脂層<307(1)>の
上に、金属箔<308>の片面に高熱伝導性で電気絶縁
性セラミックフィラーが混合された第2の樹脂層<30
7(2)>が積層一体化された構造の金属箔とBステー
ジ化樹脂膜の積層体の、該樹脂膜側を重ね合せ、圧着、
加熱して該第1の樹脂層<307(1)>と第2の樹脂
層<307(2)>を接着、硬化させる工程(3)と、
該金属箔をエッチングして第2の配線回路<308>を
形成する工程(4)と、 第1の該配線回路<306>
と第2の配線回路<308>の間に連通孔を穿孔する工
程(5)と、該穿孔した連通孔の内面にメッキによって
導電層を形成して第1の配線回路、306。と第2の配
線回路<308>を電気的に導通させる工程(6)を備
えてなり、逐次(1)〜(6)の工程を繰り返して配線
回路を多層化することを特徴とする多層電子回路基板の
製造方法。(図3参照)
(8) A first wiring circuit <306> is laminated and integrated on both sides of the resin substrate <301>, and the substrate <301>
> On the inner surface of the via hole <302>
In the electronic circuit board on which the conductive film <303> for conducting the wiring circuit <306> is formed, the hole portion <302> on the inner surface of the conductive film <303> of the via hole has a high thermal conductive and electrically insulating ceramic filler. (1) filling a resin in which the via hole vacancy <302> is filled with the resin, and a first heat-conductive and electrically insulating ceramic filler mixed on the electronic circuit board filled with the resin. Resin layer <30
7 (1)> is laminated and integrated in a B-staged state, and the first resin layer <307 (1)> has a high thermal conductivity on one side of a metal foil <308>. Second resin layer mixed with conductive and electrically insulating ceramic filler <30
7 (2)>, the resin film side of the laminated body of the metal foil and the B-staged resin film having the structure in which the laminate is integrated and laminated, and pressure-bonded.
(3) heating to bond and cure the first resin layer <307 (1)> and the second resin layer <307 (2)>;
(4) forming the second wiring circuit <308> by etching the metal foil; and the first wiring circuit <306>.
A step (5) of drilling a communication hole between the first wiring circuit and the second wiring circuit <308>, and forming a conductive layer by plating on the inner surface of the drilled communication hole; And a step (6) for electrically connecting the second wiring circuit <308> to the second wiring circuit <308>, and the steps (1) to (6) are sequentially repeated to make the wiring circuit multilayer. A method for manufacturing a circuit board. (See Fig. 3)

【0013】(9)上記第1の樹脂層<307(1)>
と第2の樹脂層<307(2)>を接着、硬化させる方
法が、第1の樹脂層と第2の樹脂層を一端から順次連続
的に圧着、加熱して接着硬化させる方法である請求項8
に記載の多層配線板の製造方法。(図3参照)
(9) The first resin layer <307 (1)>
The method of bonding and curing the first resin layer and the second resin layer <307 (2)> is a method of successively pressing and heating the first resin layer and the second resin layer from one end and heating to bond and cure. Item 8
3. The method for producing a multilayer wiring board according to item 1. (See Fig. 3)

【0014】(10)上記一端から順次連続的に圧着さ
せる方法が、ロール<309>圧着である上記9に記載
の電子回路基板の製造方法。(図3参照)
(10) The method of manufacturing an electronic circuit board according to the above item 9, wherein the method of successively pressing the rolls sequentially from one end is roll <309> pressure bonding. (See Fig. 3)

【0015】[0015]

【発明の実施の形態】以下、本発明の電子回路基板の各
構成要素および本発明の電子回路基板の製造方法の各工
程を詳細を説明する(図1〜3を参照)。 [工程1:絶縁基材の構成]樹脂基材には、第1の配線
回路(一般には銅配線回路)が積層一体化され、基板を
貫通するビアホール内面には基板両面の配線回路を電気
的に導通させるための導通膜が形成されている。現在、
回路基板の絶縁基材には、ガラス・エポキシ、フェノー
ル樹脂、BT樹脂、ポリイミド樹脂、あるいはセラミッ
クスと有機材料のハイブリッド基材からなる絶縁基材等
々が使用され、通常これらの樹脂とガラス繊維が複合さ
れた、いわゆる繊維強化樹脂の形で使用されている。本
発明の絶縁基材は通常使用されているこれらの基材はそ
のまますべて使用できる。本発明の絶縁基材は、これら
の繊維強化された樹脂基板を芯材として両面に電気絶縁
性で、高熱伝導性の樹脂の層が積層一体化されている。
また、ビアホール内面に形成された導通膜の内面空孔部
にも電気絶縁性で、高熱伝導性の樹脂が充填され、かつ
充填樹脂と導通膜は接着された状態で封孔されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, each component of the electronic circuit board of the present invention and each step of the method of manufacturing the electronic circuit board of the present invention will be described in detail (see FIGS. 1 to 3). [Step 1: Configuration of Insulating Base] A first wiring circuit (generally, a copper wiring circuit) is laminated and integrated on a resin base, and wiring circuits on both sides of the substrate are electrically connected to inner surfaces of via holes penetrating the substrate. A conduction film for conducting the electric current is formed. Current,
Insulating base materials for circuit boards include glass epoxy, phenolic resin, BT resin, polyimide resin, and insulating base materials consisting of hybrid base materials of ceramics and organic materials. These resins are usually combined with glass fibers. Used in the form of so-called fiber reinforced resin. As the insulating substrate of the present invention, all of these commonly used substrates can be used as they are. The insulating base material of the present invention is formed by laminating and integrating a resin layer having electrical insulation and high thermal conductivity on both sides using the fiber-reinforced resin substrate as a core material.
Also, the inner surface vacancy of the conductive film formed on the inner surface of the via hole is filled with an electrically insulating resin having high thermal conductivity, and the filled resin and the conductive film are sealed and bonded.

【0016】本発明第一工程では、導通膜内面の空孔に
高熱伝導性で電気絶縁性セラミックフィラーが混合され
た樹脂を充填する。電気絶縁性で、高熱伝導性の樹脂と
は、エポキシ樹脂、フェノール樹脂、BT樹脂、ポリイ
ミド樹脂等々の樹脂基材に電気絶縁性で高熱伝導性のセ
ラミックフィラーが混合されたものである。ここでフィ
ラーとは、粉末、繊維状の骨材である。
In the first step of the present invention, pores on the inner surface of the conductive film are filled with a resin mixed with an electrically insulating ceramic filler having high thermal conductivity. The electrically insulating and high heat conductive resin is a resin base material such as an epoxy resin, a phenol resin, a BT resin, and a polyimide resin mixed with an electrically insulating and high heat conductive ceramic filler. Here, the filler is a powder or a fibrous aggregate.

【0017】セラミックはおしなべて樹脂に比較して極
めて低膨脹性である。したがってセラミックフィラーを
樹脂に混合すると、その混合された樹脂は線膨脹係数が
著しく小さくなる。
[0017] Ceramics are generally very low expansion in comparison to resins. Therefore, when a ceramic filler is mixed with a resin, the mixed resin has a significantly low linear expansion coefficient.

【0018】セラミックフィラーは、電気絶縁性、高熱
伝導性あれば、ほとんどすべてのセラミック粉末、繊維
を使用できる。窒化アルミニウム、炭化ケイ素、マグネ
シア、アルミナ、窒化ボロン、ダイヤモンド等を適宜使
用できる。とりわけ窒化アルミニウム、炭化ケイ素、マ
グネシア、アルミナは好適である。これらの粉末、繊維
は一種あるいは必要に応じて二種以上を適宜混合して使
用できる。また、これら以外の例えば、溶融シリカ、ム
ライト、コージライト、ジルコン、チタン酸アルミナ、
ジルコニア、スピネル、クロミア等のあるいはこれらの
複合セラミック等々は膨脹係数の調整等の目的で、必要
に応じて適宜混合して使用してよい。
Almost all ceramic powders and fibers can be used as long as they are electrically insulating and have high thermal conductivity. Aluminum nitride, silicon carbide, magnesia, alumina, boron nitride, diamond, and the like can be used as appropriate. Particularly, aluminum nitride, silicon carbide, magnesia, and alumina are preferable. These powders and fibers can be used alone or, if necessary, in a mixture of two or more. In addition, other than these, for example, fused silica, mullite, cordierite, zircon, alumina titanate,
Zirconia, spinel, chromia, and the like, or composite ceramics thereof, may be used by mixing as appropriate for the purpose of adjusting the expansion coefficient.

【0019】なお、導通膜の空孔に充填する電気絶縁
性、高熱伝導性の樹脂と導通膜は接着されていることが
必要で、接着されていない場合、導通膜に対する補強効
果は発生しない。充填した樹脂は導通膜の機械的強度を
補強し、導通膜に作用する引っ張りの応力に対抗できる
ようにしたものである。充填した樹脂の熱膨脹係数は絶
縁基板の熱膨脹係数以下、さらに好ましくは導通膜の熱
膨脹係数値以下が好適である。充填材料の熱膨張特性が
絶縁基板の熱膨脹係数を越えると、基板の伸びに抗して
充填材が導通膜の伸びを抑制する効果は発生しない。ま
た、更に充填材料として導通膜の熱膨脹係数値以下の熱
膨脹係数を有する材料を選択すると、導通膜には常に圧
縮の補強応力が作用し、クラックが発生しなくなる。こ
のクラック抑制効果は、導通膜のみならず絶縁基板に対
しても有効で、ガラス繊維界面のクラックおよびソルダ
ーレジストのくラックを抑制する。また、基板の反りの
解消にも有効に作用する。
Note that it is necessary that the conductive film and the electrically insulating and high heat conductive resin filling the pores of the conductive film are bonded to each other. If the resin is not bonded, the reinforcing effect on the conductive film does not occur. The filled resin reinforces the mechanical strength of the conductive film and can resist the tensile stress acting on the conductive film. The thermal expansion coefficient of the filled resin is preferably equal to or less than the thermal expansion coefficient of the insulating substrate, and more preferably equal to or less than the thermal expansion coefficient of the conductive film. If the thermal expansion characteristic of the filling material exceeds the thermal expansion coefficient of the insulating substrate, the effect of the filler suppressing the expansion of the conductive film against the elongation of the substrate does not occur. Further, when a material having a thermal expansion coefficient equal to or less than the thermal expansion coefficient value of the conductive film is selected as the filling material, a compressive reinforcing stress always acts on the conductive film, so that cracks do not occur. This crack suppression effect is effective not only for the conductive film but also for the insulating substrate, and suppresses cracks at the glass fiber interface and cracks in the solder resist. In addition, it effectively acts to eliminate the warpage of the substrate.

【0020】[工程2]ビアホール空孔に上記樹脂が充
填された基層となる電子回路基板の片面あるいは両面に
高熱伝導性で電気絶縁性セラミックフィラーが混合され
た樹脂層(以下第1の樹脂層と表現する)を塗着して完
全硬化させずに半硬化したBステージ状態で止めた状態
で積層一体化させる。
[Step 2] A resin layer (hereinafter referred to as a first resin layer) in which a high thermal conductive and electrically insulating ceramic filler is mixed on one or both sides of an electronic circuit board serving as a base layer in which via holes are filled with the above resin. (Completely cured) without being cured and stopped in a semi-cured B-stage state, and then laminated and integrated.

【0021】上記した基層となる電子回路基板の両面あ
るいは片面に積層させる電気絶縁性、高熱伝導性の樹脂
と絶縁基材のビアホールに充填する電気絶縁性、高熱伝
導性の樹脂の組成は、電気絶縁性、高熱伝導性のセラミ
ックフィラーが20〜85wt%混合された組成が好ま
しい。下限未満では十分な熱伝導性が得られないため
に、熱拡散、放熱性が十分でない。また、上限を越える
と樹脂が脆くなるので好ましくない。充填する樹脂と回
路基板に積層させる樹脂は必ずしも同一のものを使用し
なくてもよい。少なくともセラミックフィラーが上記組
成範囲のものであればよい。
The composition of the resin having high electrical conductivity and high thermal conductivity to be laminated on both sides or one side of the electronic circuit board serving as the base layer, and the resin having high electrical conductivity and high thermal conductivity to be filled in the via holes of the insulating base material are as follows. A composition in which an insulating and high thermal conductive ceramic filler is mixed in an amount of 20 to 85 wt% is preferable. If it is less than the lower limit, sufficient heat conductivity cannot be obtained, so that heat diffusion and heat dissipation are not sufficient. On the other hand, exceeding the upper limit is not preferable because the resin becomes brittle. The resin to be filled and the resin to be laminated on the circuit board need not always be the same. It is sufficient that at least the ceramic filler has the above composition range.

【0022】基層となる電子回路基板に積層させる電気
絶縁性、高熱伝導性の第1の樹脂層の厚さは20〜30
0ミクロンの範囲が好ましい。下限値未満では十分な放
熱性が得られない。また上限値を越えても放熱性は微増
するだけで、厚くするのはコストアップの原因となり、
経済的でない。層は上記組成の樹脂のペーストを塗布し
て形成してもよいし、またフィルムにしてこれを張り付
けるようにしてもよい。フィルムにして張り付ける場合
は、基材をエポキシ樹脂にして、これにセラミックフィ
ラーを混合してシートに加工したものをB・ステージ化
(半硬化)し、接着面をタッキー状態(粘着状)にして
基層の電子回路基板の面に重ね合わせて加熱硬化する方
法がよい。
The thickness of the electrically insulating and high thermal conductive first resin layer to be laminated on the electronic circuit board serving as the base layer is 20 to 30.
A range of 0 microns is preferred. If it is less than the lower limit, sufficient heat dissipation cannot be obtained. In addition, even if it exceeds the upper limit, the heat dissipation only slightly increases, and thickening causes cost increase,
Not economic. The layer may be formed by applying a resin paste having the above composition, or may be formed into a film and attached thereto. When sticking to a film, use epoxy resin as the base material, mix it with a ceramic filler and process it into a sheet. B-stage (semi-cured) and make the adhesive surface tacky (adhesive) It is preferable to use a method in which the substrate is superposed on the surface of the electronic circuit board of the base layer and cured by heating.

【0023】本発明では、芯材の両面に電気絶縁性、高
熱伝導性の樹脂層を形成するのが、ポイントで、片面だ
けでは、芯材と樹脂層の線膨脹係数が異なるので、反っ
てしまう。両面に接着することによって反りが解消され
ることとなる。また、両面に張り付けることによって、
表の熱がビアホールの高熱伝導性充填樹脂を通って裏面
に良く拡散して過昇温が防止できる。
In the present invention, the resin layer having electrical insulation and high thermal conductivity is formed on both sides of the core material. The point is that the core material and the resin layer have different linear expansion coefficients on only one side. I will. By bonding to both surfaces, the warpage is eliminated. Also, by sticking on both sides,
The heat of the front spreads well to the back surface through the highly thermally conductive filling resin of the via hole, so that excessive heating can be prevented.

【0024】[工程3]電気絶縁性、高熱伝導性のセラ
ミックフィラーが20〜85wt%混合された組成から
なり、かつBステージ化された状態の電気絶縁性、高熱
伝導性樹脂層(以下第2の樹脂層と表現する)が金属箔
(一般に銅箔)の片面に積層された構造の金属箔(銅
箔)と樹脂層の積層体を用意する。次にBステージ化さ
れた第2の樹脂層側を上記工程2で用意した第1の樹脂
層と重ね合わせ圧着加熱して第1の樹脂層と第2の樹脂
層を接着硬化させる。
[Step 3] An electrically insulating, highly thermally conductive resin layer (hereinafter referred to as a second layer) having a composition in which 20 to 85 wt% of an electrically insulating, highly thermally conductive ceramic filler is mixed and in a B-stage state. Of a metal foil (copper foil) and a resin layer having a structure in which a metal layer (generally referred to as a resin layer) is laminated on one side of a metal foil (generally a copper foil). Next, the B-staged second resin layer side is overlapped with the first resin layer prepared in the above step 2 and pressed and heated to bond and cure the first resin layer and the second resin layer.

【0025】[工程4]第2の樹脂層の表面の金属箔
(銅箔)をエッチングして第2の配線回路を形成する。
[Step 4] The metal foil (copper foil) on the surface of the second resin layer is etched to form a second wiring circuit.

【0026】[工程5]第1の配線回路と第2の配線回
路の間に連通孔を穿孔する。穿孔は正確に位置決めした
後、配線回路1を目掛けてCOガスレーザーで行うの
がよい。
[Step 5] A communication hole is formed between the first wiring circuit and the second wiring circuit. Drilling is preferably performed by a CO 2 gas laser with the wiring circuit 1 positioned after accurate positioning.

【0027】[工程6:導通膜の形成]穿孔した連通孔
内面にメッキによって電気的導通膜を形成する。導通膜
には通常銅メッキ膜が使用されているが、銅のみに限ら
ずニッケル、コバルト、金、銀等、通常のこの種の用途
に使用されている金属膜はすべて適用できる。導通膜は
単一金属膜に限らず、異種金属の積層膜でもすべて適用
できる。なお、上記した樹脂基材に銅、金、銀、ニッケ
ル等の金属微粉が混合されているとメッキ膜の密着強度
が改良されるので、樹脂基材の絶縁性が阻害されない範
囲でこれらの金属粉末を上記した絶縁基材に混合しても
よい。
[Step 6: Formation of Conductive Film] An electrically conductive film is formed on the inner surface of the drilled communication hole by plating. Although a copper plating film is usually used for the conductive film, not only copper but also a metal film used for ordinary applications of this kind, such as nickel, cobalt, gold, and silver, can be applied. The conductive film is not limited to a single metal film, and may be a laminated film of different metals. In addition, if the metal fine powder of copper, gold, silver, nickel, etc. is mixed with the above-mentioned resin base material, the adhesion strength of the plating film is improved. The powder may be mixed with the above-mentioned insulating base material.

【0028】以上[工程1]から[工程6]を逐次繰り
返して配線回路を多層化する。
The above-mentioned [Step 1] to [Step 6] are sequentially repeated to form a multilayered wiring circuit.

【0029】絶縁基材の上に形成された配線回路の上に
さらに絶縁膜を介して一層あるいはさらに多層の配線回
路を積層させる場合、つまりビルドアップ方式では、ビ
アホールの部分は空孔になっているためにこの部分を回
避して積層させる必要がある。空孔の存在によって配線
回路を高密度に積層できない場合が多い。本発明ではビ
アホール内面の導通膜内面の空孔は電気絶縁性、高熱伝
導性の樹脂で充填され、しかも充填樹脂の上に金属箔
(銅箔)が積層、接着され、この金属箔が配線回路とな
るので、空孔の上に配線回路が高密度に積層できること
になる。また第1、第2の樹脂層の熱膨張係数は、9〜
10×10−6程度で低膨脹であるために、積層させた
銅回路との密着性が向上し、剥離に対する信頼性が向上
する。ちなみに従来の絶縁基材を使用した場合の剥離強
度は約1.2kg程度、本発明では1.6〜1.8kg
に向上する。高密度実装と共に信頼性も向上する。
When a single-layer or multi-layer wiring circuit is further laminated on a wiring circuit formed on an insulating base material with an insulating film interposed therebetween, that is, in the build-up method, the via hole becomes a hole. Therefore, it is necessary to avoid this part and stack the layers. In many cases, wiring circuits cannot be stacked at high density due to the presence of holes. In the present invention, the pores on the inner surface of the conductive film on the inner surface of the via hole are filled with a resin having electrical insulation and high thermal conductivity, and a metal foil (copper foil) is laminated and bonded on the filled resin. Therefore, the wiring circuit can be densely stacked on the holes. The first and second resin layers have a coefficient of thermal expansion of 9 to 9.
Since the expansion is as low as about 10 × 10 −6 , the adhesion to the laminated copper circuit is improved, and the reliability against peeling is improved. Incidentally, the peel strength when a conventional insulating base material is used is about 1.2 kg, and in the present invention, 1.6 to 1.8 kg.
To improve. Reliability is improved with high-density mounting.

【0030】[0030]

【実施例】【Example】

実施例1 基材となる電子回路基板 : 27mm×27mm×
0.6mm厚さのガラスエポキシ基板を芯材とし、芯材
の両面に同じくBステージ化した30μmのエポキシ樹
脂フィルムを重ね、エポキシ樹脂フィルムの上にさらに
18μmの銅箔を重ね合せ、200℃で熱圧着した。エ
ポキシ樹脂フィルムの組成:窒化アルミニウム80、ア
ルミナ20の割合で混合されたセラミックフィラーを7
0%,エポキシ樹脂30%の割合で混ぜた組成。フィル
ムの厚さは、30μm。エポキシ樹脂フィルムの接着面
は粘着しやすいようにタッキー化した。圧着後、銅箔を
エッチングして第1の配線回路を形成した。配線回路形
成後、φ0.23mmの貫通孔を248個穿孔した。な
お、因みに配線基板の各層の熱膨脹係数は下記の通りで
あった。 エポキシ樹脂フィルムの熱膨脹係数:(13〜17)×
10−6 ガラスエポキシ基板芯材 厚さ方向(Z方向) 80〜100×10−6 X 方向 13〜15×10−6 Y 方向 13〜15×10−6 導通膜の形成 ビアホール内面に無電解銅メッキによって16ミクロン
の銅被膜を形成した。 [工程1]次に導通膜の内面空孔部に下記組成の充填材
を充填した。充填材の組成(商品名ハイソールCB01
5) エポキシ接着剤 18wt% (硬化剤含む) セラミックフィラー 82wt% セラミックフィラーの組成:窒化アルミニウム80%、
アルミナ20% 充填材の熱膨脹係数 X,Y,Z方向共 10〜1
3×10−6 充填材をビアホールに充填した後、180℃に2時間加
熱して硬化させた。 [工程2]下記組成の絶縁性、高熱伝導性樹脂を工程1
の両面の第1の銅配線回路の上に配線回路の高さに塗着
して、70℃に8時間加熱して半硬化させ、Bステージ
化した。 [工程3]銅箔とBステージ化した樹脂膜の積層体の製
造 20μmの銅箔にセラミックフィラーを混ぜた下記組成
のエポキシ樹脂フィルムを圧着して70℃に加熱して半
硬化(Bステージ)させた。次にエポキシ樹脂のBステ
ージ面を工程2の半硬化した樹脂面(両面)と重ね合
せ、圧着(圧力: 2.5kg/cm)し、150℃
に40分加熱して完全硬化させた。 [工程4]両面の銅箔をエッチングして第2の配線回路
を形成した。 [工程5]COガスレーザーで第2の配線回路と第1
の配線回路の間に連通孔を穿孔した。 [工程6]連通孔の内面に無電解銅メッキによって20
ミクロンの銅被膜を形成して回路1と2を電気的に導通
させた。以後[工程1]〜[工程6]の操作を3回繰り
返して合計7層積層された回路基板を製造した。
Example 1 Electronic circuit board serving as a base material: 27 mm × 27 mm ×
A glass epoxy substrate with a thickness of 0.6 mm is used as a core material, and a 30 μm epoxy resin film, also B-staged, is laminated on both sides of the core material, and an 18 μm copper foil is further laminated on the epoxy resin film. Thermocompression bonded. Composition of epoxy resin film: 7 ceramic fillers mixed at a ratio of 80 aluminum nitride and 20 alumina
0%, 30% epoxy resin composition. The thickness of the film is 30 μm. The adhesive surface of the epoxy resin film was made tacky to make it easy to stick. After the pressing, the copper foil was etched to form a first wiring circuit. After forming the wiring circuit, 248 through holes of φ0.23 mm were drilled. Incidentally, the thermal expansion coefficient of each layer of the wiring board was as follows. Thermal expansion coefficient of epoxy resin film: (13-17) ×
10-6 Glass epoxy substrate core material Thickness direction (Z direction) 80-100 × 10 -6 X direction 13-15 × 10 -6 Y direction 13-15 × 10 -6 Formation of conductive film Electroless copper on inner surface of via hole A 16 micron copper coating was formed by plating. [Step 1] Next, a filler having the following composition was filled in the inner surface pores of the conductive film. Filler composition (trade name Hysole CB01)
5) Epoxy adhesive 18 wt% (including curing agent) Ceramic filler 82 wt% Composition of ceramic filler: aluminum nitride 80%,
Alumina 20% Thermal expansion coefficient of filler X, Y, Z directions 10-1
After filling the via hole with 3 × 10 −6 filler, the material was cured by heating to 180 ° C. for 2 hours. [Step 2] Insulating and high thermal conductive resin having the following composition
Was applied to the height of the wiring circuit on the first copper wiring circuit on both sides of the substrate, and was heated to 70 ° C. for 8 hours to be semi-cured, thereby forming a B stage. [Step 3] Manufacture of laminate of copper foil and B-staged resin film A 20 μm copper foil mixed with an epoxy resin film having the following composition mixed with a ceramic filler is pressed, heated to 70 ° C., and semi-cured (B stage) I let it. Next, the B-stage surface of the epoxy resin is superimposed on the semi-cured resin surface (both surfaces) in step 2, pressed (at a pressure of 2.5 kg / cm 2 ), and heated at 150 ° C.
For 40 minutes to complete cure. [Step 4] A copper wiring on both sides was etched to form a second wiring circuit. [Step 5] Using a CO 2 gas laser, the second wiring circuit and the first wiring circuit
Communication holes were drilled between the wiring circuits. [Step 6] The inner surface of the communication hole is formed by electroless copper plating to be 20
Circuits 1 and 2 were electrically conducted by forming a micron copper coating. Thereafter, the operations of [Step 1] to [Step 6] were repeated three times to produce a circuit board having a total of seven laminated layers.

【0031】[特性] 実装密度の比較 従来のビアホールを迂回する場合に比べて本例の場合、
概ね3倍の実装密度が得られた。 熱疲労テスト −65℃×30分−155℃×30分のヒートサイクル
を2000回繰り返した。基板の反りは20ミクロン以
下であった。 水圧テスト 121℃、2気圧の水圧テストを行なった。従来のビア
ホールを迂回する構造のものに比較してほぼ95%以上
改善された。 クラックの発生状況 次に各ビアホールの断面を切断してクラックの発生状況
を調べた。各ビアホールの内面のメッキ層にはクラック
は皆無であった。また、基材のガラスエポキシのガラス
繊維界面にもクラックは認められなかった。因みに充填
材を充填していない、従来の配線基板ではビアホールの
約80%に導通膜のクラック、約95%にガラス繊維界
面にクラックが発生している。また基板にほとんど反り
は認められなかった。
[Characteristics] Comparison of Mounting Density Compared to the case of bypassing the conventional via hole,
The mounting density of about three times was obtained. Thermal fatigue test A heat cycle of −65 ° C. × 30 minutes to −155 ° C. × 30 minutes was repeated 2000 times. The warpage of the substrate was less than 20 microns. Water pressure test A water pressure test of 121 ° C. and 2 atm was performed. It is improved by about 95% or more compared to the conventional structure bypassing the via hole. Next, the section of each via hole was cut to examine the state of occurrence of cracks. There were no cracks in the plating layer on the inner surface of each via hole. No crack was observed at the glass fiber interface of the base glass epoxy. By the way, in the conventional wiring board which is not filled with the filler, cracks occur in the conductive film in about 80% of the via holes and cracks occur in the glass fiber interface in about 95% of the via holes. Also, the substrate was hardly warped.

【0032】放熱性テスト。 通常の回路基板では、LSIの下にヒートシンク、ヒー
トシンクの下にさらにヒートスプレダーを装着して使用
されるものについて、本例ではヒートスプレダーを省略
して実使用に供してみた。実使用時の温度上昇は従来品
に比べて有為な差異は認められず、ほとんど支障なく使
用できた。本発明はヒートスプレダーを省略して実使用
できることが確認できた。
Heat dissipation test. In a normal circuit board, a heat sink is mounted below the LSI and a heat spreader is further mounted below the heat sink. In this example, the heat spreader was omitted and used for actual use. There was no significant difference in the temperature rise during actual use compared to the conventional product, and it could be used without any hindrance. It was confirmed that the present invention can be actually used without the heat spreader.

【0033】製造コストの比較従来のビアホールを迂回
する構造の多層基板に比較して本発明構造のものは製造
コストを約半分に下げることができた。
Comparison of Manufacturing Cost The manufacturing cost of the structure of the present invention can be reduced to about half as compared with the conventional multilayer substrate having a structure bypassing the via hole.

【0034】[0034]

【発明の効果】【The invention's effect】

1.ビアホール内面の導通膜および基板材料のガラス繊
維界面のクラックの発生を防止できる。 2.基板の放熱性と熱拡散性が極めて優れている。 3.ビアホールの上に回路形成が可能になったために高
密度な実装が可能。 4.製造工程が簡単で不良率が極めて低い。 5.製造コストが安価。 6.スループットが極めて早い。
1. The generation of cracks at the interface between the conductive film on the inner surface of the via hole and the glass fiber of the substrate material can be prevented. 2. The heat dissipation and heat diffusion of the substrate are extremely excellent. 3. High-density mounting is possible because circuits can be formed on via holes. 4. The manufacturing process is simple and the defect rate is extremely low. 5. Low production cost. 6. Extremely fast throughput.

【手続補正書】[Procedure amendment]

【提出日】平成9年10月3日[Submission date] October 3, 1997

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】図面の簡単な説明[Correction target item name] Brief description of drawings

【補正方法】追加[Correction method] Added

【補正内容】[Correction contents]

【図面の簡単な説明】[Brief description of the drawings]

【図1】 図1は本発明の電子回路基板の構造の説明図FIG. 1 is an explanatory view of the structure of an electronic circuit board of the present invention.

【図2】 図2は本発明の電子回路基板の構造の説明図FIG. 2 is an explanatory diagram of a structure of an electronic circuit board of the present invention.

【図3】 図3は本発明の電子回路基板の製造方法の説
明図
FIG. 3 is an explanatory view of a method for manufacturing an electronic circuit board according to the present invention.

【符号の説明】 101…絶縁基材 102…ビアホール
103…導通膜 104…芯材 105…高熱伝導性樹脂層 201…樹脂基板 202…ビアホール
203…導通膜 204…芯材 205…高熱伝導性樹脂層 206…配線回路 207…絶縁層 208…配線回路 301…樹脂基板 302…ビアホール
303…導通膜 306…配線回路 307(1)…樹脂層 307(2)…樹脂層 308…金属箔 309…ロール
[Description of Signs] 101: Insulating base material 102: Via hole
103: Conductive film 104: Core material 105: High thermal conductive resin layer 201: Resin substrate 202: Via hole
203 ... conductive film 204 ... core material 205 ... high thermal conductive resin layer 206 ... wiring circuit 207 ... insulating layer 208 ... wiring circuit 301 ... resin substrate 302 ... via hole
303: conductive film 306: wiring circuit 307 (1): resin layer 307 (2): resin layer 308: metal foil 309: roll

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】絶縁基材を貫通するビアホール内面に導通
膜が形成されてなる電子回路基板において、該絶縁基材
は繊維強化樹脂からなる芯材の両面に高熱伝導性で電気
絶縁性フィラーが混合された高熱伝導性樹脂層が積層一
体化された構造からなり、該導通膜内面の空孔は、高熱
伝導性で電気絶縁性フィラーが混合され、かつ該導通膜
の金属と同等以下の低い熱膨張特性を有する高熱伝導性
樹脂を充填され、該充填樹脂と導通膜が接着されてなる
ことを特徴とする電子回路基板。
1. An electronic circuit board having a conductive film formed on an inner surface of a via hole penetrating an insulating base material, wherein the insulating base material has a high thermal conductive and electrically insulating filler on both surfaces of a core material made of fiber reinforced resin. It has a structure in which the mixed high thermal conductive resin layer is laminated and integrated, and the pores on the inner surface of the conductive film are mixed with an electrically insulating filler with high thermal conductivity, and are as low as the metal of the conductive film. An electronic circuit board, which is filled with a high thermal conductive resin having a thermal expansion characteristic, and the filled resin and a conductive film are bonded.
【請求項2】樹脂基板の両面に配線回路が積層一体化さ
れ、該両面の配線回路を導通させるために該基板を貫通
するビアホール内面に導通膜が形成されてなる電子回路
基板において、該導通膜内面の空孔を、高熱伝導性で電
気絶縁性フィラーが混合された電気絶縁性で、かつ該導
通膜の金属と同等以下の低い熱膨張特性を有する高熱伝
導性樹脂で充填して封孔してなると共に、該配線回路の
上に絶縁層を挟んでさらに一層あるいは多層の配線回路
を積層一体化させ、該積層した回路は該封孔した空孔部
の上に堆積するようにしてなることを特徴とする電子回
路基板。
2. An electronic circuit board comprising a resin substrate, on which wiring circuits are laminated and integrated on both surfaces, and a conductive film formed on an inner surface of a via hole penetrating the substrate to conduct the wiring circuits on both surfaces. The pores on the inner surface of the film are filled with a high thermal conductive resin having high thermal conductivity, an electrically insulating filler mixed with an electrically insulating filler, and a low thermal expansion property equal to or less than the metal of the conductive film. In addition, one or more multilayer wiring circuits are laminated and integrated on the wiring circuit with an insulating layer interposed therebetween, and the laminated circuit is deposited on the sealed hole. An electronic circuit board, characterized in that:
【請求項3】樹脂基板の両面に配線回路が積層一体化さ
れ、該両面の配線回路を導通させるために該基板を貫通
するビアホール内面に導通膜が形成されてなる電子回路
基板において、該樹脂基板は繊維強化樹脂からなる芯材
の両面に高熱伝導性で電気絶縁性フィラーが混合された
高熱伝導性樹脂層が積層一体化された構造であって、該
導通膜内面の空孔が、高熱伝導性で電気絶縁性フィラー
が混合された電気絶縁性で、かつ該導通膜の金属と同等
以下の低い熱膨張特性を有する高熱伝導性樹脂で充填さ
れて封孔されてなり、該配線回路の上に絶縁層を挟んで
さらに一層あるいは多層の配線回路を積層一体化させ、
該積層した回路は該封孔した空孔部の上に堆積するよう
にしてなることを特徴とする電子回路基板。
3. An electronic circuit board comprising: a resin substrate having wiring circuits laminated and integrated on both surfaces thereof; and a conductive film formed on an inner surface of a via hole penetrating the substrate to conduct the wiring circuits on both surfaces. The substrate has a structure in which a high thermal conductive resin layer in which a high thermal conductive and electrically insulating filler is mixed is laminated and integrated on both surfaces of a core material made of a fiber reinforced resin, and the pores on the inner surface of the conductive film have high heat. A conductive and electrically insulating filler mixed with an electrically insulating material, and filled and sealed with a high thermal conductive resin having a low thermal expansion property equal to or less than the metal of the conductive film, and the wiring circuit has A single or multilayer wiring circuit is laminated and integrated with an insulating layer on top,
An electronic circuit board, wherein the laminated circuit is deposited on the closed hole.
【請求項4】上記高熱伝導性で電気絶縁性フィラーが、
(窒化アルミニウム、炭化ケイ素、マグネシア、アルミ
ナ)の中から選ばれた一種あるいは二種以上のセラミッ
クフィラーである請求項1〜3のいずれかに記載の電子
回路基板。
4. The high thermal conductive and electrically insulating filler according to claim 1,
The electronic circuit board according to any one of claims 1 to 3, which is one or more ceramic fillers selected from (aluminum nitride, silicon carbide, magnesia, and alumina).
【請求項5】上記高熱伝導性樹脂層の中のフィラーの量
が20〜85wt%である請求項1〜3のいずれかに記
載の電子回路基板。
5. The electronic circuit board according to claim 1, wherein the amount of the filler in the high thermal conductive resin layer is 20 to 85 wt%.
【請求項6】上記充填樹脂の中のフィラーの量が20〜
85wt%である請求項1〜3のいずれかに記載の電子
回路基板。
6. The amount of the filler in the filling resin is 20 to 20.
The electronic circuit board according to claim 1, wherein the content is 85 wt%.
【請求項7】上記高熱伝導性樹脂層が高熱伝導性樹脂フ
ィルムである請求項1〜6のいずれかに記載の電子回路
基板。
7. The electronic circuit board according to claim 1, wherein said high thermal conductive resin layer is a high thermal conductive resin film.
【請求項8】樹脂基板の両面に第1の配線回路が積層一
体化され、該基板を貫通するビアホール内面に該両面の
第1の配線回路を導通させる導通膜が形成されてなる電
子回路基板の、該ビアホールの導通膜内面の空孔部に高
熱伝導性で電気絶縁性セラミックフィラーが混合された
樹脂を充填する工程(1)と、 該ビアホール空孔が該樹脂で充填された電子回路基板の
上に、高熱伝導性で電気絶縁性セラミックフィラーが混
合された第1の樹脂層をB−ステージ化させた状態で積
層一体化させる工程(2)と、 該第1の樹脂層の上に、金属箔の片面に高熱伝導性で電
気絶縁性セラミックフィラーが混合された第2の樹脂層
が積層一体化された構造の金属箔とBステージ化樹脂膜
の積層体の、該樹脂膜側を重ね合せ、圧着、加熱して該
第1の樹脂層と第2の樹脂層を接着、硬化させる工程
(3)と、 該金属箔をエッチングして第2の配線回路を形成する工
程(4)と、 該第1の配線回路と第2の配線回路の間に連通孔を穿孔
する工程(5)と、該穿孔した連通孔の内面にメッキに
よって導電層を形成して第2の配線回路と第1の配線回
路を電気的に導通させる工程(6)を備えてなり、逐次
(1)〜(6)の工程を繰り返して配線回路を多層化す
ることを特徴とする多層電子回路基板の製造方法。
8. An electronic circuit board in which first wiring circuits are laminated and integrated on both surfaces of a resin substrate, and a conductive film for conducting the first wiring circuits on both surfaces is formed on an inner surface of a via hole penetrating the substrate. (1) filling a hole in the conductive film inner surface of the via hole with a resin mixed with an electrically insulating ceramic filler having high thermal conductivity; and an electronic circuit board having the via hole filled with the resin. (2) laminating and integrating a first resin layer mixed with a high thermal conductive and electrically insulating ceramic filler in a B-stage state on the first resin layer; The resin film side of a laminate of a metal foil and a B-staged resin film having a structure in which a second resin layer mixed with a high thermal conductive and electrically insulating ceramic filler is laminated and integrated on one surface of the metal foil, Laminate, crimp and heat the first tree A step of bonding and curing the layer and the second resin layer (3); a step of etching the metal foil to form a second wiring circuit (4); the first wiring circuit and the second wiring A step (5) of drilling a communication hole between the circuits, and a step of forming a conductive layer on the inner surface of the drilled communication hole by plating to electrically connect the second wiring circuit and the first wiring circuit ( 6) A method of manufacturing a multilayer electronic circuit board, wherein the steps (1) to (6) are sequentially repeated to multilayer the wiring circuit.
【請求項9】上記第1の樹脂層と第2の樹脂層を接着、
硬化させる方法が、第1の樹脂層と第2の樹脂層を一端
から順次連続的に圧着、加熱して接着硬化させる方法で
ある請求項8に記載の多層配線板の製造方法。
9. The method according to claim 9, wherein the first resin layer and the second resin layer are bonded.
9. The method for manufacturing a multilayer wiring board according to claim 8, wherein the method of curing is a method of successively pressing and heating the first resin layer and the second resin layer from one end, and heating and bonding the first resin layer and the second resin layer.
【請求項10】上記一端から順次連続的に圧着させる方
法が、ロール圧着である請求項9に記載の多層配線板の
製造方法。
10. The method for manufacturing a multilayer wiring board according to claim 9, wherein the method of sequentially and sequentially pressing from one end is roll pressing.
JP21383397A 1996-07-05 1997-07-03 Electronic circuit board and its manufacture Pending JPH10163594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21383397A JPH10163594A (en) 1996-07-05 1997-07-03 Electronic circuit board and its manufacture

Applications Claiming Priority (7)

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JP21040396 1996-07-05
JP23831496 1996-08-05
JP29701596 1996-10-03
JP8-210403 1996-10-03
JP8-238314 1996-10-03
JP8-297015 1996-10-03
JP21383397A JPH10163594A (en) 1996-07-05 1997-07-03 Electronic circuit board and its manufacture

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JPH10163594A true JPH10163594A (en) 1998-06-19

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134921A (en) * 2000-10-30 2002-05-10 Ibiden Co Ltd Multilayer printed wiring board and method for manufacturing the same
JP2004140267A (en) * 2002-10-18 2004-05-13 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
JP2008193001A (en) * 2007-02-07 2008-08-21 Furukawa Electric Co Ltd:The Metal core multilayer printed wiring board
CN105744740A (en) * 2014-12-29 2016-07-06 三星电机株式会社 Printed circuit board and method of manufacturing the same
CN112105139A (en) * 2020-08-28 2020-12-18 中科威禾科技(肇庆)有限公司 Processing method for improving asymmetric processing warping of laminated board and laminated board thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134921A (en) * 2000-10-30 2002-05-10 Ibiden Co Ltd Multilayer printed wiring board and method for manufacturing the same
JP2004140267A (en) * 2002-10-18 2004-05-13 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
US9093324B2 (en) 2002-10-18 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor apparatus and fabrication method of the same
JP2008193001A (en) * 2007-02-07 2008-08-21 Furukawa Electric Co Ltd:The Metal core multilayer printed wiring board
CN105744740A (en) * 2014-12-29 2016-07-06 三星电机株式会社 Printed circuit board and method of manufacturing the same
CN112105139A (en) * 2020-08-28 2020-12-18 中科威禾科技(肇庆)有限公司 Processing method for improving asymmetric processing warping of laminated board and laminated board thereof

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