JPH0349478A - Horizontal synchronizing signal reproducing circuit - Google Patents

Abstract

PURPOSE:To suppress horizontal fluctuation and bent at reproduction of a VTR and to suppress horizontal jitter at a weak electric field district at a TV signal reception by differentiating and detecting a composite video signal, sampling and holding the result so as to detect a noise level and controlling a loop gain or a filter characteristic of a horizontal AFC circuit based on the detected voltage. CONSTITUTION:The circuit is provided with a horizontal synchronizing separator circuit 12, a differentiating and detection circuit 13, a sample-and-hold circuit 14, a phase detection current control circuit 15, a phase detection circuit 16, a filter circuit 17 smoothing a phase detection voltage, a horizontal oscillation circuit 18, and a pulse shaping circuit 19. Then the inputted composite video signal is differentiated and full-wave-detected and the detected voltage is sampled and held for a period in a horizontal synchronizing signal period to detect a noise of input, a phase detection current of the phase detection circuit 16 is controlled in response to the detected voltage or the impedance of the filter circuit 17 is controlled. Thus, the loop gain of the horizontal AFC circuit 10 is controlled with an output voltage of the sample-and-hold circuit 14.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention provides a system for manually adjusting the loop gain of the horizontal AFC circuit based on the noise state of the horizontal synchronizing signal in the composite video signal 5j. The present invention relates to a horizontal synchronizing signal reproducing circuit equipped with means for controlling the signal to a value suitable for the signal.

(Prior art) Traditionally, television receivers (hereinafter referred to as TV receivers) separate synchronization signals from input composite video signals.
An image is faithfully displayed on the display screen by a bias signal synchronized with this synchronization signal.

The deflection circuit that generates the deflection signal compares the phase with the synchronization signal separated from the composite video signal, and uses a horizontal automatic frequency control circuit (hereinafter referred to as "horizontal automatic frequency control circuit") to generate a deflection signal synchronized with the synchronization signal. road).

In conventional horizontal AFC circuits, horizontal jitter occurs in weak electric field areas when receiving TV signals, and video table recorders (
There has been a problem in that horizontal lateral wobbling and bending occur during playback of recordings on a VTR (hereinafter referred to as a VTR).

The horizontal AFC circuit of a conventional TV receiver employs a PLL system as shown in FIG.

That is, a synchronization signal is separated and extracted from the composite video signal by a synchronization separation circuit 1, and this synchronization signal is input to a phase detection circuit 2.
The phase is compared with the horizontal oscillation signal of the horizontal oscillation circuit 3, and a comparison signal is output. A certain portion of the low frequency side signal of this comparison signal is taken out through the filter circuit 4, and this low frequency side signal component is applied to the horizontal oscillation circuit 3, which converts the horizontal oscillation signal of the horizontal oscillation circuit 3 into the same signal. make it clear

By the way, in the above-mentioned PLL type control TM system, the oscillation frequency changes according to the phase difference between the horizontal synchronization signal and the horizontal deflection output pulse. (that is, 1 radian) is expressed as a loop gain.

When using the a1;1 control system of this PLL system, the optimum values of the loop gain and the filter characteristics of the filter circuit 4 are determined by the jitter that occurs in the TV signal input mode.
The optimum amount for suppressing horizontal lateral wobbling and bending that occurs in the VTR signal input mode is completely different. For this reason, in most conventional TV receiver designs, circuit constants are set to suppress both of these two factors to some extent.

Furthermore, some TV receivers are designed to switch between a VTR signal input mode and a TV signal reception mode, and the characteristics can be changed using a service switch.

In other words, in areas where the S/N ratio of the TV signal is poor, such as areas with weak electric fields, the composite video signal No. 3 is disturbed by noise, and the horizontal synchronization signal that has been synchronized and separated is not as normal as shown in Figure 7 (a). As shown in the same figure (b), it becomes disordered. Therefore, P should follow the <fl phase of this synchronization signal.
When the LL lube is activated, the deflection frequency of the horizontal oscillation circuit also becomes unstable, resulting in horizontal jitter on the screen.

By the way, if the frequency of the horizontal synchronizing signal part of the video @ signal that is not transmitted as in the TV signal reception mode is accurate and stable (not tuned by FMI etc.), A
Once the FC loop is locked, the loop gain of the PLL loop is not required as much, and it is preferable to keep the loop gain low in order to keep the reproduction of the horizontal synchronization signal from being disturbed by disturbance noise. .

On the other hand, in the video signal in VTR signal input mode,
Since the video signal is FM-modulated due to the expansion and contraction of the tape peculiar to VTRs, the horizontal synchronization in this FM-modulated video signal is different from the normal horizontal synchronization signal shown in Figure 8(a). The signals are shifted in time position as shown in FIG. 2(b). For this reason, if the loop gain of the PL loop is low, it becomes difficult to accurately synchronize and reproduce this FM-modulated video signal, causing horizontal shaking or bending of the screen. In other words, it is desirable that the loop gain of the horizontal AFC circuit be high in the VTR transmission Y three-person mode.

In this way, in the VTR signal input mode, there is a certain amount of (
On the other hand, in a TV signal receiving mode in an area with poor radio wave conditions such as a weak electric field area, a low loop gain is required.

(Problems to be Solved by the Invention) As described above, in the conventional method of switching the horizontal AFC loop gain and filter characteristics between the VTR signal input mode and the TV signal reception mode, video manual input is required only during VTR video playback. There is no problem if the loop gain is set high, but if you use the tuner on the VTR side to
When receiving a signal, synchronized reproduction must be performed with a high loop gain, which is not preferable.

Additionally, for filters that use a service switch to change the filter characteristics, general users can
It is troublesome and inconvenient to switch the switch every time you want to change the TR.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a horizontal synchronizing signal reproducing circuit that can automatically set the loop gain or filter characteristics suitable for VTR input and TV reception to eliminate the above-mentioned drawbacks.

[Structure of the Invention] <Means for Solving the Problems] The first invention related to this horizontal synchronization signal reproducing circuit comprises: an input terminal into which a composite video signal is input; and a composite video signal supplied to the input terminal. A horizontal synchronization separation circuit that separates a horizontal synchronization signal, a horizontal oscillation circuit whose oscillation frequency can be controlled, and a phase comparison between the horizontal timing signal separated by the horizontal synchronization separation circuit and the oscillation signal of the horizontal oscillation circuit, and It consists of a phase detection circuit that outputs a comparison signal according to the phase difference, and a filter circuit that converts the comparison signal from this phase detection circuit into a DC component and applies it as a control signal to the horizontal oscillation circuit. a horizontal AFC circuit that controls the oscillation signal to be synchronized with the horizontal synchronization signal; a differentiation/detection circuit that differentiates the composite video signal from the input terminal and performs double-wave detection; and a detection voltage from the differentiation/detection means. a sample-and-hold circuit that samples and holds the voltage within the period of the horizontal synchronization signal to obtain a detected voltage corresponding to the noise state; The apparatus includes: pulse generating means for generating a reference pulse for performing sample and hold; and control means for controlling the loop gain of the horizontal AFC circuit in accordance with the detected voltage from the sample and hold circuit.

Further, a second invention provides the lbll in the first invention.
The control means is configured such that a current control transistor is connected in series with a resistor through which a phase detection current of the phase detection circuit flows, and the current flowing through the transistor is controlled in accordance with the detection voltage from the sample bold circuit. It is characterized by the fact that

Furthermore, in a third invention, the control means in the first invention is configured such that an impedance control transistor is connected to the filter circuit, and the impedance of the transistor is controlled in accordance with the detected voltage from the sample and hold circuit. The feature is that it is structured like this.

Furthermore, in a fourth invention, in the first to third inventions, a switch means is provided at the output part of the sample and hold circuit, and a pulse period during which the horizontal oscillation signal is in the same phase as the horizontal synchronization signal in the horizontal AFC circuit is provided. The switch means is turned on only when the output voltage of the sample and hold circuit is supplied to the control means, and during the period when the horizontal oscillation signal does not have the same phase as the horizontal synchronization signal, the switch means is turned off and at the same time the output voltage of the sample and hold circuit is supplied to the control means. The present invention is characterized in that a direct current voltage of 1 is supplied to the control means.

(Function) In the present invention, the input composite video signal is differentiated and double-wave detected, and the detected voltage is sampled and held during one period within the horizontal synchronization signal period, thereby detecting the noise state of the input. Depending on this detected voltage, the phase detection current of the phase detection circuit in the horizontal AFC circuit is controlled, or the impedance of the filter circuit in the horizontal AFC circuit is controlled.This allows the output voltage of the sample and hold circuit to correspond to the noise state. It is possible to control the loop gain of the horizontal 8 f-C circuit.

When a TV signal is received in a state where the S/N ratio of the composite video signal is poor, such as in a weak electric field area, the detection voltage of the sample bold circuit becomes high, and at this time, the control means controls the horizontal phase detection current or the impedance. Horizontal AF
The loop gain of the C circuit can be reduced. Further, when the S/N ratio is relatively good, such as when receiving a normal TV signal or inputting a reproduced signal from a VTR, the detection voltage of the sample bold circuit decreases, and at this time, the control means 1 detects the horizontal phase detection signal. By increasing the current or the impedance, the loop gain of the horizontal AFC circuit can be increased. Therefore, it is possible to suppress horizontal jitter in a weak electric field area when receiving a TV signal, and suppress horizontal lateral vibration during VTR playback.

Further, the loop gain control operation of the horizontal AFC circuit is performed only when horizontal synchronization of the horizontal AFC circuit is locked;
When it is not locked, the horizontal phase detection current or the impedance is adjusted to a predetermined value, thereby allowing the horizontal AFC circuit to perform the pull-in operation quickly.

(Example) The present invention will be described below based on the example shown in the drawings.

FIG. 1 is a block diagram showing a horizontal signal reproducing circuit according to an embodiment of the present invention.

This horizontal synchronization signal reproducing circuit 10 has a composite video signal of 3 cv.
The horizontal synchronizing signal pulse IIP is input from the input terminal 11 to which the signal is inputted, and the input composite video signal 3cv is divided IIllt1.
a horizontal synchronization separation circuit 12, and a differentiation/detection circuit 13 that differentiates the input composite video signal Scv and performs double-wave detection.
and a sample and hold circuit 14 that samples and holds the differentiated and detected signal voltage for one period of the horizontal synchronization signal period.
and a phase detection current control circuit 1 that controls the phase detection current of the phase detection circuit 16 according to the sampled and held voltage.
5, a phase detection circuit 16 that detects the phase of the horizontal synchronizing signal pulse port P, a horizontal period reference pulse obtained from the horizontal oscillation circuit 18 through the pulse shaping circuit 19, and a filter circuit that smoothes the phase detection voltage. 17, a horizontal oscillation circuit 18 whose oscillation frequency is controlled by a phase detection voltage, a reference pulse KP in the horizontal synchronization signal period supplied from the horizontal oscillation waveform to the sample hold circuit 14, and a reference pulse KP supplied to the phase detection circuit 16. The pulse shaping circuit 19 generates a reference pulse F having a horizontal period.

The composite video signal 3cv is applied to the base of the transistor Q1 via the capacitor C1. This base is connected via a resistor R1 to the positive terminal of a voltage source E1. Transistor Q1 constitutes a differential amplifier together with transistor Q2, and a resistor R is connected to each emitter of transistors Ql and Q2.
3. Connect R4, and connect the connection point of these resistors to a constant current source [
1 to the reference potential point, and the transistors Ql,
Each collector of Q2 is connected to the DC power supply Vcc via resistors R5 and R6. And transistor Q1,
Each collector of Q2 is connected to each base of transistors Q4 and Q3, the common emitter of transistors Q4 and Q3 is connected to a reference potential point via a constant current source 12, and each collector of transistors Q3 and Q4 is connected to a DC l! connected to source VCC.

The common emitter output of transistors Q3 and Q4 is supplied to the base of transistor Q5. Transistor Q5,
Q6 constitutes a common emitter circuit whose common emitter is connected to the reference potential point via the collector-emitter path of transistor Q7 and resistor R7. The collectors of the transistors Q5 and Q6 are connected to the collectors of transistors Q8 and Q9 forming a current mirror circuit, the bases of these transistors Q8 and Q9 are connected to each other, and the emitters of each transistor are connected to each other through resistors R8 and R9, respectively. It is connected to the DC power supply Vcc. The collector of the transistor Q8 is connected to the base. The collector of transistor Q9 is connected to the base of transistor Q10, and is also connected to DC power supply Vcc via sample and hold capacitor C2. Transistor Q10
The emitter of is connected to the base of transistor Q11, and the collectors of transistors Q10 and Q11 are connected to the DC power supply Vc.
The emitter of the transistor Q11 and the base of the transistor Q6 are connected to a reference potential point via a constant current l1iil3. The above transistor Q10,
Q11 forms a Darlington connection circuit.

The output of transistor Q11 is the output of transistor Q1.
2 base. A constant current source I4 is connected between the emitter of the transistor Q12 and the DC power supply Vcc, and the emitter of the transistor Q12 is connected to the emitter of the transistor Q13 via a resistor R10.
The collector of transistor Q14 is connected to the reference potential point via the collector-emitter path of transistor Q14 and resistor R11.

The collector and base of transistor Q14 are connected to each other. The collector of transistor Q13 is connected to a reference potential point, and its base is connected to the emitter of transistor Q23, while a constant current 8! It is connected to the base * lightning position via I5. The base of transistor Q23 is connected to DC power supply Vcc via resistor R15 and to a reference potential point via constant current source I6. The above transistor Q2
3.Resistance R15. Constant current sources 15 and 16 constitute a reference voltage circuit. The transistor Q14 and the transistor Q15 constitute a current mirror circuit, and the base of the transistor Q14 is connected to the base of the transistor Q15.

The horizontal synchronization signal pulse port P output from the horizontal synchronization separation circuit 12 is input to the phase detection circuit 16. The horizontal synchronizing signal pulse port P is connected to a transistor Q17 that operates as a differential pair.
The voltage is applied to the base of one transistor Q17 of Q18, and the bias voltage source E2 is applied to the base of the other transistor Q18. Above transistor Q
The emitters of 17 and 018 are connected to each other, the common emitter of which is connected to the collector-emitter path of the transistor Q15 via the resistor R12! It is connected to the S quasi-potential point. The collector of transistor Q18 is connected to DC power supply Vcc, and the collector of transistor Q17 is connected to each emitter of transistors Q19 and Q20 forming a differential pair.

A bias voltage source E is connected to the base of the transistor Q20.
3 is connected, and the resistor R14 is connected to the base of the transistor Q19.
A bias voltage source E4 is connected through the terminal. The collectors of transistors Q19 and Q2G are connected to the collectors of transistors Q21 and Q22 forming a current mirror circuit, the emitters of transistors Q21 and Q22 are connected to DC power supply Vcc, and the base and collector of transistor Q21 are connected to each other. ing. Further, the base of the transistor Q19 is connected to the reference potential point via the resistor R13 and the collector-emitter path of the transistor Q16, and the base of the transistor Q16 is connected to the pulse shape circuit 1.
A reference pulse FH having a horizontal period is applied from 9 onwards. Then, the phase detection output of the phase detection circuit 16 (transistor Q
20 and is applied to the oscillation frequency control terminal of the horizontal oscillation circuit 18 via the filter circuit 17.

The input and output terminals of the filter circuit 17 are connected to a reference potential point via a series circuit of a resistor R18 and a capacitor C3, and are also connected to a reference potential point via a capacitor C4.

FIG. 2 is a circuit diagram showing an embodiment of the pulse shaping circuit 19. In the circuit shown in this figure, the oscillation circuit 18 generates an oscillation signal with a frequency 32 times the horizontal scanning frequency fH, or
This oscillation signal is supplied via the inverter 21 to a binary output counter circuit formed by connecting five T-7 lip 7 lobes T1 to T5 in cascade (series) to generate a reference pulse FH for horizontal period phase detection. At the same time, the five T-
Output Q. of each flip-flop 11 to T5. U is connected to four inverters 22 to 25 (however, inverter 23.25
is an inverter with two output terminals, and generates a sample-and-hold reference pulse KP within the horizontal synchronizing signal period. That is, the oscillation signal of the 3 2 The signals at the output terminals Q of T4 and the output @enable signal of T5 are both applied to the inverter 22, and the signals at the output terminals TI and T5 and the signals at the output terminals O of T12 to T4 are both applied to the inverter 22.
4 and generates a reference pulse KP within the horizontal phase signal Ill from one output terminal of the inverter 23. In addition,
The pulse FH. generated by the horizontal oscillation circuit 18 and the pulse shaping circuit 19 The phase of KP is made to be the same as the horizontal synchronizing signal HP as shown in FIG. 3 when the PLL is locked. In addition, the reason why the sample and hold pulse KP is output within the horizontal synchronizing signal period is that, firstly, if the horizontal synchronizing signal period is always within the video period, the waveform differentiated according to the video content Since there is a difference in amplitude, it is not possible to determine whether it is noise or not.Secondly, if it is not within the horizontal synchronizing signal period but during the entire horizontal blanking signal period, a burst signal may have been inserted. Also, since it detects even the rising and falling components of the horizontal synchronizing signal, it becomes difficult to distinguish it from noise.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIGS. 3 and 4. Figure 3 shows the differential/detection circuit 13, sample hold circuit 14, and phase detection current control circuit 15 in Figure 1.
FIG. 4 is a signal waveform diagram at each part in the differential/detection circuit 13 of FIG. 1.

The composite video signal 3cv (see FIG. 4(a) or FIG. 3(a)) inputted to the input terminal 11 is differentiated by a differentiating circuit including a capacitor C1 and a resistor R1, and is then differentiated as shown in FIG. 4(b). and is supplied to the base of transistor Q1.

Next, it is amplified by the differential amplifier composed of transistors Q1 and Q2, and the base waveform of transistor Q3 has the same phase as the base waveform of transistor Q1, and the base of transistor Q4 has a waveform as shown in Fig. 3 (C). The waveform of the inverted component is output as follows.

When this is double-wave detected by the common emitter circuit of transistors Q3 and Q4, a waveform as shown in FIG. 4 (d><< or FIG. 3 (C)) is obtained at the base of transistor Q5.

Next, the base waveform of Q5 is sample-and-hold circuit 1.
4, one period within the horizontal synchronization signal period (Fig. 3(e)
(period of the pulse KP shown in ), and the voltage is held in the capacitor C2. That is, during the period of pulse KP, the base of transistor Q7 is at a high level,
Current is supplied to the common emitters of transistors Q5 and Q6.

At this time, if the base voltage of transistor Q5 is higher than the output voltage of the sample and hold circuit (that is, the base voltage of transistor Q6), the collector current of Q5 increases,
The sample and hold capacitor C2 is charged through a current mirror circuit of transistors Q8 and Q9. Similarly, if the base voltage of Q5 is lower, then Q6
The collector current of C2 increases and capacitor C2 is discharged.

With such an operation, smoothing is performed during the pulse KP.

On the other hand, since the base voltage of transistor Q7 is at a low level outside the period of pulse KP, transistor Q5
, Q6 are not supplied with current and are in a cut-off state, and the voltage stored in capacitor C2 is supplied to the next stage circuit through Darlington transistors Q10 and Q11.

Therefore, when there is a lot of noise in the composite video signal, such as when receiving a TV signal in a weak electric field area, the base waveform of transistor Q5 becomes a waveform as shown in FIG. The base voltage of Q12) also increases as shown in the dotted line at 0 in Figure 3.
The solid line indicates the base voltage level during normal TV signal reception.

The output voltage (Q12 base voltage) of the sample and hold circuit 14 is supplied to the phase detection current control circuit 15. The sample-and-hold output voltage provided to transistor Q12 is compared to a reference voltage (013 base voltage), and if the base voltage of Q12 is higher, the collector current of Q12 decreases. The collector current of transistor Q12 is Q14,
It becomes a horizontal phase detection current (current of transistor Q15) via the current mirror circuit of Q15.

Therefore, when the S/N ratio of the composite video signal is poor, such as in a weak electric field area, the base voltage of Q12 becomes high.
The horizontal phase detection current decreases and the PLL loop gain decreases. Therefore, horizontal jitter that occurs in a weak electric field can be suppressed.

On the other hand, when receiving normal TV signals or inputting VTR signals,
The base voltage of Q12 is low, and the phase detection current of the phase detection circuit 16 is thick<PLL loop gain is maintained large. Therefore, even if the position of the horizontal synchronizing signal pulse HP changes, the horizontal oscillation circuit 18 is controlled to quickly match the phase of the pulse port P, and horizontal lateral wobbling, bending, etc. can be suppressed.

FIG. 5 shows a horizontal synchronizing signal reproducing circuit 3 according to another embodiment of the present invention.
1 is shown.

This horizontal synchronizing signal reproducing circuit 31 has a structure in which the phase detection current of the phase detection circuit 16 is controlled based on the output voltage of the sample bold circuit 14, and instead of controlling the phase detection current of the phase detection circuit 16,
The filter characteristics of the filter circuit 17A are controlled based on the output voltage of the filter circuit 17A.

This filter circuit 17A includes a field effect transistor (
FET) Q24's source is connected to the input/output terminal of the filter circuit, and its drain is connected to resistor R18 via resistor R19.
and the connection point between the capacitor C3 and the capacitor C3. Therefore, the output voltage of the sample bold circuit 14 is
4, and the effective impedance between the source and drain is varied by the applied voltage.

That is, as the output voltage of the sample and hold circuit 14 becomes higher, the effective impedance connected in parallel with the resistor R18 becomes smaller, and therefore the loop gain of the horizontal AFC becomes smaller.

The structure of each other circuit portion is almost the same as that shown in FIG. However, in this embodiment, since the phase detection current control circuit 15 is deleted, the phase detection circuit 16 does not use the transistor Q15 connected in series with the resistor R12 in FIG. 1, but instead uses the common emitter of the transistors Q17 and Q18. A resistor connected to a reference potential point via a resistor R12 is used.

In the above embodiment, even when the horizontal oscillation signal of the horizontal oscillation circuit is not synchronized with the synchronization signal (that is, the PLL loop is not locked), the horizontal phase detection current is adjusted depending on the noise state of the input composite video signal. Alternatively, the filter impedance III control operation will be performed, but this may slow down the horizontal synchronization pull-in, so the above II control operation will be performed.
It is also possible to perform the IIltlll operation only when the horizontal synchronization is locked, and to provide a constant horizontal phase detection current or a constant filter impedance when the horizontal synchronization is not locked, thereby speeding up the pull-in of the horizontal synchronization. For example, a switch means for turning on and off the output voltage of the sample and hold circuit 14 is provided, and the switch means is turned on only during a pulse period in which the horizontal oscillation signal is in the same phase as the horizontal dome signal, and the sample and hold circuit 14 is turned on. 14 to the phase detection current control circuit 15.
Alternatively, the filter circuit 17A is supplied with a predetermined DC voltage (for example, a power supply voltage) to the phase detection current friil while the switch means is turned off during a period in which the horizontal oscillation signal is not phase-synchronized with the horizontal synchronization signal.
The signal may be supplied to the control circuit 15 or the filter circuit 17A.

Incidentally, the configuration may be such that FIG. 1 and FIG. 5 are combined. That is, the output voltage of the sample and hold circuit 14 may be used to variably control the phase detection current of the phase detection circuit 16 and the filter characteristics of the filter circuit 17.

[Effects of the Invention] As described above, according to the present invention, the input composite video signal is differentiated. The noise level of the composite video signal is detected by sampling and holding the detected voltage for one period within the horizontal synchronization signal period, and the loop gain or filter characteristics of the horizontal AFC circuit is controlled based on this detected voltage. As a result, it is possible to perform horizontal AFC with circuit characteristics that match the noise state of the input composite video signal, suppress horizontal jitter in weak electric field areas when receiving TV signals, and improve horizontal AFC during VTR playback. Sideways shaking, bending, etc. can be suppressed.

[Brief explanation of drawings]

FIG. 1 shows a horizontal synchronizing signal reproducing circuit according to an embodiment of the present invention; FIG. 2 shows an embodiment of the pulse shaping circuit of FIG. 1; FIGS. The figure is a waveform diagram explaining the circuit operation of Fig. 1, Fig. 5 is a block diagram showing another embodiment of the present invention, Fig. 6 is a block diagram showing a conventional horizontal AFC circuit, and Fig. 7 is a normal FIG. 8 is a waveform diagram showing separated horizontal synchronizing signals at normal electric field strength and weak electric field strength. FIG. 10...Horizontal synchronization signal regeneration circuit, 11...Input terminal, 12...Horizontal synchronization separation circuit, 1
3... Differentiation/detection circuit, 14... Sample hold circuit, 15... Phase detection current control circuit, 16... Phase detection circuit, 17.17A... Filter circuit, 18... Horizontal oscillation Circuit, 19...Pulse shaping circuit.

Claims (4)

[Claims] (1) An input terminal into which a composite video signal is input, a horizontal synchronization separation circuit that separates a horizontal periodic signal from the composite video signal supplied to this input terminal, a horizontal oscillation circuit whose oscillation frequency can be controlled, and the horizontal A phase detection circuit that compares the phases of the horizontal synchronization signal separated by the synchronization separation circuit and the oscillation signal of the horizontal oscillation circuit and outputs a comparison signal according to the phase difference, and converts the comparison signal from this phase detection circuit into a DC component. a horizontal AFC circuit that controls the oscillation signal of the horizontal oscillation circuit to be synchronized with the horizontal synchronization signal; and a composite video signal from the input terminal. A differentiation/detection circuit that differentiates a signal and performs double-wave detection; and a sample/hold circuit that samples and holds the detected voltage from this differentiation/detection means within the period of the horizontal periodic signal to obtain a detected voltage corresponding to the noise condition. and pulse generating means for generating a reference pulse for sample-holding in the horizontal periodic signal period in the sample-hold circuit based on the oscillation signal from the horizontal oscillation means; A horizontal synchronizing signal reproducing circuit comprising: control means for controlling a loop gain of the horizontal AFC circuit. (2) The control means connects a current control transistor in series with a resistor through which a phase detection current of the phase detection circuit flows, and controls the current flowing through the transistor in accordance with the detection voltage from the sample and hold circuit. 2. The horizontal synchronizing signal reproducing circuit according to claim 1, wherein the horizontal synchronizing signal reproducing circuit is configured as follows. (3) The control means is characterized in that an impedance control transistor is connected to the filter circuit, and the impedance of the transistor is controlled in accordance with the detected voltage from the sample and hold circuit. horizontal sync signal regeneration circuit. (4) A switch means is provided at the output part of the sample and hold circuit, and the switch means is turned on only during a pulse period in which the horizontal oscillation signal has the same phase as the horizontal synchronization signal in the horizontal AFC circuit, and the sample and hold circuit is turned on. An output voltage of the circuit is supplied to the control means, and a predetermined DC voltage is supplied to the control means at the same time as the switch means is turned off during a period in which the horizontal oscillation signal is not phase-synchronized with the horizontal synchronization signal. Claim 1 characterized by
, 2 or 3. The horizontal synchronizing signal reproducing circuit according to .