JPH03163911A - inverter circuit - Google Patents

Abstract

PURPOSE:To realize the low energy consumption and low power supply voltage in an inverter by composing the inverter of an n-type MIS transistor or a p-type MIS transistor, forming the inverter by multicrystal silicone and using the inverter for a built-in peripheral circuit. CONSTITUTION:When a transistor Q6 is in an ON state and a transistor Q5 is in an OFF state, a drain potential of the Q6, namely, 20V is outputted to a Vout as it is. Since an electric charge accumulated at the gate of the Q6 has no discharging place (Q2 and Q4 are in the OFF state) even when the potential of the Vout is increased, this drain potential is remained on the gate of the Q6. Namely, even when the potential of the Vout is increased, the voltage between the gate and source of the Q6 is not transiently reduced (strictly, the electric charge on the gate of the Q6 is discharged by a product between the capacity between the gate and source of the Q6 and OFF resistance Roff of the Q2 and Q4). Thus, the waveheight value 20V of phi4 is outputted to the Vout. Thus, it can be known that the energy consumption and power supply voltage of this inverter can be reduced.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is directed to enhancement membrane 1.
S (Metal Insulator Semico
(inductor) relates to the circuit configuration of an inverter in a transistor circuit.

[Conventional technology]

Conventional enhancement type p-type or n-type MI
S (Metal Insulator Semico
An inverter using transistors is described in, for example, Japanese Patent Application Laid-Open No. 1-4-3 62019. That is, the @ path configuration shown in FIG. 2 is used.

[Problem to be solved by the invention]

However, the inverter shown in FIG. 2 had the following problems.

1) On voltage on V+n (digitally “L” voltage)
A direct current flows between Vooz and GND during the period when is applied. That is, the inverter shown in FIG. 2 consumes a large amount of power.

2) If the threshold voltage of the transistor is VT, then v
During the period when the off voltage (digitally 110" voltage) is applied to I, , V o u i is Vl]DI-2
It is VT. This means that when the off-voltage is applied to V1n, the output voltage of the inverter between VonI and GND is VDDI-VT, and Vont-V'r is VDD2-VT.
Since it is applied to the gate of the upper transistor of the inverter between GND, V Out becomes VDDI2VT. That is, the power supply voltage of the inverter shown in FIG. 2 is higher than that of a CMOS inverter.

An object of the present invention is to realize lower power consumption and lower power supply voltage of an inverter.

[Means to solve the problem]

The purpose of the above is to input an input signal V t n to the drain of Q1 (transistor C (hereinafter referred to as Tr)), and input a clock signal to the gate of Q1. A pulse (hereinafter abbreviated as CP) φ1 is input, the gate of Tr Q 2 and the gate of Tr Q 5 are connected to the source of Q1, the sources of Q2 and Q5 are grounded, and the drain of Q2 is connected to the source of TrQs. CPφ3 is applied to the gate of Q3, and T r Q 4 is applied to the drain of Q3.
The source of TrQo is connected to the gate of TrQo, CPφ2 is applied to the gate and drain of Q4, CPφ4 is applied to the drain of Qe, the source of Qe is connected to the drain of Q5, and the output signal Voui is connected to the gate of Q5. This can be achieved by creating a circuit configuration in which the output is taken out from the drain.

[Effect]

In the inverter with the above circuit configuration, when applying the input signal Vin to Q2 and Q5 via Q1, if φ3 or φ2 is set to oV and φ4 is set to o■, Vin becomes the on-voltage (digital (voltage of II I I+) but φ2
-GND and between φ4 and GND, no direct current flows. That is, the power consumption of the inverter is reduced.

Also, VIn is the off voltage (digitally II O I+
Q2. After Qs and Q4 are completely turned off, when φ4 is turned on, the peak value of φ4 is output as is to V O I1 + . This is Vo
Even if the potential of u t rises by -L, the charge accumulated in the gate of Q6 has no place to discharge (when Q2 and Q4 are in the off state: a) Case of Q6 - Jr. remains in That is, V o
Even if the potential of
gate. The charge at the gate of Q6 is discharged by the product of the source-to-source capacitance CCS and the off-resistance Ro of Q2 and Q4. Therefore, V transiently. 11, the peak value of φ1 is output as is. That is, the power supply voltage of the inverter can be lowered.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The royal diagram shows the circuit configuration and timing chart 1- of the inverter of the present invention. As for the circuit configuration,
The input signal V t n is input to the drain of transistor (hereinafter abbreviated as Tr) Q, the clock pulse (hereinafter abbreviated as CI) φ1 is input to gate 1 of Q1, and
The source of I has the gate of T r Q 2 and the gate of T r Q
The gates of Q2 and Q5 are connected, the sources of Q2 and Q5 are grounded,
The drain of Qz is connected to the source of ]". r Q 3, cpφ3 is applied to the gate of Q3, the source of TrQ4 and the gate of Tr Q e are connected to the drain of Q3, and the gate of Q4 is and drain, cPφ2 is applied, CPφ4 is applied to the drain of Q6, the source of Q6 is connected to the drain of Q5, and the output signal V o u c
is the circuit configuration taken out from the drain of Q5. Next, the circuit operation will be explained based on the timing chart of φ1, φ2, φ3, and φ4 shown in FIG. Here, φ1. φ2,
ON voltage of φ3, φ4+VIn (digitally “1”
voltage) is 20V, and the off voltage of φI, φ2, φ3, φ4, Vln (digital voltage of II O T') is 0V.
V, and the threshold voltage Vr of the transistor is 5V. For example, when V+n=20V, at the timing of φ+=20V, the gate of 02, Q5]. 5 V is applied and φ
i=OV and 02, Q5 case I. 5V is maintained. Therefore, Q2+Q5 is turned on. but,
At that time, since φ3 and φ4OV, no direct current flows between φ2 and GND and between φ4 and GND. Then φ
2=20V, 15V is applied to the gate of Q6, and φ2-
At Ov, i5V is held at the gate of Q6. At this time,
Q e becomes on state, but φ3 and φ4 are ov, so φ2
No direct current flows between GND and φa GND.

Next, since 03 is turned on at φa''20V, the charge accumulated in the gate F of Q6 is discharged via Q3.Q2. That is, the potential of the gate of Q6 becomes O■. At this time, both Q2 and Q4 are OV, so φ2 − G
No direct current flows between ND and φ4 and GND. Next, set φ3=OV, turn Q3 off, and set φ4=20V. At this time, Qs and Qs are in the off state, so between φxGND, φ4. There is no direct current flowing between GND. Also, since Q6 is in the off state and Q5 is in the on state, the source potential of Q5, that is, OV, is V o u
It is output at t. Therefore, when V I n is 20V, V
Out is OV, that is, it is operating as an inverter. Next, for example, when Vin=O■, OV is applied to the gate of Q2+QB at a timing of φ120V, and Ov is held at the gates of Q2 and Q5 when φl=OV. Therefore, Q2 and Q5 are turned off. Next φ2
=20V to the gate of Q6]. 5V is applied, φ2
=o■ for game 11 of Q6]. 5 V is maintained. At this time, Q6 is turned on, but since φ8 and φ4 are Ov, no DC current flows between φz GND and between φ4 and GND. Next, Q3 turns on at φ320V.
Since Q2 remains off, the charges on Qc are not discharged. That is, the potential of the gate of Q6 is ]. 5
The state of V is maintained. At this time, φ2 and φ4 are both o
Between φ2 and GND, φ4. - DC ff between GND
The current doesn't flow. Next, set φa to OV, turn off Q8, and set φ4 to 20V. At this time, since Qg and Q+ are in the off state, no direct current flows between φ2 and GND and between φa and GND. Also, at this time, Q8 is in the on state and Q5 is in the off state, so the drain potential of Q6, that is, 20V, is directly output to V out. This is because even if the potential of Vouc rises, the charge accumulated on the gate of Qs remains on the gate of QB because there is no place to discharge it (because Q2 and Q4 are in the off state). In other words, even if the potential of V out rises, the voltage Vas between the gate and source of Q6 does not decrease transiently (strictly speaking, the capacitance between the gate and source of QB fj
kcas and off resistance R. of Q2 and Q4. ．． , is the product of Q6
The charge on the gate 1 is discharged). Therefore, V o
The peak value of 20V of φ4 is output as is to ut.

From the following, it can be seen that the inverter of the present invention has low power consumption and can reduce the power supply voltage.

FIG. 3 shows the circuit configuration and timing chart of the inverter of the present invention. The circuit configuration is T
The input signal vI11? is input to the drain of rQ1? Enter, Ql
CP■10 is input to the gate of Q1, and T is input to the source of Q1.
rQ! and T r Q 5 gates are connected, and Q
The sources of Q2 and Q5 are grounded, and the drain of Q2 is connected to T r
Connected to the source of Qs, and connected to the gate of Q8 with CPφt
o is applied, the source of TrQ4 and the gate of TrQe are connected to the drain of Q3, CPφ process 0 is applied to the gate and drain of Q4, and CPφ is applied to the drain of Q6.
(1) Apply 10, connect the source of QB to the drain of QI, and output signal V. ut is a circuit configuration taken out from the drain of Q5. Next, φ10, ■10 shown in Figure 3
The circuit operation will be explained based on the timing chart. Here, the on-voltage of φto, $10, V 1n is set to 20V,
The off-state voltages of φ10, rfi10, and Van are assumed to be O■, and the threshold voltage VT of the transistors is assumed to be 5■. for example,
When Vtn=20V, φ■0=20V, $to=
Q2 at the timing of OV. 1 for QJ and QB gates
5V is applied, Qt+ Q21Q11, Qe and Q4
turns on. At this time, Q3 is in the off state because φzo=OV. Therefore, no direct current flows between the drain of Q4 and the source of Q2, and between the -11 drain of Q6 and the source of Q5. Next, Ql. Q4 is turned off and Q3 is turned on.

At this time, since Q2 is also in the on state, the charge on the gate of Q6 is instantaneously discharged via Qa and Qx. Therefore, the potential of the gate of Q6 becomes OV, and QB is turned off. Therefore, no direct current flows between the drain of Q4 and the source of Q2, and between the drain of Qs and the source of Q5. or,
At this time, Q6 is in the off state and Q5 is in the on state, so the source potential of Q5, ie, Ov, is output to V out . Therefore, when vin=20■, V out is OV, that is, the inverter is operating. Next, for example, V1
When n = OV, QI at the timing of 10 = 20v, φto = OV, OV to the gate of Q5, 1 to the gate of Q6
5V is applied, Qt, Qa. ．． Qe is on state, Q2
．． Q5 is turned off. At this time, since 10=OV, Q3 is in the off state. Then φ+o=OV, φ10=2
Qt. at 0V timing. Q4 is turned off and Q3 is turned on. At this time, Q2 and Q512- are off, so between the drain of Q4 and the source of Q2,
And no direct current flows between the drain of Q6 and the source of Q5. Also, at this time, since QB is in the on state and Q5 is in the off state, the drain voltage of 20V of Q6 is output as is. This is because even if the potential of V out rises, the voltage Vas between the gate and source of Q6 does not decrease transiently.

Therefore, the peak value of φ number 20V is transiently outputted to V out. From the above, it can be seen that the inverter of the present invention has low power consumption and can reduce the power supply voltage.

FIG. 4 is a circuit configuration and timing chart in which two inverters of the present invention are used to form one stage of shift register. As for the circuit configuration, the input signal V + n of the shift register is input to the drain of T r Q 1, and the input signal V + n of the shift register is input to the drain of T r
CP■10 is input to the gate of , and T is input to the source of Qs.
r Connect the gate of Q2 and the gate of TrQ5, and
The sources of Q2 and QB are grounded, and the sources of Q2. The drain of is Tr
Connect to the Qa source. CPφto is applied to the gate of Qa, the source of Tr Q 4 and the gate of TrQe are connected to the drain of Q8, CP■10 is applied to the gate and drain of Q4, and CP■ is applied to the drain of Q6. 1
0 is applied to the drain of Q5, and the source of Q6 and T
r Connect the drain of Q7, and connect CP to the gate of Q7.
20 is applied, the gate of TrQδ and the gate of TrQ+t are connected to the source of Q7, the sources of Q8 and Qli are grounded, the 1 line of Q8 is connected to the source of Q9,
CP■20 is applied to the gate of Q9, the source of TrQ+o and the gate of TrQ12 are connected to the drain of Q9, CP■20 is applied to the gate and drain of Q+o, and the drain of Q12 is applied. Apply CP■20, Q
+. The source of Q+2 is connected to the drain of +, and the shift I
- The circuit configuration is such that the register output signal V g 11 t is taken out from the drain of Qtt. Next, φio, φ10, φ20. shown in FIG. (2) The circuit operation will be explained based on the timing chart of 20. Here, ■10,φio,
φ20, φ20・V In on voltage is 20■, φ1.

,φ1. , φ20, ■20, the off-voltage of V+n is Ov,
The threshold voltage VT of the transistor is assumed to be 5V. For example, when v,n=20V, φ1. O=20V. φto=O
15 on the gates of Q2, Q5 and QB at the timing of V.
■ is applied, Ql, Q2, QB. QB and Q4 are turned on. At this time, since φio=OV, Q3 is in the off state. Therefore, no direct current flows between the drain of Q4 and the source of Q2, and between the drain of Q6 and the source of Q5. Next, at the timing of φlo=OV, ■10=2 0 V, Ql and Q4 are turned off, and Q3 is turned on. At this time, since Q2 is also in the on state, the charge on the gate of Q6 is Q3. It is instantly discharged via Q2. Therefore, the potential on the gate of Q6 becomes Ov, and Q8 turns off.

Therefore, between the drain of Q4 and the source of Q2, and Q6
No direct current flows between the drain of Q5 and the source of Q5.

Also, at this time, Q6 is off and Q5 is on, so Q5
The source potential of Q7, ie Ov, is applied to the drain of Q7. Next, at the timing of φ20=20V and φ20=OV, Q
The gates of ++ and Qt+ have OV. Q12 (7) Gate ni is applied with King 5v, Q? IQ io + Q 1
．． 2 is in the on state, and Qs+Q11 is in the off state.

At this time, since φ20=OV, QO is in the off state 15. Next, at the timing of φ20=OV and φ20=20V, Q7 and QIO are turned off and Q9 is turned on. At this time, since Q8+Q11 are in the off state, no direct current flows between the drain of Qio and the source of Q8, and between the drain of Q12 and the source of Qiz. Also, at this time, since Q12 is on and Q11 is off, the drain voltage of 20V of Q14 is output as is. This is because even if the potential of the output signal V'out of the shift register rises, the charge accumulated at the gate of Q12 has no place to discharge (because QIO and Qδ are in the off state). It remains on the gate of Q12. In other words, even if the potential of V:ut rises to -H, the voltage Vas between the gate and source of Q12 does not become small transiently. . o i
The charge on the gate of Q12 is discharged by the product of f). Therefore, the peak value 20V of ■20 is transiently outputted as the output signal V'au t of the shift register. From the above, it can be seen that the shift 1 register of the present invention has low power consumption and can be made low in power supply voltage.

]b FIG. 5 is a modification of the circuit shown in FIG. 4. That is, the circuit configuration and timing are the same as the circuit shown in FIG. 4 except that CPφ30 is applied to the drain of Q12.

In the shift register circuit shown in Fig. 5, V out is Ov.
When outputting Q, wait until Q12 is completely off.
20V is applied to the drain of 12. Therefore, V:
ut is always maintained at ○V. That is, the shift register shown in FIG. 5 stabilizes the output.

FIG. 6 is a configuration diagram when the shift register of the present invention shown in FIG. 4 or 5 is applied to a built-in scanning side drive circuit of an active matrix liquid display with a built-in peripheral circuit. In the figure, 1 is a glass substrate, 2 is a display section, and 3 is a glass substrate.
4 is a scanning side drive circuit, 4 is a signal side drive circuit, and 5 is an external circuit. Here, the transistors used in the display section 2, scanning side drive circuit 3, and signal side drive circuit 4 are polycrystalline silicon thin film transistors. By using the shift register of the present invention in the built-in scanning side drive circuit of a polycrystalline silicon active matrix liquid crystal display with a built-in peripheral circuit, the power consumption of the liquid crystal display can be reduced. Power supply voltage conversion is realized.

〔Effect of the invention〕

According to the present invention, an n-type M-type S transistor or a p-type M-type S transistor
Even an inverter composed of only transistors can be CMOS
Since it is possible to achieve a similar reduction in power consumption and power supply voltage, there is an effect of reducing the cost of the system.

[Brief explanation of the drawing]

1 and 3 are circuit configuration diagrams of an inverter according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a conventional inverter, and FIGS. 4 and 5 are circuit configuration diagrams of a shift 1 register of the present invention. Block diagram No. 6 is a block diagram of an active matrix liquid product display with a built-in peripheral circuit. DESCRIPTION OF SYMBOLS 1...Glass substrate, 2...Display section, 3...Scanning side drive circuit, 4...Signal side drive circuit, 5...External circuit, Q1-Q12...MIS transistor, ■. ... Inverter input signal, V out... Inverter output signal, ■? ■...Shift register input signal,
V out...output signal of shift register, φl
~φ4, ■10~φ10, φ20~φ20l φ30...Clock pulse. φ30 Funeral 5 Figure 6

Claims (1)

[Claims] 1. Enhancement type n formation is performed by p type MIS (Met
alInsulator Semiconductor)
In the circuit configuration of an inverter formed of transistors, an input signal V_i_n is input to the drain of a transistor (hereinafter abbreviated as Tr) Q_1, a clock pulse (hereinafter abbreviated as CP) φ_1 is input to the gate of Q_1, and
The gate of TrQ_2 and the gate of TrQ_5 are connected to the source of _1, and the sources of Q_2 and Q_5 are grounded.
The drain of _2 is connected to the source of TrQ_3, and Q_3
Apply CPφ_3 to the gate of Q_3, connect the source of TrQ_4 and the gate of TrQ_6 to the drain of Q_3,
Apply CPφ_2 to the gate and drain of Q_4,
CPφ_4 is applied to the drain of Q_6, the source of Q_6 is connected to the drain of Q_5, and the output signal V_o_
An inverter circuit characterized in that u_t is taken out from the drain of Q_5. 2. Enhancement type n-formation is an inverter driving method characterized by operating an inverter formed of p-type MIS transistors with one or more clock pulses. 3. In the inverter circuit configuration where the n formation is formed by p-type MIS transistors, V_i_n is input to the drain of TrQ_1, and CPφ_1_ is input to the gate of Q_1.
0, connect the gates of TrQ_2 and TrQ_5 to the source of Q_1, ground the sources of Q_2 and Q_5, connect the drain of Q_2 to the source of TrQ_3, and apply CPφ_1_0 to the gate of Q_3. ,
The drain of Q_3 is connected to the source of TrQ_4 and TrQ_6.
Connect the gate of Q_4, and connect C to the gate and drain of Q_4.
Pφ_1_0 is applied, and CP■_ is applied to the drain of Q_6.
1_0 is applied, the source of Q_6 is connected to the drain of Q_5, and V_o_u_t is taken out from the drain of Q_5. 4. One stage of shift register is formed using two inverters as described in claim 3. That is, input signal V^s_i_n of the shift register is input to the drain of TrQ_1, and CPφ_1_0 is input to the gate of Q_1. Enter and Q
The gate of TrQ_2 and the gate of TrQ_5 are connected to the source of _1, and the sources of Q_2 and Q_5 are grounded.
The drain of _2 is connected to the source of TrQ_3, and Q_3
CP■_1_0 is applied to the gate of Q_3, the source of TrQ_4 and the gate of TrQ_6 are connected to the drain of Q_3, CPφ_1_0 is applied to the gate and drain of Q_4, and CP■_1_0 is applied to the drain of Q_6. , the drain of Q_5 is connected to the source of Q_6 and TrQ_7
CPφ_2_ is connected to the gate of Q_7.
0 is applied, and the gate of TrQ_8 and the gate of TrQ_1_1 are connected to the source of Q_7, and Q_8 and Q_1_1 are connected.
The source of Q_8 is connected to the source of Q_9, CP_2_0 is applied to the gate of Q_9, and the drain of Q_9 is connected to the source of TrQ_1_0 and Tr
Connect the gate of Q_1_2, apply CPφ_2_0 to the gate and drain of Q_1_0, apply CP_2_0 or φ_3_0 to the drain of Q_1_2, and
Connect the source of Q_1_2 to the drain of _1_1,
The output signal V_o_u_t of the shift register is Q_1_1
A one-stage shift register circuit configuration characterized in that data is taken out from the drain of the shift register. 5. An inverter circuit, wherein the inverter according to any one of claims 1 to 5 is formed of polycrystalline silicon. 6. An active matrix liquid crystal display with a built-in peripheral circuit, characterized in that the inverter according to any one of claims 1 to 5 is used in the built-in peripheral circuit.