JPH0311665A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a semiconductor memory device.Special code: Static random access memory in which stored information is stably retained as long as power is supplied, and does not require rewriting of stored information at regular intervals. The present invention relates to a device (hereinafter sometimes abbreviated as SRAM).

Conventional technology Conventional SRAM uses a memory cell consisting of two inverters to stably hold information and at least one switch transistor for reading and writing. abbreviation)
For the configuration (5 MOSFETs, 2 polysilicon resistors and 3 MOSs for the polysilicon load resistor)
A memory cell is constituted by the FET. On the other hand, in DRAM, a memory cell is composed of one switch transistor and one capacitor, and because the memory cell area is small, it is integrated at a density approximately four times that of SRAM.

An attempt to improve the low integration density of SRAM JP-A-1983-
In Publication No. 84432, the inventor of the present invention disclosed an SRAM memory cell configuration of a ``1 transistor cell'' that stably stores stored information in the area of one MOSFET. It is named this way because the area it occupies is the same as one MOSFET.With this invention, a memory cell is configured with the same number of elements as an iDRAM, so it has the same degree of integration as a DRAM. An SRAM having the following is realized.

Problems to be Solved by the Invention However, in the above invention, no consideration was given to compatibility with peripheral circuits for driving memory cells and processing their information.The basic idea is extremely inventive. Although it is rich in energy, there are some flaws in its practicality.The operating principle is based on the generation of hot carriers in MOS FETs, and MOS
Invention 1, which had a reliability problem due to the inevitable deterioration of FET characteristics, was tried in view of the above problem, and was developed to improve the reliability of high-density SRAM and to improve the consistency with peripheral circuits. An object of the present invention is to provide a semiconductor memory device with improved performance.

Means for Solving the Problems The present invention is intended to solve the above problems.The present invention includes an island region of a second conductivity type reaching one main surface of a semiconductor substrate of a first conductivity type, and a gate insulating film provided on the surface of the island region. a first conductivity type source/drain separated by and provided at both ends of the gate; and a first conductivity type emitter located inside the island region and below the source; MOSFET by source, drain and gate
The emitter, island region, and source constitute a bipolar transistor, the drain is connected to a fixed positive power supply, the gate and source are connected to a bit line via a switch transistor, the emitter is connected to ground potential, and the island region is connected to an external source. It has a static memory cell configuration that is separate from the circuit.

Further, the semiconductor device includes a second conductivity type ion implantation layer provided inside the substrate and reaching from the source to the drain, and the highest concentration portion between the drain and the second conductivity type island region is located inside the substrate.

Effect of the present invention With the above-described configuration, the emitter of the first conductivity type exists in the island region of the second conductivity type separated from the surroundings, so that it is separated from the semiconductor substrate of the first conductivity type and is connected to the ground potential. The semiconductor substrate can be connected to a positive potential independently of this. In addition, even if the peripheral circuit has a CMO5 configuration and a bipolar configuration, the SRAM of the present invention
Can coexist with cells.

However, since the part with the highest impurity concentration between the source and drain in the SRAM cell is inside the semiconductor substrate and is away from the gate oxide film, the generated hot carriers are injected into the gate oxide film. The probability of causing characteristic deterioration of MOSFET is significantly reduced.

Embodiment An embodiment of the present invention will be explained with reference to FIGS. 1 to 5.

FIG. 1 is a cross-sectional structural diagram of an SRAM cell according to an embodiment of the present invention. In FIG. 1, it has a two-layer structure in which a p-type epitaxial layer 2 (hereinafter simply referred to as a shrimp layer) is grown on an n-type semiconductor substrate 1.

Before growing the shrimp layer 2, a p+ type buried layer 91 is formed inside the n type semiconductor substrate 1, and an n+ type buried layer 8 is formed inside the n type semiconductor substrate 1.
It is formed at a position closer to the surface of the type semiconductor substrate 1.

The n-type buried layer 8 becomes an emitter.

An isolation region 3 reaching the bottom of the p-type buried layer in the n-type semiconductor substrate 1 is formed by penetrating the p-type epitaxial layer to form a p-type island region 9 surrounded by the isolation region. This island region 9 has a conductivity type opposite to that of the substrate 1. A polysilicon gate 7 is provided on its surface via a gate oxide film 6, and an n-type source 4 and drain 5 are formed at both ends of the gate 7. Ru. An n+ type emitter 8 is placed below the source 4.

N-channel MO with source 4, drain 5, and gate 7
An SFET is configured, and an npn bipolar transistor is configured with an emitter 8, an island region 9, and a source 4 as an emitter, base, and collector, respectively.

The drain 5 is connected to the positive fixed power supply Vdd and the source 4.
The gate 7 is connected to the bit line via the switch transistor 11, and the emitter 8 is connected to the ground potential.

In this SRAM cell, the potential of the source (collector) 4 is "
Information is stored as ``High'' or ``Low.'' When the potential of source 4 is ``Low'' (close to ground potential) (
A voltage is applied between the source 4 and the drain 5, and a high electric field is generated near the drain 5. If electrons flow from the source 4 toward the drain 5 (Is), hot carriers are generated in the high electric field near the drain 5, and the holes increase the substrate current Ib.
and flows into the p-type island region. This current Ib becomes a base current, and electrons flow out from the emitter 8 (Ie
).

This emitter current ■e flows into the source 4, a part of which becomes the source current Is, and the current circulates continuously, so that the potential of the source 4 is maintained at the "Low" level.

On the other hand, when the potential of the source 4 is "I (high"), n
Since the potential difference between the source 4 and drain 5 of the MOSFET is small and the electric field strength near the drain 5 is low, no hot carriers are generated. In this case, the base current Ib to the &npn bipolar transistor does not occur, and the emitter current Ie from the emitter 8 also does not flow. In this way, the state in which no current flows continues, and the source 4 becomes "High""High.
The surface of the island region between the source 4 and the drain 5 has a low n-type impurity concentration, or contains an even thinner n-type impurity concentration, and the potential difference between the gate 7 and the source 4 is zero.耘 It is necessary for a minute current to flow. This is because it is necessary for the source current s to flow even though the gate 7 and source 4 are short-circuited. Furthermore, if source 4 is at IIi and ghl+, if it is pulled toward the L0w'' level due to a disturbance, and the source 4 and drain 5 are in a conductive state, current is supplied from drain 5 due to the drop in the level of source 4. This is because the effect of maintaining the original state occurs.

The purpose of providing a p+ type buried layer 91 under the p type island region 9 is to prevent electrons from the emitter 8 from flowing toward the substrate 1.

FIG. 2 is a cross-sectional structural diagram of an SRAM cell according to another embodiment of the present invention. The difference from FIG. 1 is that a p'' injection layer 10 reaching from the source 4 to the drain 5 is formed.
The + implantation layer 10 has a distribution in which the impurity concentration is low at the interface between the island region 9 and the gate oxide film 6, and the impurity concentration increases as the distance from the interface increases.

As a result, the high electric field near the drain 5 is generated not at its interface, but at the inner plate of the island region 9, that is, near the bottom of the drain 5. Therefore, electrons flowing from the source 5 cause ionization collisions and are separated from the gate oxide film. Hot carriers are generated at the ionization collision point 51 in the figure. In other words, with this structure, although hot carriers are generated, there is a low probability that they will be injected into the gate oxide film.
Characteristic deterioration is unlikely to occur.

Figure 3 shows nMOSFET13 and pMOSFET14.
Complementary MO8 configuration consisting of SR of FIG. 1 or 2
FIG. 3 is a cross-sectional view of an integrated structure with an AM cell 12. nMO5
The FET 13 is configured by forming an n+ source/drain 15 inside the p-type island region 92 consisting of the p-type epitaxial layer 2 separated by an isolation region, and the pMOSFET 16 is constructed by forming an n+ source/drain 15 inside the p-type epitaxial layer 2 separated by an isolation region. n-Well1 spread to
A p+ source/drain 16 is formed within the 7.

Here, n-type semiconductor substrate 1. The n-Well 17 is connected to a positive power supply (+Vdd), and the iQ p-type island region 92 is connected to a ground potential. The p+ type buried layer 91 functions to prevent latch-up of the complementary MO3 circuit. Here, the n+ source 3-45 and drain 15 are formed simultaneously with the source 4 and drain 5 of the SRAM cell 12 at the same concentration and the same junction depth.

FIG. 4 is a cross-sectional view of a structure in which the nMOSFET 13 and the vertical npn bipolar transistor 18 are integrated with the SRAM cell 12.

Regarding the nMOSFET 12 (as it is the same as that shown in FIG. 3, the explanation will be omitted.
l 117 Second p-type active base formed in a part of (n-type island region) n+ emitter 1g in the active base 20, p+ base 21 which is a contact to the active base 20, and n- which acts as a collector It consists of an n+ collector 22 which is a contact to the Well 17. n-W
ell 17 is separated from n-type substrate 1 by p + type buried layer 91 . In order to reduce collector resistance, an n-type buried layer 23 is formed in contact with the bottom of the n-We1117. This buried layer 231t is formed at the same time as the n+ emitter 8 of the sRAM cell 12 with the same concentration and the same junction depth.

Similarly, the emitter 19 and the n+ collector 22 are formed simultaneously with the source 4 and drain 5 of the SRAM cell and the source and drain 15 of the nMOSFET.

If you compare it with Figure 3, you will see that it is an SRAM that has a bipolar transistor integrated with a complementary MO3 circuit, an LBi-CMO3LSI in its peripheral circuit, or conversely, a part of it that has an LBi-CMO3LSI.
Bi-CMO with SRAM of transistor cell configuration
It is clear that 8LSI is constructed.

5(A) to 5(E) show a part of the manufacturing process for forming the structure shown in FIG. 3.

(A) A p-type impurity such as boron is introduced into one main surface of the n-type semiconductor substrate 1, and a p+-type buried layer 91 is formed at a deep position so as to have a peak inside the substrate.

(B) An n-type impurity such as arsenic is introduced into a portion of the p''-type buried layer where a memory cell is to be formed to form an n-type buried layer 8 near the surface.

(C) Grow p-type epitaxial layer 2.

(D) Isolation region 3 is formed by trench etching and oxide film filling 5-6- P type deep layer 2 and p+ type buried layer 91
A plurality of isolated p-type island regions 9 are formed.

(E) Phosphorus is ion-implanted into the region where the pMO8FET 14 will be formed later and spread by thermal diffusion to form the nWell 17.

After this, if you follow the normal MOS process, you will get the structure shown in Figure 3.

Effects of the Invention As is clear from the above explanation, the present invention provides (1)
Complementary MO3 circuit and Bi-CM peripheral circuit of SRAM
An O8 circuit can be used. This results in high sensitivity,
A semiconductor memory device with high speed and low power consumption is realized.

(2) A highly reliable SRAM cell is realized in which the hot carrier generation location is located away from the gate oxide film.

As a comprehensive effect of the above, the original feature of the present invention is D.
High-density SRAM equivalent to RAM or LS containing it
I is realized. As described above, the present invention has extremely high industrial value.

[Brief explanation of drawings]

Figure 1 is a cross-sectional structure of an SRAM cell that is an embodiment of the present invention. Figure 2 is a cross-sectional structure of an SRAM cell that is another embodiment of the present invention. Figure 3 is a complementary type that is another embodiment of the present invention. M
FIG. 4 shows an integrated structure of a MOSFET, bipolar transistor, and SRAM cell, which is another embodiment of the present invention. FIG. 5 shows a complementary MOS and SRAM shown in FIG. 3. It is a manufacturing process diagram for creating an integrated structure with a cell. 1... N-type semiconductor substrate, 2... P-type epitaxial #3.
... Separation region 4 ... (SRAM cell) source or collector 5 ... (SRAM cell) drain, 6
...Gate oxide film 7...Gate, 8...(S
RAM cell) n10 emitter 9...p type island region (SR
base of AM cell), 10...p0 injection 11-=.
Switch Transistor 12・S RAM SE)'v,
13-nMOSFET, 14・=pMOSFE
T, +5-(nMO8FET) n+ source・
Drain, 16... (pMOSFET) p+so 7
−

Claims (10)

[Claims] (1) a second conductivity type island region reaching one principal surface of the first conductivity type semiconductor substrate; a gate provided on the surface of the island region via a gate insulating film; a source/drain of a first conductivity type, and an emitter of a first conductivity type located inside the island region and below the source, the drain being connected to a fixed positive power supply, and the gate and source being connected to a switch transistor. 1. A semiconductor memory device comprising a static memory cell, wherein the emitter is connected to a ground potential via a bit line, and the island region is isolated from an external circuit. (2) The semiconductor memory device according to claim 1, wherein the surface of the island region between the source and drain contains impurities of the first conductivity type. (3) A highly concentrated buried layer of the second conductivity type is provided at the bottom of the island region of the second conductivity type, and at least the top surface of the emitter of the first conductivity type is not in contact with the buried layer of the second conductivity type. A semiconductor memory device according to claim 1, characterized in that: (4) It is characterized by including a second conductivity type ion implantation layer provided inside the substrate and reaching from the source to the drain, and where the highest concentration between the drain and the second conductivity type island region is located inside the substrate. A semiconductor memory device according to claim 1. (5) The surface of the island region between the source and drain contains impurities of the first conductivity type, and a high concentration buried layer of the second conductivity type is provided at the bottom of the island region of the second conductivity type. 2. The semiconductor memory device according to claim 1, wherein at least an upper surface of the conductivity type emitter is not in contact with the second conductivity type buried layer. (6) The surface of the island region between the source and drain contains impurities of a first conductivity type, and further includes an ion implantation layer of a second conductivity type provided inside the substrate and reaching from the source to the drain; 2. The semiconductor memory device according to claim 1, wherein a location with the highest concentration between the conductive island regions is located inside the substrate. (7) A highly concentrated buried layer of the second conductivity type is provided at the bottom of the island region of the second conductivity type, and at least the top surface of the emitter of the first conductivity type is not in contact with the buried layer of the second conductivity type. in,
Moreover, the feature includes a second conductivity type ion-implanted layer provided inside the substrate and reaching from the source to the drain, and a location with the highest concentration between the drain and the second conductivity type island region is located inside the substrate. A semiconductor memory device according to claim 1. (8) a second conductivity type island region reaching one main surface of the first conductivity type semiconductor substrate; a gate provided on the surface of the island region via a gate insulating film; a static memory cell comprising a source/drain of a first conductivity type, and an emitter of a first conductivity type located inside the island region and under the source;
Consisting of a second conductivity type island region, a gate provided on the surface of the second island region via a gate insulating film, and a first conductivity type source/drain separated by the gate and provided at both ends thereof. a first conductivity type MOSFET, a third island region of the first conductivity type, a gate provided on the surface of the third island region via a gate insulating film, and a second MOSFET separated from the gate and provided at both ends thereof. 1. A semiconductor memory device comprising a second MOSFET configured with a source and drain of two conductivity types, and a complementary circuit is configured. (9) a second conductivity type island region reaching one main surface of the first conductivity type semiconductor substrate; a gate provided on the surface of the island region via a gate insulating film; a static memory cell comprising a source/drain of a first conductivity type, and an emitter of a first conductivity type located inside the island region and under the source;
Consisting of a second conductivity type island region, a gate provided on the surface of the second island region via a gate insulating film, and a first conductivity type source/drain separated by the gate and provided at both ends thereof. a first conductivity type MOSFET, a third island region of the first conductivity type, a gate provided on the surface of the third island region via a gate insulating film, and a second MOSFET separated from the gate and provided at both ends thereof. a second MOSFET comprising a source and drain of two conductivity types; a fourth island region of the first conductivity type; a base of the second conductivity type provided within the fourth island region; and the first one provided outside.
A semiconductor memory device equipped with a bipolar transistor consisting of a conductive emitter and collector. (10) A step of introducing a second conductivity type impurity into one principal surface of the first conductivity type semiconductor substrate to form a first buried layer; a step of introducing impurities to form a highly concentrated second buried layer, a step of growing an epitaxial layer of a second conductivity type on the substrate, and a step of separating the epitaxial layer and the first buried layer into a region. A step of forming a plurality of isolated island regions of the second conductivity type surrounded by and after converting an arbitrary number of the plurality of island regions into the first conductivity type, a gate is formed on the surface of the island region via a gate insulating film. and a step of providing a source/drain of a second or first conductivity type in the island region of the first or second conductivity type, respectively. 1. A method of manufacturing a semiconductor memory device, comprising at least a MOSFET as a component.