JPH0254884B2 - - Google Patents

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides a phase modulation signal (hereinafter abbreviated as PM signal in this specification) with a carrier frequency _c according to the amount of relative movement of the wavelength λ with respect to the scale. The present invention relates to an improvement in a displacement amount detection circuit that obtains a resolution of (1/n)λ for the scale of a phase modulation method that digitally detects the amount of movement based on the scale.

[Background technology and its problems] In digital displacement detection circuits that obtain PM signals and detect displacement, there are various difficulties in achieving both response speed and resolution. It was customary to select and use a carrier frequency according to the purpose.

Now, if the recording wavelength of the scale is λ, the carrier frequency is _c , and the amount of displacement is x, then the PM signal e _PM is: e _PM = E _PM sin (ω _c t + 2πx/λ) …(1) However, ω _c = It is expressed as 2π _c . In equation (1), the scale recording wavelength λ
On the other hand, if the resolution R is required, R=λ/n...(2) where n is a positive integer. Therefore, for a phase change of 2π within one period of the carrier frequency _c , the resolution is 1/n. In other words, it is to have a time resolution of 1/n for one period Tc (=1/ _c ) of _c . Therefore, in order to obtain the resolution R (=λ/n), a clock frequency of _ck = (λ/R)· _c = n· _c (3) is required.

In order to increase the resolution R, that is, to decrease λ/R, since λ is constant depending on the scale, n must be increased. Therefore, according to equation (3), a high clock frequency is required. This means that high-speed logic elements are required.

On the other hand, regarding the response speed, considering the state of moving at speed _VM , equation (1) is: e _PM = E _PM sin2π ( _c + V _M /λ) t = E _PM sin2 π ( _c + △ _c ) t... It is transformed as shown in (4). This equation shows that _c needs to be chosen high in order to increase the response speed V _M , as is clear from the fact that the maximum value Δ _MAX that Δ _c can take is considered to be _c . If _c is increased, the interpolation clock frequency must be made even higher than _ck in order to improve the resolution, which not only makes signal processing more difficult but also increases the need for low-power logic elements such as C-MOSICs and large-scale integrated circuit LSIs. This makes it difficult to adopt the system, making it impossible to reduce the power consumption and cost of the system. Also, the use of multiple carrier frequencies has the disadvantage of complicating the circuit.

[Object of the Invention] The object of the present invention is to enable the application of low-speed logic elements while satisfying high resolution and high-speed response performance using a single carrier frequency, thereby reducing the size, power consumption, and cost of the system. Another object of the present invention is to provide a displacement detection circuit in a phase modulation type position reading device having a novel configuration, which makes it possible to improve reliability.

[Summary of the Invention] In order to achieve the above object, the displacement detection circuit according to the present invention uses a clock signal of a frequency of (n/m) _c to obtain a movement signal with a resolution of (m/n)λ. It operates with the main interpolation part _of
n) The gist is to include a sub-interpolation circuit that divides into λ units.

[Examples] The present invention will be explained in more detail below using Examples with reference to the drawings, but these are merely illustrative and various modifications and improvements can be made without going beyond the scope of the present invention. Of course it is possible.

FIG. 1 is a block diagram showing the basic configuration of a displacement detection circuit according to the present invention.

The waveform-shaped PM signal of carrier frequency _c (hereinafter abbreviated as S signal in this specification) is
Since it occurs asynchronously with the clock signal CK ₂ of the interpolation circuit, it is added to the first synchronization circuit 1 and synchronized with the clock signal CK ₁ having a frequency of n _c .
Next, the output of the first synchronization circuit 1 is guided to the second synchronization circuit 2, where it is synchronized with a clock signal having a frequency of (n/m) _c . 3 is the main interpolation circuit that has been used conventionally, for example, the
No. 28032 or JP-A-57-30909, JP-A-57-
The circuit described in No. 514 was used, and direction discrimination with a resolution of (m/n)λ was performed using a clock signal of a frequency of (n/m) _c from the output of the second synchronization circuit 2. Obtain output pulse 6.

As disclosed in the above publication, the main interpolation circuit 3 operates at (n/m) in one cycle time (1/ _c ) of _c .
Since the clock pulse of _c is interpolated, the phase change (time change) of one pulse of the clock pulse (n/m) _c corresponds to the displacement corresponding to the resolution (m/n) λ.

Now, as mentioned above, the main interpolation circuit 3 is (n/m)
Since a clock signal with a frequency of _c is used, it does not respond to displacement within the interval (m/n)λ corresponding to its resolution, that is, the interval corresponding to one pulse of the clock signal, and this interval becomes a dead interval. .

Conventionally, for this reason, the clock frequency was increased as mentioned above in order to further increase the resolution.
In the present invention, a sub-interpolation circuit is used to avoid an increase in clock frequency.

This sub-interpolation circuit is the dead interval (n/
m) It is intended to obtain a resolution of (1/n)λ in an interval of λ, and the first and second synchronization circuits 1,
2, a gate circuit 4 and an m-ary counter 5. The two S signals S ₁ and S 2 synchronized by the first synchronization circuit 1 and the second synchronization circuit ₂ are sent to the gate circuit 4 together with the clock signal CK ₁ of frequency n _c .
added to. This gate circuit 4 is (n/m)
Within one period of the clock signal CK ₂ of _c , that is, (m/
n) 0 to m- depending on the position of the _S1 signal between λ
Outputs 1 pulse. This is essentially a division (interpolation) of the (m/n)λ interval into 1/m, and the output of the gate circuit 4 is connected to the m-ary counter 5, and this count output 7 is Insert circuit 3
It is clear that a signal having a resolution of λ/n can be obtained by simultaneously calculating the outputs 6 of .

A more detailed explanation will be given below based on a specific example.

FIG. 2 is a block diagram showing the configuration of an application example of the present invention that is optimal for combination with a system using a microcomputer, etc., and shows synchronization circuits 8, 9,
10, gate circuits 11 and 12, and a counter 13 constitute a data output type sub-interpolation circuit. In a displacement detection system using Magnescale, the scale wavelength λ is generally 200μ.
m is often used. In order to achieve a resolution of 1 μm at a carrier frequency _c = 50kHz, n
= 200, therefore a 10MHz clock signal is required.
In the example, m = 10 is selected, for example,
The main interpolation section described in No. 57-514 has a resolution of 10 .mu.m, and the sub-interpolation section according to the present invention has a resolution of 1 .mu.m.

In FIG. 2, 8 and 9 are two-stage synchronization circuits corresponding to the first synchronization circuit,
Synchronize the asynchronous signal S _IN corresponding to the PM signal with the 10MHz clock signal _CK1 . Output of synchronization circuit 8
The SY _1D signal is determined at which position in one section of the clock signal CK ₂ applied to the main interpolation circuit, that is, a 10 μm section, at which point the S _IN signal becomes active (Low active).
This is a signal that indicates whether the current level has fallen, and the falling edge is referenced. 10 is a second synchronization circuit, which uses a 1MHz clock signal CK ₂ as a synchronization pulse.
is used, and its output SY _1M signal is CK ₂
It is also input to a known main interpolation circuit 14.

11 is a gate circuit, the SY _2D signal is activated,
The period until the SY _1M signal is activated, i.e.
Interpolated in the interval corresponding to the dead interval of the main interpolation circuit where SY _2D is “L” and SY _1M signal is “H”
Outputs CK ₁ signal, ie CP signal.

As mentioned above, in order to detect at which position within 10 μm of one section of the CK ₂ signal the S _IN signal is activated, the SY _1D signal should be referenced, but the circuit configuration can be simplified. For this purpose, the SY _2D signal is used.

The gate circuit 12 is a control circuit that generates a preset pulse PR for initializing the 4-bit binary counter 13, which corresponds to the m _- ary counter _.
One pulse is output at the timing of . With this output, the counter 13 that counts the CP signal
1 and corrects the decimated CP pulse by reference to the SY _2D signal.

FIG. 3 shows the situation when a minute displacement occurs in the dead section that cannot be detected by the main interpolation circuit 14. In period T ₁ it is stationary, and in period T ₂ it is CK _1.
This shows a timing chart when a displacement equivalent to 3 signal pulses, or 3 μm, occurs. t ₀
When the S _IN signal falls, the SY _1D signal falls in synchronization with the CK ₁ signal, and with a time delay of one pulse of the CK ₁ signal, the SY _2D signal also falls. The pulse PR generated during the period when the SY _1D signal is "L" and the SY _2D signal is "H" presets the counter 13 to 1, and when the SY _2D signal is "L" and the SY _1M signal is "H". The counter 13 is caused to count by one value larger than the pulse CP generated during the period , that is, by the amount corresponding to when referring to the SY _1D signal.
In the example of FIG. 3, the counter 13 counts 6 at the end of the CP pulse after _t0 , and holds this value until it is initialized at the next timing _t1 . During the t ₁ period, it remains stationary, so the timing t ₁
However, the displacement in the T ₂ cycle is equivalent to 3 μm because the value of the counter 13 after timing t ₂ counts 3 using the same procedure. Detected.

Next, an actual displacement detection method according to the present invention including a sub-interpolation circuit will be explained. Japanese Patent Publication No. 57-514
The main interpolation circuit is S _IN
For each cycle of the signal, the detected movement amount is output in an incremental data output format. Therefore, to measure the actual cumulative displacement, S _IN
It is obtained by adding incremental data output for each period of the signal. The resolution of the main interpolation circuit is in units of 10 μm, and if this quantization unit is even slightly exceeded, it is determined that a movement of 10 μm has occurred. On the other hand, the sub-interpolation circuit detects one period of the _CK2 clock that cannot be detected by the main interpolation circuit for each period of the S _IN signal, that is, the dead period of 10μ.
Outputs data that absolutely represents the actual amount of minute displacement within the m section. That is,
The sub-interpolation circuit detects the actual displacement in units of 1 μm, and the value of the counter 13 is an accurate value corresponding to the extra movement amount (in units of 1 μm) detected by the main interpolation circuit, so the actual displacement is detected in units of 1 μm. In order to obtain the amount of movement, the amount obtained from the main interpolation circuit at the timing to be measured must be
By subtracting the value of the counter 13 of the sub-interpolation circuit (in units of 1 μm) obtained at that timing from the cumulative value of the incremental movement in units of 10 μm, the accurate cumulative amount of movement can be determined with a resolution of 1 μm. Can be done.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

1. Resolution can be improved without increasing the clock frequency of the main interpolation circuit.

2. Conventionally, multiple carrier frequencies have been used due to the need for response speed and resolution, but all applications can be handled using only a single carrier frequency, and complete compatibility between systems is maintained.

3 The additional elements necessary for the present invention are only a few parts such as a counter and a flip-flop, and can be treated as an additional circuit to the basic configuration conventionally used. The same processing format can be adopted regardless of the presence or absence.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a displacement detection circuit according to the present invention, and FIG. 2 is a block diagram showing the configuration of an application example of the present invention that is optimal for combination with a system using a microcomputer or the like.
FIG. 3 is a timing chart of the device shown in FIG. DESCRIPTION OF SYMBOLS 1...First synchronization circuit, 2...Second synchronization circuit, 3...Main interpolation circuit, 4...Gate circuit, 5
... m-ary counter, 6 ... Output of main interpolation circuit, 7
... Output of m-ary counter, 8 to 10 ... Synchronization circuit, 11, 12 ... Gate circuit, 13 ... Decimal binary counter, 14 ... Main interpolation circuit.

Claims (1)

[Claims] 1. In a phase modulation type displacement detection device that detects a displacement amount based on a phase modulation signal of a carrier frequency _c corresponding to an amount of relative movement with respect to a scale of a wavelength λ, the phase modulation signal is a first synchronization circuit synchronizing with a first clock signal having a frequency of _c ;
A second synchronization circuit synchronizes the output signal of the synchronization circuit with a second clock signal having a frequency of (n/m) _c , the first clock signal, and the outputs of the first and second synchronization circuits. A gate circuit which receives a signal and outputs 0 to m-1 pulses according to the position of the output signal of the first synchronization circuit within one cycle of the second clock signal, and the output pulse of the gate circuit. a sub-interpolation circuit consisting of an m-ary counter for counting, and a movement signal corresponding to the displacement having a resolution of (m/n)λ from the output signal of the second synchronization circuit and the second clock signal. A displacement amount detection circuit comprising: a main interpolation circuit that outputs an output; 2. The first synchronization circuit consists of two stages of synchronization circuits, and includes a control circuit that initializes the counter to an initial value of 1 from the output signal of the synchronization circuit of each stage and the first clock signal. A displacement amount detection circuit according to claim 1, characterized in that: