JPH0245996A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPH0245996A JPH0245996A JP19671388A JP19671388A JPH0245996A JP H0245996 A JPH0245996 A JP H0245996A JP 19671388 A JP19671388 A JP 19671388A JP 19671388 A JP19671388 A JP 19671388A JP H0245996 A JPH0245996 A JP H0245996A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal
- conductor
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000004544 sputter deposition Methods 0.000 claims abstract description 9
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 5
- 229910018487 Ni—Cr Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 17
- 238000007747 plating Methods 0.000 claims description 11
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 7
- 239000000919 ceramic Substances 0.000 abstract description 6
- 238000009713 electroplating Methods 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000003989 dielectric material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910018106 Ni—C Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electrodes Of Semiconductors (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路の製造方法に関し、特に導体層の
形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a hybrid integrated circuit, and more particularly to a method of forming a conductor layer.
従来、この種の混成集積回路における導体層は、スパッ
タまたは蒸着によりＴ ｉ ／ Ｐ ｄ ／ Ａ ｕあ
るいはＮ ｉ −Ｃｒ ／ Ｐ ｄ ／ Ａ ｕなど種
類の異なる金属層を形、成し、レジストのパターン化工
程およびエツチング工程により所定の回路を形成するも
のが殆んどであるが、厚いＡｕメッキを併用するものも
あった。第２図は従来の混成集積回路の一例の断面図で
ある。以下その製造方法について説明する。Conventionally, the conductor layer in this type of hybrid integrated circuit is formed by forming different types of metal layers such as Ti/Pd/Au or Ni-Cr/Pd/Au by sputtering or vapor deposition, and then using a resist layer. Most of them form a predetermined circuit through a patterning process and an etching process, but some also use thick Au plating. FIG. 2 is a cross-sectional view of an example of a conventional hybrid integrated circuit. The manufacturing method will be explained below.
まずセラミックス基板１上に約０．１μｍ厚のＮｉ−Ｃ
ｒ層１５とＰｄ層１６および０．５〜１．０μｍ厚のＡ
ｕ層１７をスパッタにより形成する。次にこれらを下地
層として電解メッキによりＡｕ層１８を形成する。First, about 0.1 μm thick Ni-C was placed on the ceramic substrate 1.
r layer 15, Pd layer 16 and 0.5 to 1.0 μm thick A
The u layer 17 is formed by sputtering. Next, using these as a base layer, an Au layer 18 is formed by electrolytic plating.
メッキを併用した導体のパターン化の類似した方法とし
てセミアデイティブ法がある。第３図は第２の従来例と
してセミアデイティブ法により形成された導体層を有す
る混成集積回路の断面図である。A semi-additive method is a similar method for patterning conductors using plating. FIG. 3 is a sectional view of a second conventional example of a hybrid integrated circuit having conductor layers formed by a semi-additive method.
これはセラミックス基板１上に無電解メッキにより厚さ
約１．０μｍの比較的薄いＣｕ層１つを形成し被メッキ
部以外をレジストにて保護し、被メッキ部のみに電解メ
ッキにより約３．０〜１０．０μｍの比較的厚いＣｕ層
２０を形成し、レジスト剥離後に露出した薄い無電解Ｃ
ｕメッキ層をエツチング除去することにより導体パター
ンを形成する方法である。A relatively thin Cu layer of about 1.0 μm thick is formed on the ceramic substrate 1 by electroless plating, the parts other than the plated part are protected with a resist, and only the part to be plated is electrolytically plated to a thickness of about 3.0 μm. A relatively thick Cu layer 20 of 0 to 10.0 μm is formed, and the thin electroless C layer is exposed after resist removal.
This method forms a conductor pattern by etching away the U plating layer.
上述した従来の混成集積回路の製造方法のうち、第３図
で説明したものでは、比較的厚いＡｕ層を基板全面に成
膜した後に、不要部分をエツチング除去するために、多
くの工数を必要とし、且つ無駄となるＡｕの割合が非常
に高かった。また導体層そのものに使用されるＡｕの量
も多く、このなめ混成集積回路のコストが高くなるとい
う欠点があった。混成集積回路は、構成される抵抗体お
よび誘電体などの薄膜素子が電気的に高い精度と信頼性
を有しているにもかかわらず、限定された用途にしか用
いられていない主な理由はこのコストか高いことに起因
している。Among the conventional methods for manufacturing hybrid integrated circuits mentioned above, the method explained in FIG. 3 requires a large number of man-hours to remove unnecessary parts by etching after forming a relatively thick Au layer over the entire surface of the substrate. Moreover, the proportion of wasted Au was extremely high. In addition, a large amount of Au is used in the conductor layer itself, which has the disadvantage of increasing the cost of this slanted hybrid integrated circuit. The main reason why hybrid integrated circuits are only used for limited purposes is because the thin film elements such as resistors and dielectrics that make up them have high electrical accuracy and reliability. This is due to the high cost.
また、スパッタのみにより導体層を形成した場合、導体
層は１μｍ以下の厚みで使用される場合が多く、パター
ン化後の配線抵抗は必然的に高いものとなる。通常この
影響を軽減するために、配線パターン幅に余裕をもたせ
た設計を行なうが、回路の実装密度を上げる上で好まし
くない。配線抵抗を下げるための特殊な例として、はん
だデイツプにより導体上にはんだ層を形成する方法があ
るが、組立ての制約を受けると同時に余計な工数を必要
とする。Further, when a conductor layer is formed only by sputtering, the conductor layer is often used with a thickness of 1 μm or less, and the wiring resistance after patterning is inevitably high. Normally, in order to reduce this effect, a design is made in which the wiring pattern width has a margin, but this is not preferable in terms of increasing the circuit packaging density. As a special example of reducing wiring resistance, there is a method of forming a solder layer on a conductor using a solder dip, but this method is subject to assembly constraints and requires extra man-hours.
第４図に示した導体層を有するものについては、コスト
的に大きなメリットがあるものの、基板上の抵抗体およ
び誘電体などの薄膜素子との接続部が電気的に安定せず
、また導体層表面にＣｕ層が露出するために作業工程中
や保管中に表面を保護しなければならないなどの欠点が
ある。Although the device with the conductor layer shown in Fig. 4 has a large cost advantage, the connections with thin film elements such as resistors and dielectrics on the substrate are not electrically stable, and the conductor layer Since the Cu layer is exposed on the surface, there are drawbacks such as the need to protect the surface during the working process and during storage.
本発明の混成集積回路の製造方法は、スパッタまたは蒸
着により形成される第１の金属層とメッキにより形成さ
れる第２の金属層とにより導体層を構成する混成Ｓ積回
路の製造方法において、前記第１の金属層をＴｉ、Ｎｉ
−Ｃｒ、Ｃｒのうちいずれか１種の金属層とＣｕ層とか
ら形成し、前記第２の金属層の少くとも最上層をＡｕか
ら形成するものである。A method for manufacturing a hybrid integrated circuit according to the present invention is a method for manufacturing a hybrid S integrated circuit in which a conductor layer is formed by a first metal layer formed by sputtering or vapor deposition and a second metal layer formed by plating. The first metal layer is made of Ti, Ni
The second metal layer is formed of a metal layer of any one of -Cr and Cr and a Cu layer, and at least the uppermost layer of the second metal layer is formed of Au.
次に、本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図（ａ、 ）〜（ｄ）は本発明の一実施例を説明す
るための工程順に示したチップの断面図である。FIGS. 1(a, 1d) to 1(d) are cross-sectional views of a chip shown in order of steps for explaining an embodiment of the present invention.
まず第１図（ａ）に示すように、セラミックス基板１上
にスパッタまたは蒸着によりＴｉ層２およびＣｕ層３を
形成する。ここでＴｉ層２はセラミックス基板１あるい
は抵抗体及び誘電体などの薄膜回路素子電極との密着性
を良好に保つための密着金属層であって、Ｔｉの他Ｎｉ
−Ｃｒ。First, as shown in FIG. 1(a), a Ti layer 2 and a Cu layer 3 are formed on a ceramic substrate 1 by sputtering or vapor deposition. Here, the Ti layer 2 is an adhesion metal layer for maintaining good adhesion with the ceramic substrate 1 or thin film circuit element electrodes such as resistors and dielectrics.
-Cr.
Ｃｒなどを用いてもよい これらの密着金属層は、０．
０５〜０．１μｍ程度の薄い金属層でも十分な効果が得
られる。These adhesive metal layers may be made of Cr or the like.
A sufficient effect can be obtained even with a thin metal layer of about 0.05 to 0.1 μm.
この密着金属層のみではその上にメッキにより成膜され
る金属との密着性を初期状態で十分に得ることが困難で
あるため、入念なメッキ前処理とアニール工程が必要と
されるが、メッキにより形成される金属層との密着を容
易に得られるＣｕ層をあらかじめスパッタあるいは蒸着
によって０．５〜１．Ｃ）ｌｉｍの厚さに形成しておく
ことにより、後のメッキによる成膜が非常に容易なもの
となる。また、スパッタあるいは蒸着によって形成され
る金属層は、後のメッキ工程においてカソード電極とな
るが、Ｃｕのように導電率の高い金属を選択することに
より、基板上の電流密度のばらつきを低くおさえること
ができる。次に、導体層となる被メッキ部以外の部分を
レジスト４により被覆する。With this adhesive metal layer alone, it is difficult to obtain sufficient adhesion with the metal to be plated on top of it in the initial state, so careful plating pretreatment and annealing process are required. A Cu layer with a thickness of 0.5~1. C) By forming the film to a thickness of lim, it becomes very easy to form a film by plating later. In addition, the metal layer formed by sputtering or vapor deposition becomes a cathode electrode in the subsequent plating process, but by selecting a metal with high conductivity such as Cu, it is possible to suppress variations in current density on the substrate. Can be done. Next, the portion other than the portion to be plated, which will become the conductor layer, is covered with a resist 4.
次に、第１図（ｂ）に示すように、レジスト４をマスク
とじＣｕ層上に電解メッキによりＣｕ層５およびＡｕ層
６を形成する。これらのメッキ層はＣｕ、Ｎｉ、Ａｕな
ど用途に応じて選択可能であり、金属層の厚みも所望の
厚みに設定することとが可能である。Next, as shown in FIG. 1(b), the resist 4 is masked and a Cu layer 5 and an Au layer 6 are formed on the Cu layer by electrolytic plating. These plating layers can be selected from Cu, Ni, Au, etc. depending on the application, and the thickness of the metal layer can also be set to a desired thickness.
次に第１図（Ｃ）に示すように、レジスト４を剥離した
のち、第１図（ｄ）に示すように、レジスト４の剥離に
よって露出した下地金属層であるＣｕ層３及びＴｉ層２
をエツチングにより除去し、Ｔｉ層２．Ｃｕ層３．Ｃｕ
層５及びＡｕ層６からなる導体層を形成する。Next, as shown in FIG. 1(C), after peeling off the resist 4, as shown in FIG.
is removed by etching, and the Ti layer 2. Cu layer 3. Cu
A conductor layer consisting of layer 5 and Au layer 6 is formed.
メッキにより形成される金属層のうち、最上層をＡｕ層
６とすることにより、エツチングによる導体層の劣化が
起きなくなり、幅３０μｍ￥ｒｒｆ後の細い配線のパタ
ーン化が容易になると同時に、使用されるエッチャント
の選択範囲を広げることができる。使用されるエッチャ
ントとしてはＴ ｉ ／ Ｃｕ ｔｌＩ成の場合、Ｃｕ
エッチャントとしてＨ２ＳＯ４，Ｈ２Ｏ２系が適切であ
り、ＴｉエッチャントとしてはＨＦ、ｃＨ３ＣＯＯＨ系
が容易に適用可能である。Of the metal layers formed by plating, by making the top layer the Au layer 6, deterioration of the conductor layer due to etching will not occur, and at the same time, it will be easier to pattern thin wiring after a width of 30 μm. You can expand the selection range of etchants. In the case of Ti/Cu tlI formation, the etchant used is Cu
H2SO4 and H2O2 systems are suitable as etchants, and HF and cH3COOH systems are easily applicable as Ti etchants.
以上説明したように本発明は、混成集積回路の導体層を
構成する、スパッタまたは蒸着により形成される第１の
金属層とメッキにより形成される第２の金属層のうち、
第１の金属層をＴｉ、ＮｉＣｒ、Ｃｒのうちいずれか１
種の金属層とＣｕ層とから形成し、第２の金属層の少く
とも最上層をＡｕから形成することにより、抵抗体や誘
電体等の薄膜素子を有する基板に抵抗の小さい厚い導体
配線を容易に形成することができる。しがち配線幅を狭
くできるので、高密度実装が可能となる。更に最上層に
Ａｕ層を形成することにより、微細配線の形成が容易に
なると共に、Ａｕの使用量を低減できるため、コストを
低減できる効果もある。As explained above, the present invention provides a first metal layer formed by sputtering or vapor deposition and a second metal layer formed by plating, which constitute a conductor layer of a hybrid integrated circuit.
The first metal layer is made of one of Ti, NiCr, and Cr.
By forming a seed metal layer and a Cu layer, and forming at least the uppermost layer of the second metal layer from Au, thick conductor wiring with low resistance can be formed on a substrate having thin film elements such as resistors and dielectrics. Can be easily formed. Since the wiring width, which tends to be narrowed, can be narrowed, high-density packaging is possible. Furthermore, by forming the Au layer as the top layer, it becomes easier to form fine wiring, and the amount of Au used can be reduced, which has the effect of reducing costs.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した断面図、第２図及び第３図は従来の
混成集積回路の製造方法を説明するための断面図である
。
１・・・セラミックス基板、２・・・Ｔｉ層、３・・・
Ｃｕ層、４・・・レジスト、５・・・Ｃｕ層、６・・・
Ａｕ層、１５・＝Ｎ ｉ −Ｃｉ層、１６ ・Ｐ ｄ層
、１７−Ａｕ層、１Ｂ・・−Ａｕ層、１９−・Ｃｕ層、
２０−・−Ｃｕ層。FIGS. 1(a) to (d) are cross-sectional views shown in the order of steps for explaining one embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views for explaining a conventional method for manufacturing a hybrid integrated circuit. FIG. 1... Ceramic substrate, 2... Ti layer, 3...
Cu layer, 4... resist, 5... Cu layer, 6...
Au layer, 15-=Ni-Ci layer, 16-Pd layer, 17-Au layer, 1B--Au layer, 19--Cu layer,
20-.-Cu layer.
Claims (1)
メッキにより形成される第２の金属層とにより導体層を
構成する混成集積回路の製造方法において、前記第１の
金属層をＴｉ，Ｎｉ−Ｃｒ，Ｃｒのうちいずれか１種の
金属層とＣｕ層とから形成し、前記第２の金属層の少く
とも最上層をＡｕから形成することを特徴とする混成集
積回路の製造方法。a first metal layer formed by sputtering or vapor deposition;
In the method for manufacturing a hybrid integrated circuit in which a conductor layer is formed by a second metal layer formed by plating, the first metal layer is formed by forming a conductor layer with a metal layer of any one of Ti, Ni-Cr, and Cr. A method for manufacturing a hybrid integrated circuit, characterized in that at least the uppermost layer of the second metal layer is made of Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19671388A JPH0245996A (en) | 1988-08-05 | 1988-08-05 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19671388A JPH0245996A (en) | 1988-08-05 | 1988-08-05 | Manufacture of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0245996A true JPH0245996A (en) | 1990-02-15 |
Family
ID=16362351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19671388A Pending JPH0245996A (en) | 1988-08-05 | 1988-08-05 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0245996A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117784A (en) * | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
| JP2005328019A (en) * | 2004-04-12 | 2005-11-24 | Toppan Printing Co Ltd | Manufacturing method of printed wiring board with built-in element |
| JP2006024754A (en) * | 2004-07-08 | 2006-01-26 | Advanced Lcd Technologies Development Center Co Ltd | Wiring layer, forming method thereof, and thin-film transistor |
| JP2007134458A (en) * | 2005-11-09 | 2007-05-31 | Shinko Electric Ind Co Ltd | Wiring substrate manufacturing method and semiconductor device manufacturing method |
| CN109661114A (en) * | 2017-10-11 | 2019-04-19 | 欣兴电子股份有限公司 | The method for manufacturing conducting wire |
-
1988
- 1988-08-05 JP JP19671388A patent/JPH0245996A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117784A (en) * | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
| JP2005328019A (en) * | 2004-04-12 | 2005-11-24 | Toppan Printing Co Ltd | Manufacturing method of printed wiring board with built-in element |
| JP2006024754A (en) * | 2004-07-08 | 2006-01-26 | Advanced Lcd Technologies Development Center Co Ltd | Wiring layer, forming method thereof, and thin-film transistor |
| JP2007134458A (en) * | 2005-11-09 | 2007-05-31 | Shinko Electric Ind Co Ltd | Wiring substrate manufacturing method and semiconductor device manufacturing method |
| CN109661114A (en) * | 2017-10-11 | 2019-04-19 | 欣兴电子股份有限公司 | The method for manufacturing conducting wire |
| US10615054B2 (en) | 2017-10-11 | 2020-04-07 | Unimicron Technology Corp. | Method for manufacturing conductive line |
| CN109661114B (en) * | 2017-10-11 | 2021-02-05 | 欣兴电子股份有限公司 | Method for manufacturing conductive wire |
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