JPH0239768A - Digital color copying machine - Google Patents

Abstract

PURPOSE:To improve the convenience of a superimposing function by registering the superimposing picture in a notable area in a picture memory means as multivalue data or binary data according to the selection of a selecting means, and reading it in an prohibiting are on a copying paper. CONSTITUTION:The registered picture data in an area designated on an original beforehand are registered on a memory. When the registered picture is a halftone picture such as a photograph, the multivalue output value of an R, a G and a B in a shading correcting circuit 23 is stored into the memory of a registered picture memory circuit 1 as the registered picture data. When the registered picture is the binary picture such as a character, etc., however, the multivalue output value in the correcting circuit 23 is converted into the binary data of printing colors Y, M and C, and stored. Consequently, even when the memory at the same capacity is used, the registered picture data in the larger area can be stored compared with the case of storing the multivalue data. For example, when the output value of the correcting circuit 23 is at eight bits, the registered picture in the eight-times larger area can be superimposed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital color photographic device having a superimpose function.

(Prior Art) A digital color copying machine includes a reading section that reads a document using a color + i image element and converts it into a print output signal (binary), and an image printed on paper using an electrophotographic method in response to this print output signal. When performing printout in multiple colors, the reading unit reads the document and the printer unit prints the image on the same paper in a field-sequential manner for each color.

The superimpose function is a useful function in digital color copying machines. In this function, an image for superimposition is read from a document and stored in memory. Then, when copying another document, by reading the image data from the memory and copying it, it is possible to copy the image of the other document overlapping a part of the image of this document.

(Problem to be Solved by the Invention) In a conventional digital color copying machine with a superimpose function, the image data for superimposition stored in the memory is the 2-digit image data after the binarization processing of the read data (multivalued).
It was value data.

On the other hand, if multivalued data before binarization processing is stored in memory, color adjustment and scaling processing can be performed on the superimpose image. Therefore, a digital color copying machine has been proposed that registers multi-value data in a memory and superimposes the data.

However, if there is no need to perform scaling or color correction after registration, storing the data as multivalued data has the disadvantage of requiring a large memory capacity. When storing as binary data in the same memory capacity, a wider area of images can be registered than when storing as multi-value data. For example, if the multivalued data is 8 bits, eight times as many areas can be registered. Therefore, depending on the purpose of use, it may be more effective to perform image registration and superimposition using binary image data after halftone processing. Therefore, if the user-friendliness of the superimpose function can be improved if it is possible to select whether to store a registered image in multi-valued or binary form based on the necessity of scaling and color correction after registration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital color copying machine that can select a multivalued image or two (one) image as a registered image when reading an image for superimposition from a document and registering it in a memory in a superimpose function. be.

(Means for Solving the Problems) A digital color copying machine according to the present invention includes: an image storage means for storing image data; an area setting means for setting an attention area on a document and a prohibited area on a copy sheet; A binarization means for binarizing the multi-value image read data into binary print data for image printing, and an image storage means containing the multi-value image read data and the binary print data after being binarized by the binarization means. A selection means for selecting whether to store the document image in the area of interest set by the area setting means, and a binarization means interposed before or after the image storage means in accordance with the selection by the selection means, and the image data is image registration means for storing the image in the image storage means as multivalued image reading data or binary print data;
a printing means for printing on the copy paper based on image printing data; and an image storage means for converting the binarization means according to the selection by the selection means when printing in the prohibited area on the copy paper set by the area setting means. reading the image data of the registered image registered in the image storage means,
The present invention is characterized by comprising registered image printing control means for sending image printing data to the printing means.

(Function) The image of the area of interest on the document can be selected by the selection means as either a multivalued image or a 2 (orthogonal) image after halftone processing, depending on the purpose. Binarization is performed according to the selection by the selection means. The means can be interposed before or after the image storage means.In other words, when a multivalued image is selected, the image storage means can be interposed before the binarization means, and the multivalued image read data (
For example, the three colors R, G, and B) are stored in the image storage means.
oru.

When printing, the multivalued image reading data is read out, and the binarization means converts it into binary print data (for example, three values of Y, M, and C).
After converting the image into a print color (printing color), it is output to a printing means as image printing data. On the other hand, if a binary image is selected,
An image storage means is interposed after the digitization means, and the multivalued image read data is binarized by the binarization means, converted into binary print data, and outputted to the printing means. In this way, the image registration means and the registered image printing control means register the image for superimposition of the region of interest in the image storage means as multivalued data or binary data according to the selection by the selection means, and print the superimposed image on the copy paper. Cannot be read in prohibited area.

(Embodiments) Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings.

(a) Configuration of digital color copying machine (b) Superimpose function (C) Mosaic monitor (d) Registered image memory circuit <d-1> Circuit configuration <d-2> Superimpose mode in which bt is recorded in multi-values <d-3> Variable magnification <d-4> Writing and reading in mosaic monitor mode d-5> Superimpose mode for S2 memory in 2 (direct) <d-6> Single color (2 ( Direct) and -2 superimpose mode <d-7> Mixing of multi-value storage and binary storage <d-8> Area discrimination circuit and address generation counter <(1-9> Writing of multiple images and Readout e) Image level setting circuit (r) Flow of copy control Margin below (a) Structure of digital color copying machine The digital color copying machine according to the present invention uses an image sensor to read a document and convert it into a printout signal. Consists of a reading unit and a printer unit that prints an image on paper using electrophotography in response to this print output signal.When printing out multiple colors, the reading unit reads the original for each color. The printer unit prints images on the paper in a field-sequential manner.

FIG. 1 shows the overall configuration of a digital color copying machine according to an embodiment of the present invention. The scanner 10 includes an exposure lamp 12 that illuminates the original, a rod lens array 13 that collects reflected light from the original, and a contact type COD color sensor (image sensor) 14 that converts the collected light into an electrical signal. There is. When reading a document, the scanner 10 is driven by a motor 11 to move in the direction of the arrow, and scans the document placed on the platen 15. The image of the document surface illuminated by the light source I2 is photoelectrically converted by the CCD color sensor I4.

The three-color electrical signals (multi-value) of fl, G, and B obtained by the CCD color sensor I4 are processed by the reading signal processing unit 20 into a print output signal (binary) of yellow, magenta, cyan, or black. is converted into buffer memory 30
is memorized. In the print head unit 31, an LD drive circuit 32 causes a semiconductor laser (LD) 33 to blink (second
(see figure).

As shown in FIG. 1, the laser beam generated by the semiconductor laser 33 in response to the print signal is transmitted through a reflecting mirror 37.
The rotationally driven photoreceptor drum 4I is exposed. As a result, an image of the document is drawn on the photoreceptor 2 of the photoreceptor drum 41. The photoreceptor drum 4I is irradiated with an eraser lamp 42 on the seedlings that are exposed to light for each trace, and a charging deformer 43 is applied to the photoreceptor drum 4I.
, and is irradiated with a laser lamp 44 . When exposed to light in this charged state, a static 7rim image is formed on the photosensitive drum 41. Yellow, magenta, cyan, and black toner developers 45a~
Only one of 45 (1) is selected and develops the electrostatic latent image on the photoreceptor drum 41.

The developed image is transferred by the transfer charger 46 to vapor wrapped around the transfer drum 51.

Usually, this printing process is repeated for yellow, magenta, red, and black. At this time, the scanner IO repeats the scanning operation in synchronization with the operations of the photosensitive drum 41 and the transfer drum 51. Thereafter, the vapor is separated from the transfer drum 51 by operating the separating claw 47, is fixed through the fixing device 48, and is discharged onto four paper discharge trays.

Note that the vapor is fed from a paper cassette 50, and its leading end is chucked by a chucking mechanism 52 on the transfer drum 5I to prevent misalignment during transfer.

Next, with reference to FIG. 2, a description will be given of the signal processing section 20 that processes the output signal of the CCD sensor 14 and outputs a binary image signal. Note that, as shown later in FIG. 8, the registered image memory circuit 1 is also inserted after the halftone processing circuit 27 (that is, after the binarization process) in the case of binary storage.

When outputting a normal image, the image signal photoelectrically converted by the COD color sensor I4 is converted into an image density by the log amplifier 2I, and then converted into a digital 1m by the A/D converter 22.
(multivalued). This numerically converted red R1 green G
, blue B image signal is sent to the shading hti positive circuit 23
The engine aging is corrected. As explained later,
In the superimpose mode (multi-level storage) or mosaic monitor mode, the signal of the setting area that has undergone shading correction is stored in the registered image memory circuit 1. (Normal (
In the 9-shot mode or the super innovative mode (binary storage), the image signal is not processed by the registered image memory circuit I, but is sent to the masking processing circuit 24. ) The above processing is performed using R
, G, and B are processed in parallel. Next, the masking processing circuit 24 performs printing in the field sequential manner, so that the masking processing circuit 24 performs printing in order of printing. Generates a signal for one of the printing colors (yellow magenta, cyan, or black) according to the characteristics of the printing toner from the three human signals from the positive circuit 23 or the registered image memory circuit (in the case of multi-value storage). do. A control signal from the CPU 25 determines which print color a signal is to be generated. The masking processing circuit 24 is provided with an undercolor removal (UCfl) circuit and a black printing (BP) amount generation circuit, which generate a black amount in the case of black printing.

(In superimpose mode (binary storage), the print signal is temporarily stored in the registered image memory circuit 1.) The image setting circuit 2 performs color adjustment on the print signal in superimpose mode, mosaic monitor mode, etc. This is the circuit to apply. If the color adjustment of the bleached candy is sufficient, the output signal of the masking processing circuit 24 is immediately passed to the electric magnification circuit 26.

The electric magnification circuit 26 electrically processes the signal from the masking processing circuit 24 or the image level setting circuit 2 to electrically change the magnification in the main scanning direction.The method is well known and will be described here. The explanation will be omitted here. On the other hand, variable magnification in the sub-scanning direction can be realized by variably shifting the speed of relative movement between the developing device and the scanner 10. The halftone processing circuit 27 is
The signal from the electric magnification circuit 26 is binarized to generate a binary pseudo intermediate signal (print output signal) and sent to the sofa memory 30. The LD drive circuit 32 drives the semiconductor laser 33 in response to the pseudo halftone signal of the buffer memory 30 to emit a laser beam.

Note that the clock generator 28 is connected to the COD color sensor 14.
It generates a horizontal synchronization signal "JI-Tsync" and a clock signal CKA for horizontally synchronizing the reading of image data and the image data processing of each circuit.In addition, the two sub-scanning clock generators for variable magnification are A sub-scanning clock for magnification change, which is an interrupt signal to the registered image memory circuit l, is generated in accordance with the signal.

As explained later, this digital color (Natsushaki)
It has a superimpose function and a color adjustment function called a mosaic monitor. Both functions require a memory to store image data, and since the image processing is also common, the registration image memory circuit 1 for image registration and continuous output and the image tone setting circuit 2 for color adjustment are shared. , and are controlled by the CPU 25 to realize both functions.

In the signal processing section 20, image data is processed at the timing shown in FIG. Here, the horizontal synchronization signal 1 (sync) and the clock signal CKA are generated by the clock generator 28, and the R
, G, and B flow serially in synchronization with the clock signal CKA (in the figure, the numbers of the image data are as follows:
Indicates the address in the main scanning direction. ). Horizontal synchronization signal Hsy
Every time nc occurs, line n in the main scanning direction is updated. That is, the scanner 10 has advanced by a unit distance in the sub-scanning direction.

FIG. 4 is a diagram showing the arrangement of various keys on the operation panel 70 provided on the top surface of the copying machine.

The operation panel 70 includes a print start key 71 for starting the copying operation and an interrupt key 7 for specifying interrupt copying.
2. Clear Stotubgie 73, All Reset Key 7
4. Numeric keypad 75 for setting numbers, set key 76, cancel key 77, various function keys 78 to 81, jog dials 82 and 83 for setting areas to be described later.
, a display section 84 consisting of a liquid crystal display, etc., which displays the original image for setting the area and also displays various messages.
is provided. Here, function keys 78,
79 and 80 are respectively used as a mosaic monitor selection key, a superimpose mode selection key, and a density correction key, as well as multi-value storage, binary (color) storage, binary (single color) storage, or It is used as a key for instructing selection, deletion, etc. of superimposed registered images.

The magnification ratio is set using the numeric keypad 75. You can also use image mode (
Settings such as multilevel storage superimpose mode, data deletion, and selection of registered images can also be made in response to messages on the display section 84.

Settings for the write area, continuous area, etc. in the superimpose mode and mosaic monitor mode, which will be explained later, are performed as follows. For example, in the case of setting the writing area, by placing the original on the platen I5 and performing a preliminary scan with the scanner IO, the original is displayed in the original area ED on the display section 84 of the operation panel 70, as shown in FIG. The image is displayed roughly. The intersection of the vertical and horizontal direction lines LPY and LPX becomes the center of the writing area (shaded area) EA. When the jog dials 82 and 83 are operated, these indication lines move left and right or up and down, respectively, thereby defining the area EA, and by pressing the set key 76, that area is set as the writing area. Note that in this case, the size of the write area EA is given as a constant size in advance.

(1)) Superimpose function When Funkun Yonggi 79 is pressed on the operation panel 70, the superimpose mode is selected. In this mode, image data (referred to as registered image data) of a specified area (referred to as writing area) on the original is registered in memory in advance, and this registered image data is superimposed on a copy of another original and printed on the paper. Print at any position. In this superimpose function, the registered image memory circuit 1 is used to write and successively output registered image data.

The method of setting the writing area EA of the registered image has already been described with reference to FIG. The write area EA has a size of, for example, 2cx square, and the storage capacity of the registered image memory circuit 1 is set equal to the storage capacity required for multivalued registered image data.

The CPU 25 can easily calculate the range of lines in which the writing area EA is located as seen from the leading edge of the image and the range of pixels in the main scanning direction. Data (writing area setting signal) regarding the positions (coordinates (xo, yo) of the upper left corner and coordinates (x+, y+) of the lower right corner) are sent to the registered image memory circuit l.

When the same document is scanned again, the registered image memory circuit 1 stores the image data of the writing area EA in the memory.

Next, when another document to be copied is placed on the platen 15 and a preliminary scan is performed using the scanner IO, the document image ED and the instruction line are displayed on the display section 84 of the operation panel 70, as in the case of writing area setting. LPX and LPY are displayed. The intersection of these instruction lines LPX and LPY becomes the center of the superimpose area EB in which the registered image is printed. jog dial 8
2.83 to define the superimpose area at a desired position and press the set key 76 to set the superimpose area EB. The CPU 25 registers data (successive area setting signal) about the position of the superimposed area EB (coordinates of the upper left corner (X, , Y,) and coordinates of the lower right corner (X, , Y,)) in the registered image memory circuit l. send to

When the original is scanned again, the copied image of the original is printed except for the superimposed area EB (blank area), as shown in FIG. 6(a).

(“White” data is printed in area EB.) This printing process is repeated for up to four colors. The paper is transferred to the transfer drum 51
Keep it on top. Next, when you perform the copy operation again,
The image data in the memory is read out, and as shown in FIG. 6(b), the superimposed area EI3 on the same paper is
is printed on. (°White data is printed in areas other than area EB.) This printing process is repeated for up to 4 colors (in addition,
In this example, the superimposed image is enlarged.

). In this way, the image in the memory is written into the original image, as shown in FIG. 6(c).

If the registered image is a halftone image such as a photograph, R, G, H of the shading correction circuit 23 is used as the registered image data.
The output value (multi-value) is stored in the memory of the registered image memory circuit l.

However, if the registered image is a binary image such as a character, the output value (multivalue) of the shading correction circuit 23 is
By converting the data into M and C binary data and storing it, even if the same 8-jaw memory is used, a wider area of registered image data can be stored compared to the case where multi-value data is stored.

For example, if the output value of the shading correction circuit 23 is 8 hits, in the case of a binary image, a registered image that is substantially 8 times wider can be superimposed.

Therefore, the user is allowed to set binary storage or multi-value storage.

Note that if the magnification ratio of the original image and the memory image are the same, there is no need to take the above printing process, and the original image and the memory image can be output at the same time (Fig. 26, 5).
223-5228).

Further, if the position corresponding to the superimposed area of the document is set as a white background, the superimposed image may be written on the white background without prohibiting writing in the superimposed area.

The case where writing can be performed in one superimposed area has been described above. However, it is also possible to register from one or more writing areas and print in multiple superimposed areas, or by using an area discriminating circuit for writing or continuous printing as shown in FIG. 8, which will be explained later. Image memory circuit that registers the occurrence counter! The CPU25 is installed in parallel inside the
This becomes possible easily by setting a write area setting signal and a successive area setting signal for each of them.

(c) Mosaic Monitor A mosaic monitor is realized by a monitor image memory circuit 1 that stores an image of an area of interest, and an image tone setting circuit 2 that performs color adjustment in the printing process.

When the fun key 78 is pressed on the operation panel 70, the mosaic monitor mode is selected.

In the mosaic monitor mode, the user first looks at the pre-scanned document image displayed on the display section 84 of the operation panel 70 and selects the area of interest (for example, the shaded area EA in FIG. 5) where the user wants to make the most color adjustment. Set. Correspondingly, the registered image memory circuit 1 stores only the image data (multi-value) of the region in the next scan in accordance with the setting value of the region of interest. Note that the thickness of the region of interest (Q×υ) is determined in accordance with the storage capacity of the registered image memory circuit 1, as described above.

Next, the image tone setting circuit 2 (see section (e)) processes the image data I read out from the memory and converted into print colors by the masking processing circuit 24, and prints images of various tones on the same paper. Print data I'=k.

Generate r (i=c, m, y). FIG. 7 shows an example of an output formanode. In this example, -k (C-+, Co, (+), k (m-+, m
o, m+), k CY-+, Y.

+c
yy+) to output images with 3x9=27 types of tones to paper P. The coefficient co with 0 added here.

mo, y (+ represents the standard color adjustment coefficient for color adjustment,
Color adjustment coefficient with I' + * m + + Y +
and the color adjustment coefficient C-+ with -1 attached. m-+, Y-+ are
The coefficients are larger and smaller than the standard color adjustment coefficients C6, mo, and Yo, respectively.

The user compares the various output images GM (referred to as mosaic monitor images) shown in FIG. 7 and selects the output image showing the optimum color tone on the display unit 84. This ends the mosaic monitor mode.

In the mosaic monitor mode, an image (color tone) selected from the mosaic monitor images GM displayed on the display section 84
In order for the user to specify, for example, the function keys 78 to 8
Press function key 7 according to the message displayed on
8 to 81 may be operated. Alternatively, the image block shown in FIG. 7 may be displayed on the display unit 84, and the color tone may be selected by specifying the block coordinates using the function keys or numeric keys.

Next, the document is read again and the image is printed in the set color tone.

Note that both the superimpose function and mosaic monitor function described above require memory for image registration, and
There are many common parts in the circuits related to memory access and writing. Therefore, in this embodiment, both functions are realized by sharing the registered image memory circuit l.

Downstream margin (d) Registered image memory circuit <d-1> Circuit configuration Registered image memory circuit 1 stores the registered image of EA in the specified area of the document in superimpose mode (the area of interest in the document in mosaic monitor mode). Register at
Any specified position on the paper for copying (superimpose area EB, output in mosaic monitor mode) (
--This is a circuit that reads out the print area defined by the mat (Fig. 7).

FIG. 8 shows a circuit diagram of the registered image memory circuit (2). Here, the memories 401a, 40lb, and 401c (hereinafter collectively referred to as memories 40+) are RAMs that record registered images, respectively. Each memory has the same address and write/read timing.
selected by the control signal.

Note that in the case of binary storage, which will be explained later, when writing image data, it is necessary to write in accordance with the print color. Therefore, the CPU 25 is designed to be able to select the memory to be written to using the CS control signal. In the case of multi-value storage, the control signal is set to 'ooo'.

The registered image memory circuit 1 is used in superimpose mode and mosaic monitor mode, and even in superimpose mode, there are multi-value color storage, binary color storage, monochrome binary storage, etc. In each case, memory 401
We need to change the way we access it. Therefore, data input from the shading correction circuit 23 to the memory 401 and data output from the memory 401 to the masking processing circuit 24 are controlled by various selectors 421, 426, 42744.
4,446.3 - Processed by state buffer 422, data selection circuit 442, etc. The selector 421 selects white data when successive signals in the superimpose mode have a large peak, and selects white data from the shading correction circuit 2 in other cases.
Select image data from 3. The output signal of selector 421 is sent to buffer 422 and selector 427.

The buffer 422 is 1. When the A N D gate 425 is at L level, it becomes active and sends the output of the selector 421 to the I10 terminal of the memory 401 . One input terminal of the AND gate 425 receives the 7-gate I/multi-value storage signal via the inverter 430, and the other input terminal receives the A
The output signal of the ND gate 405 is sent to the inverters 423 and 42.
It is input via 4.

Therefore, the buffer 422 is in a high impedance state when storing binary data and when it is in the successive region during successive data. In other words, the data is transmitted to the buffer 422 or the subsequent stage in the case of multilevel memory writing, and in this case, the memory
10I will be located. In the case of continuous multi-level storage, the buffer 422 is placed in a high impedance state to enable reading from the memory 401 hl, etc. On the other hand, in the case of binary storage, the image data is sent to the masking processing circuit 24 via the selector 427 with the buffer 422 in a high impedance state, and after being binarized in the halftone processing circuit 27, it is stored in the memory 401.

The selector 426 receives the output data (Hachijinriki) of the memory 401 and the white data (B input), the select signal of the selector 426 is supplied by an AND gate 428, and the selected signal is sent to the B input of the selector 427. A
The ND gate 428 outputs the signal when the output signal of the AND gate 405 is at L level via the inverter 423 (i.e.,
A signal for selecting the three-person horn (own data) is output only when the trimming control signal is at the L level (when the trimming control signal is in the readout area at the time of successive output) and the trimming control signal is at the L level. Therefore, when the multi-value storage is in the successive region, the read data (8-power) of the memory 401 is generally selected, but when the trimming control signal goes to L level, the white data (B input) is selected. Become.

The selector 127 receives the output signal of the selector 121 (
The output signal (B input) of the selector 426 is input manually, the select signal of the selector 427 is supplied by the AND gate 429, and the output signal of the selector 427 is sent to the masking circuit 24.

One input terminal of the AND gate 429 has 2 tia
/multilevel storage signal is sent via inverter 430, and the output signal of AND gate 405 is sent via inverter 423 to the other input terminal. Therefore, the B input is selected only when multi-value storage is used and the data is within the successive region at the time of successive data. In other words, in the case of binary storage, for example, the image data sent from the selector 421 is selected.

The selector 446 receives the output signal (
A select signal is supplied from an AND gate 448, and the selected signal is sent to the buffer memory 30.

A binary storage/multi-value storage signal is input to one input terminal of AND gate 448, and an output signal of AND gate 405 is outputted to the other input terminal via inverter 423.

The output of the selector 446h (P-8 conversion 2a 445 is selected when the output is binary storage and is within the successive region at the time of successive storage. In other cases, for example, in the case of multivalued storage, halftone processing is performed. The output signal of circuit 27 (8-power) is selected.

An S-P converter 441, a data selection circuit 442, a selector 444, and a P-S converter 445 are provided for binary storage.

As shown in FIG. 29, the data selection circuit 442
State buffer y501a, 50 lb, 501
c, 504a, 504b, 504c and gate 502.
It is composed of 503a, 503b, and 503c. 3
- State buffers 501a, 501b.

501c are AND gates 503a and 503, respectively.
b, 503c becomes active when 7J<L level, and transmits the input from the S-P converter 44 to the memory 401. A binary memory/multi-value memory signal is input to one input terminal of the AND gate 502, and an AND signal is input to the other input terminal.
The output signal of gate 405 is input. Furthermore, the output of the AND gate 502 is the output of the AND gates 503a and 503b.
, 503c. Therefore, in the case of multi-value storage or outside the successive region at the time of successive data, the buffers 501a, 50 lb, and 501c are in a high impedance state. That is, the 3-state buffers 501a, 501b, and 501c are activated only when writing binary memory. A, ND gates 503a, 503
The memory 401a is connected to the other input terminal of b503c.

Positive control signals corresponding to 401b and 401c are input. Also, this CS control signal is 3
- State buffer y 504a, 504b.

504c, and when the CS control signal is at L level (“0”), the 3-state buffer y
504a, 504b, and 504c transmit the output of the memory 401 to the selector 444.

The selector 444 selects the output signal of the memory 401 (by hand)
and select white data (8 man power). AND gate 114
7 is a selector 444 corresponding to the σW control signal.
sends a select signal to Therefore, in binary monochrome memory etc., τ
No) Control signal! When the memory 401a, 4.01b, 401c is selected, the selector 444 selects the white data, and otherwise selects the output of the memory 401.

An SP converter 441 that converts serial data into parallel data converts the signal binarized by the halftone processing circuit 27 into data of the number of bits to be stored in the memory 40.1 when writing binary storage. The data is converted and output to the data selection circuit 442.

The P-S converter 445 that converts parallel data into serial data converts the parallel data (successive data in the memory 40+) sent from the selector 444 when reading the binary memory.
is converted into serial data and sent to the selector 446.

S-P conversion and P- in writing and continuous writing in binary memory
Since it is necessary to perform 8 conversions, different clocks are required for other parts. That is, the binary signal flows in the S-P converter 44+ and the P-S converter 445 in synchronization with the clock CKA, or the parallel-converted image data cannot be processed using this clock. Therefore, the selector 451 selects the signal CKB obtained by dividing the clock CKΔ by the number of bits to be parallelized by the frequency divider 452 to perform image transfer and address management for the memory 401. 1st
Figure 0 shows the clock CKA in binary storage mode,
The relationship between CKB, a binary signal, and a parallelized signal is shown (in the case of the number of bits of the multilevel signal - 8). Note that in the superimpose mode and mosaic monitor mode in multilevel storage, the memory 401 must be handled by the clock CKA as before. Therefore, 2
Selector 4 that uses a value storage/multi-value storage signal as a selection signal
51, and in these modes (multi-value storage), C
It is made to be KB-CKA.

Next, writing and reading data to and from the memory 401 will be explained. (The circuit configurations of the write area t'JI separate circuit 402, write address generation counter 403, read area discrimination circuit 408, and read at 1 nos generation counter 409 will be explained in detail later (FIG. 12) 6) When the writing area determination circuit 402 receives the image leading edge signal during scanning for document reading, it counts the clock CKB and the horizontal synchronization signal Hsync, and sends the CPU 25
Based on the write area setting signal set in advance, the determination signals WEX and WEY are generated when it is determined that the write area is within the write area in the main scanning direction (X) and the single scanning direction (Y), respectively. The discrimination signals WEX and WEY are provided by AND gate 4.
07, and the write address generation counter 40
He will appear in 3rd. In the AND gate 407, when the data in the memory 401 is to be held, the CPU 25
-(level) is input, and the clock CKB is input via the inverter 406. Therefore, the AND gate 407 outputs the write area (WEX =WEY='
L') CKB (CKA in multi-level memory)
is output to the WE line terminal of the memory 401, making the memo 401 writable. The write address generation counter 403 is
At the time of writing, the clock C is set when within the writing area in the main scanning direction.
KB, and when it is within the write area in the sub-scanning direction, count the horizontal synchronization signal Hsync, and
Find the Fg, mark, and Y coordinates, and calculate the one-dimensional write address from both coordinate values. Furthermore, a fixed offset amount set by the CPU 25 as the start address for writing to the memory is added. The write address thus obtained is output to the selector 404.

Similarly to the write area determination circuit 402, the read area determination circuit 408, based on the continuous area setting signal set by the CPU 25, determines whether the continuous area is within the continuous area in the main scanning direction (X) or the sub-scanning direction (Y). Generates discrimination signals flEX and flEY. Both discrimination signals REXREY are connected to the AND gate 40.
5 and is also sent to the successive address generation counter 409. The AND gate 405 is further inputted with a 1-factor/readout signal set by the CPU 25 . Therefore, in the case of reading, the AND gate 405 outputs the I] level to the selector 404 in the successive region, and outputs the L level to the σ■ terminal of the memory 401 via the inverter 423. This allows the memory 401 to be used continuously. Similarly to the write address generation counter 403, the successive address generation counter 409 generates a one-dimensional read address and sends it to the selector 404. The selector 404 selects the read address when the output signal of the AND gate 405 is at level T, and selects the write address in other cases. The output terminal of the selector noctor 404 is connected to the address terminal of the memory 401 Therefore, the memory 401 is
When writing, it is accessed using the write address, and when writing successively, it is accessed using the successive address. Note that the successive address generation counter 40
9 allows magnification to be changed using a sub-scanning clock, as will be explained later. Further, in order to change the color adjustment in the mosaic monitor mode, overflow signals X and Y are generated and sent to the image tone setting circuit 2 at the subsequent stage.

Note that the superimpose read signal is a signal that becomes L' during reading in the superimpose mode and mosaic monitor mode, and is used to cause the selector 421 to select white data. In addition, the trimming control signal is a signal that turns white when you want to print white in the continuous area.
The selector 426 is caused to select white data.

<d-2> Superimpose mode that stores multi-values The superimpose function can be achieved by providing a memory after halftone processing, but in that case, the data has already been converted to a binary print signal. Therefore, it is not possible to adjust the color of the registered image later. In particular, when the registered image is a full-color image, color adjustment is often required.

Furthermore, if scaling is applied after binarization processing, the image deteriorates significantly. Therefore, in this embodiment, when the CPU 25 specifies multi-value storage by setting the binary storage/multi-value storage ↑a signal to I level, when writing, the selector 421, 3-state sets the read signal to L level. In a circuit consisting of a buffer 422 and a data selection circuit 442, the buffer 422 is activated and the buffer 50 in the data selection circuit 442 is activated.
By putting 1a, 501b, and 501C in a high impedance state, the memory 40 is placed before the halftone processing circuit 27.
! to store R, G, and B multi-value data in the memory 401.
to be memorized. (The color adjustment in the superimpose mode will be explained later in relation to the image setting circuit 2.) At this time, the superimpose mode read signal is at L level, and the selector 421 selects the image data. are doing. Also, the control signal (2) is "000".

When writing a registered image, when the user specifies a writing area, the CPU 25 determines how many lines this area covers from the leading edge of the image (in the sub-scanning direction), and also what about the main scanning direction (X direction). A writing area determination circuit (see FIG. 12 for details) 402 calculates whether it is within the range of the pixel, and uses the coordinates of the upper left corner and the upper right corner of this area as writing area setting signals in the X direction and Y direction. X part 402a and 7 part 4
02b respectively. X and Y refer to the main scanning direction and the sub-scanning direction, respectively. When the image leading edge signal is input, the X section 402a and the 7 section 402b of the writing area determination circuit 402 count the horizontal synchronizing signal Hsync and the clock CKB, and check whether the count value is within the above writing area setting range. Compare how. If it is within the range in the main scanning direction, WEX=L" is output, and if it is within the range in the sub-scanning direction, WEY='L' is output.

Write address generation counter (see Figure 12 for details) 40
3 generates a write address when the write area determination circuit 402 determines that it is a write area, and sends it to the address terminals of the memories 401a, 401b and 401c via the selector 404. In other words, the X section 4 of the write address generation counter
In 03a, when W, EX-'L', the clock CKB is counted and an address related to the main scanning direction is generated.

Note that this address is cleared by the horizontal synchronization signal Hsync.

In addition, the Y section 4031 of the write address generation counter 403
) counts the horizontal synchronizing signal Hsync when WEY='L' and generates an address in the sub-scanning direction.

Note that this atto Inos is cleared by the image leading edge signal generated by the CPU 25. From both addresses in the main scanning direction and sub-scanning direction and fixed offset amount! A write address for the dimension is generated.

In this way, a write address is generated and the memory 401a
40 [b When writing image data to 401c,
Furthermore, the data holding signal is ■7°, and the π/reading signal is °L.
It is set as . As a result, the selector 4f)4 receives a selection signal from the AND gate 405, selects the address signal from the write address generation counter 403, and transmits it to the address terminals of the memories 40Ia, 401b, and 40Ic.

Further, the clock CKB is transmitted to the WE terminals of the memories 401a, 40lb, and 401c via the inverter 406 and the AND gate 407, thereby enabling writing to the memories. On the other hand, since the superimpose successive signal from the CPtJ 25 is set to °L'' except in the case of successive output in the superimpose mode and mosaic monitor mode, the selector 421 selects and outputs image data. In addition, since the read/read signal is set to L, in the case of multi-value storage (i-1-/multi-value storage signal from CPtJ25 = 'II'), the 3-state buffer 422
becomes active via the AND gate 425 only when it is possible to write the original image, and stores the image data in the memory 4.
Transmit this to the I10 terminals of 01a, 40 lb, and 401c.

This allows the memory 401 to store only the image of the area that the writing area determination circuit 402 has determined is within the range in both the main scanning direction and the sub-scanning direction. When the writing is completed, the CPU 25 sets the data holding signal to H° and inhibits writing via the AND gate 407 l1,
The contents of memory 401 are held.

When reading the data stored in the memory 401, it is necessary to read the data so as to print it in a designated successive area (superimpose area).

The circuit configuration required for reading is almost the same as that for writing. As with writing, the control signal is set to 000゛.

Below, the margin CPU 25 uses the
Setting values (X coordinates and Y coordinates) that can be determined to be within the readout area range in the main scanning direction and the sub-scanning direction are respectively given. When the image leading edge signal is inputted manually during scanning, the successive area determination circuits 408a and 408b output the horizontal synchronization signal Hs.
Along with counting ync and clock CKB,
A comparison is made to see if the count value is within the above continuous area setting range. If the main scanning direction is within the range, output IIEX-, and if the sub-scanning direction is within the range, output Y='L'.
Output.

The continuation address generation counter 409 generates a continuation address when the read area determination circuit 408 determines that the readout area is a continuation area, and this address is sent to the memory 401a via the selector 404 since the 1st cause/continuation signal is H at the time of continuation. ,
40 lb, sent to the address terminal of 401c. That is, the X section 409a of the successive address generation counter is r
(When EX='L', the clock CKB is counted and an address related to the main scanning direction is generated. This address is cleared by the horizontal synchronization signal Hsync. Also,
The seventh part 409b of the successive address generation counter is nEY='
When L', the sub-scanning clock from the variable-magnification sub-scanning clock generator 29 (FIG. 2) is counted to generate an address in the sub-scanning direction. The reason why the sub-scanning clock is counted instead of the horizontal synchronization signal Hsync is to take magnification into consideration. Note that this address is cleared by the image leading edge signal generated by the CPU 25. A one-dimensional successive address is generated from both addresses and a fixed offset m. Data read out by accessing the memory 401 is transmitted to the subsequent stage.

Flowcharts of image registration and succession in this mode are shown in FIGS. 20 and 23.

<d-3> Variable scaling When performing a superimpose function using multi-level storage, variable scaling is possible. When changing the magnification, you may want to change the sound of the superimposed image to match the magnification, or you may want to change the sound of the superimposed image to match the magnification, or you may want to change the sound of the superimposed image to match the magnification. There are times when you want to do it. Either case can be handled by controlling the sub-scanning clock generator 29 for variable magnification by the CPU 25 to change the sub-scanning clock for variable magnification (see FIG. 26). That is, when scaling the superimposed image, a scanning clock for scaling is supplied to the successive address generation counter 409, and when scaling the document read data, a sub-scanning clock for scaling is supplied to the electric scaling circuit 26. supply. In this embodiment, if the magnification ratio of the superimposed image and the magnification ratio of the original image are the same, both images can be printed at the same time.

<d-4> Image data of the area of interest in the mosaic monitor mode and the continuous flow in the mosaic monitor mode (
Writing of multivalued data is performed in the same way. In this case, the CPU
25 calculates a write area setting signal from the coordinates of the area of interest and outputs it.

On the other hand, when printing a mosaic monitor image in the mosaic monitor mode, the memories 401a, 401b, 401c
It is necessary to read out the data based on the data written in it so that it can be printed in the format shown in FIG. In this case, in order to make the image data "white" except when data is continuously output from the memory 401, the superimpose succession signal is set to "H", and the selector 421 selects "white" data. When the selector 426 reads the image data on the document, it does not read the contents of the memory 401 and the trimming control signal is at the "H" level in the continuous area, so that "white data" does not flow to the subsequent stage. .

At this time, the X portion 408a, the Y portion
The unit 408b includes a magnification MAGA for reading the manuscript and a memory 40.
The coordinates are set in consideration of the difference from the print magnification MAGB of the contents of 1. Note that the sub-scanning clock for scaling is made to match the original reading sound rate MAGA.

Now, taking Figure 7 as an example, if you want to output a mosaic monitor image of 3 x 9 blocks, the way to read the memory is to use the overflow signal When all the contents in the direction are read out, the main scanning direction is read out again from the first line.

At the time of successive address, the 1/read signal is H', the selector 404 selects the successive address, and the memory 40
1a, 401b and 401c are read areas and are ready for output. Furthermore, the buffer 422 is in a high impedance state. Here, the CPU 25 selects the successive area discriminating circuit X section 4 in accordance with the output format (see FIG. 7).
08a, when Xo≦X≦x1, the open circuit Y portion 40
8b is given a setting value that allows it to be determined that when Yo≦y≦y1, it is within the successive range. X section 408a of the successive area determination circuit 408 that determines the reading area for the paper
, when the output REX of the Y section 408b is at the L level, the X section 409 of the read address generation counter 409
A, 7 part 409b generates successive addresses, and the memories 401a, 40 lb, 40 use the successive addresses.
1c and transmits the stored image data to the subsequent stage via selectors 126 and 127. At this time,
Naturally, the successive address generation counter 409 is requested to count even if it passes one block in the main scanning direction and exceeds the maximum size if it is within the successive area, but the successive address generation counter 409 receives overflow signals X and Y. is output to the picture setting circuit 2 arranged in the subsequent stage, and
For the next block, we will start counting again from the initial value. Overflow signal X.

Y is used when a plurality of images are arranged in the horizontal direction and the sub-scanning direction and printed with different color tones in the mosaic monitor mode. In the image U1M setting circuit 2, which will be described later, different color adjustment coefficients are set depending on the overflow signals X and Y.
Since km and kc are set by the CPU 25, each image is printed in its original color. In this way, three images are printed horizontally,
By repeating this nine times, a 3×9 mosaic monitor image is printed.

<d-5> Superimpose mode for storing in binary (color) There are times when you want to memorize or write in a large area even if you don't have one. Therefore, in this embodiment, in the case of binary storage, the CPU 25 sets the multi-value storage signal to the L level, so that the memory blocks 401a to 401c can be inserted after halftone processing. In the case of binary storage, as explained below, the binary image data after the binarization process is stored in the memory 4.
Stored in 01. As a result, if the multilevel signal is 8 bits, for example, binary data of 8 times the area can be stored.

In the case of write storage, the buffer 422
becomes a high impedance state, and the data selection circuit 44
The buffers 501a, 501b, 501c in 2 become active and the memory 401 is disconnected from the previous stage of the masking process. On the other hand, the selector 427 selects input A. In the case of writing, the superimpose successive signal is H
”, so the selector 421 selects the image data. Therefore, the image data is sent to the subsequent stage via the selectors 421 and 427, and passes through the circuits 24, 2, 26, and 27 to the 2(
Directed. On the other hand, on the rear side of the halftone processing circuit 27, 2
The converted signal is transmitted to the memory 401 as parallel data converted by the S-P converter /+41 via the 3-state buffers y501a 501b 50Ic in the data selection circuit 442.

Here, since the image signal is a signal that has passed through the halftone processing circuit 27, the signal that can drive the semiconductor laser 33,
That is, it is a binary signal of 0N10FF (I pip). Therefore, a Noria-to-parallel converter 441 is placed before the memory/101, converts the data into data for each bit number (8 bits) in the multi-value state before binarization, and converts the data into data for each number of bits (8 bits) in the memory 401a, 40lb, 401c.
/ 0911 I am trying to convey this to my child. Furthermore, in the case of successive outputs, the parallel-to-norial converter 445
Reconvert to bit data and output.

Since signals stored in binary format cannot be scaled, the sub-scanning clock for scaling is set to equal magnification in binary storage.

Write area determination circuit 402 and write address generation counter 4
Regarding the operation of 03, there is no difference from that in multi-level storage except that the clock CKA is frequency-divided, so a description thereof will be omitted.

In the case of continuous output, the 3-state buffer 422 and the 3-state buffer y in the data selection circuit 42 are
501a, 50 lb, and 501c are in a high impedance state, and the data in the memory 401 is transferred to the data selection circuit 442 activated by the CS control signal.
3-state buffer 504a, 504b or 5 in
04c, selector 444, r'-8 converter 445
, and is sent to the buffer memory 30 via the selector 446. Outside the continuous area, the data passes through selectors 421 and 427.
White data is sent from selector 446.

Now, as mentioned earlier, the system we are currently targeting is one that prints in surface order. Therefore, the signal output from the halftone processing circuit 27 is a Y, M, or C print signal. As a result, in order to store a color image using binary storage, the same steps as in the printing process are required.
You have to scan the same area multiple times.

At this time, as a matter of course, the memory capacity may be smaller than that of multilevel storage, so the memory 401 is divided and written/written.
Reading is preferred for storing many images. Therefore, in this embodiment, the memories 401a, 401b, which are multi-valued and write/read data for three colors in parallel,
401c can be handled separately. When writing the contents of the memory, it is necessary to match the print color.

For example, Y, M, and C images are each stored in memory 4018401.
If the information is stored in the memory 401a and 401b, then in the process of actually performing superimposition, the memory 401a must be taken care of such that the memory 401a is not read during Y printing. Therefore, the CPU 25 specifies the successive memory using the CS control signal. in particular,
The CPU 25 should manage the fang control signal so that the memory 401a is selected for the Y signal, the memory 401b is selected for the M signal, and the memory 401c is selected for the C signal (see the flowchart in FIG. 27). reference).

Note that if multiple images are registered, the address (fixed offset ff1) is set so that the selected image is not read.
(See 8205 in FIG. 25).

If there is no need to change the magnification or change the color hli after registration, it may be possible to automatically select storage in binary format.

Flowcharts of image registration and readout in this mode are shown in FIGS. 20 and 27.

<d-6> Superimpose mode that stores in single color (2 (direct)) Up until now, the explanation has been based on the assumption that a color image is used for superimposition, but depending on the application, the image to which you want to superimpose may be used. For example, there are cases where only one printing color is printed, such as one color of black.Of course, if multiple values are stored, it is easy to perform appropriate color correction and convert to a single color such as one color of black. .

However, in this embodiment, a binary signal is written into the memory 40I in the same way as in the case of binary storage of a full-color image. Writing and successive output of binary signals are performed in almost the same way as in the case of multicolor binary storage, but there are some differences.

When using binary storage, the image is binarized after appropriate color correction is stored, so in order to store a full color image, 401a, 401b, 401
It required memory for 3 sides of c, whereas for single color only 1
Only the face portion is required.

Therefore, when storing a single color, it is possible to store not only one image but M (for example, three) images. The CPU 25 specifies the memory using the Uq control signal for writing and reading, and
Outputs fixed offset amount and write (successive) area setting signals. In this case, for example, even within the area where the memory image is printed, it is necessary to read the memory for Y printing, and not to print anything for M printing. In order to realize this operation, as mentioned above, the selector 444 is provided so that all three bits of the CS control signal are
In the case of B, the selector 444 selects the white data on the B input side and prohibits printing. Note that the sub-scanning clock for scaling is set to equal magnification.

The flow of image registration and readout in this mode is explained in the 21st section.
As shown in FIG.

<d-7> Mixture of multivalued storage and binary storage It is also possible to mix multi-value storage and binary storage.

In the present invention, addresses in the main and sub-scanning directions are converted into one-dimensional addresses for accessing the memory, as will be explained later. When registering the image, the CPU 25 may set the address (fixed offset) in consideration of the free space of the memory 401 (S27, 528 in FIG. 18). However, 2
Some consideration is required when monochrome mode and full color (multi-value and binary) mode of value storage are mixed.

1st! As shown in the figure, for full-color images, regardless of whether they are multivalued or binary, the beginning of the address (each memory 401a,
40lb and 401c). On the other hand, for a monochromatic binary image, a fixed offset of the write address is calculated and registered so that the rear end of the registered image data is located at the highest address (LA). that time,
In order to prevent the start address of the registered image data of each single-color binary image from becoming as small as possible, registration is performed while taking care to ensure that each single-color binary data is stored evenly in the memories 401a, 40 lb, and 401c. Proceed. This is because, for example, if single-color binary images are intensively registered in the memory 401a, the area in which full-color (multi-valued, binary) images can be registered will rapidly decrease.

In the example shown in FIG. 11, the monochrome binary image 1 and the image 2 are stored in the memory 401a instead of being stored in the memory 401a.
01b starting from the highest address LA.

<d-8> Area discrimination circuit and address generation counter Next, the 12th section regarding the write (read) area discrimination circuit 402 (408) and the address generation counter 403 (409) that constitute the registered image memory circuit 1. This will be explained using the detailed circuit diagram shown in the figure. Note that the area discrimination circuit and address generation counter with the same configuration are used for writing and reading, and the difference between the two is that in the case of continuous writing, a sub-scanning clock for scaling is used and overflow signals X and Y are output. Only.

In FIG. 12, X of the writing area (successive area) discrimination circuit
The section 402a (408a) is a counter circuit 601°602
, D-flip-flops 603, 604, and AND gate 605 (1).

The preset terminals of the counter circuits 601 and 602, which are down counters, are provided with initial value data Xo for setting the values of the X coordinates of the upper left corner and lower right corner of the write area (read area).
-1, X, -1 are sent from the CPU 25, and a horizontal synchronization signal 1-1sync is sent to the 1oad terminal.

Therefore, when the horizontal synchronization signal l-1sync is output,
Initial value data X for counter circuits 601 and 602, respectively
. -1, x+l is preset. Here, XO
, XI are the XIfi standard values of the upper left corner and the lower right corner of the rectangular writing (continuation) area. Both counter circuits 601.6
A clock signal CKB is input to the clock terminal 02. Therefore, each time the clock signal CKB is input, the counter circuits 601 to 602 decrease the count value by one, and when the count value exceeds 0, the ripple c
Generates an arry signal. This ripple carr
The y signals are sent to D-flip-flops 603 and 6, respectively.
04 as a clock signal. In both flip-flops 603 and 604, the same horizontal synchronizing signal I (sync) is input manually to each CLR terminal, but the L level and H level are respectively input to the D terminal. The Q output of 03 is the horizontal synchronization signal Hsy
At the forward edge of nc, it becomes [-f level, and after counting xopl clock, ripple carry
It is inverted to L level at the forward edge of the signal. On the other hand, D-
The Q output of the flip-flop 604 is the horizontal synchronization signal 1r.
It goes to L level at the forward going edge of sync, and after counting the xJJ clock, becomes 1 level at the forward going edge of the ripple carry signal. The Q output of flip-flop 603 and the Q output of flip-flop 6011 are each sent to an input terminal of A N D gate 605 .

Therefore, the output terminal of AND gate 605 is the count
. It becomes L level between and Xl.

FIG. 13 in the margin below shows a time chart of the operation of the area discriminating circuit. The counter circuit 601 starts counting using the initial data X0-1' given by the CPU 25 as an initial value, and decrements the count value every time the clock CKB is input. Then, when the clock CKB is manually inputted by xo, the counter circuit 601 generates a ripple carry.
Generate a signal. When this signal is input, flip-flop 603, which has been previously set to H, inverts its Q output and transmits the L level to AND gate 605. Similarly, when the counter circuit 602 is manually inputted with the initial data X1-bi as the initial value and the clock GK+3, the Q output of the flip-flop 604 changes to °L.
From ° to 'I-1'i, m anti-ten is transmitted to the 'I+' level AND gate 605. (Note that the Q output and Q output of the flip-flops 603 and 604 are respectively 1 (° level, °L° level) when cleared.) Now,
If o<L, then X is a writing area (continuation area). and X
, the output of the gate 605 (WEX(nEX)
) becomes L°.

The X section 403a (409a) of the write (read) address generation counter 403 (409) consists of an AND gate 606 and a programmable counter 607.

The output signal of AND gate 606 is sent to programmable counter 607 as a clock signal.

Therefore, when the output signal (WEX) of AND gate 605 is at the "L" level, AND gate 606 transmits another input CKB to programmable counter 607. The programmable counter 607 cyclically counts the clock CKB using the program data X given from the CPU 25 as a divisor.

Now, the length of the registered image in the main scanning direction is determined by the Q of the clock CKB.
In the case of counting, data X given by the CPU 25 when written to the memory ICI. , Xl
, X, you can set -X, ``Q'' to xo)/ll=ρ.In the case of binary storage, X = (x,
-x, )/8 n=c/8.

7 parts 402b (408b) of the write (continuous) area determination circuit
are counter circuits 611, 612, flip-flop 6
13, 614, and an AND gate 6I5. In addition, the seventh section 403b of the write (read) address generation counter
(409b) consists of an AND gate 616 and a programmable counter 617.

Its configuration and operation are exactly the same as those in the main scanning direction using the X section 402a (4Q 8a) of the write (successive) area discrimination circuit and the X section 403a (409a) of the write (successive) address generation counter. . However, counter circuit 6
The initial value data given by the CPU 25 to 11,612 is Y
o -1, Y+ -1, and in the AND gate 616, the clock CKB is replaced by l-1sync or the sub-scanning clock for variable magnification, so that the X direction is different = 1
Using the scanning (X direction) signal, the counter circuit 61
CLf of 1,612 rotor terminals, flip-flops, etc.
Let the l1sync signal input to the l terminal be the image leading edge signal, and the program data given to the programmable counter 617 be Y=Q. In addition, programmable counter 6
07617 generate overflow signals X and Y, respectively.

The values obtained as the count values of the programmable counters 607 to 617 can be used as they are as addresses in the memory 401. For example, program data
If is a power of 2, it is sufficient to set the lower bit as the output of the programmable counter 607 and the upper bit as the output of the programmable counter 617. However, if this is not the case, using the above method will reduce memory usage efficiency.

Therefore, in this embodiment, in order to increase memory usage efficiency, addresses in the main and sub-scanning directions are converted into one-dimensional continuous memory addresses. No matter what the aspect ratio of the obtained area is, if the area is within the total memory capacity (YES at 326 in FIG. 18), writing and reading can be performed. As a specific method,
Write (continuous) address generation counter 403 (409)
, the X section 403a (409a) and the 7 section 403b (
In addition to 409b), a multiplication table 621 is provided that searches the program data X and the output data of the programmable counter 607 as addresses, and a fixed offset m (S27 in FIG.
) That is, the memory start address and programmable counter 6
By adding the output of 07 and the output of the multiplication table in an adder 622, the real address of the memory 40+ is calculated. Thus, whatever the value of
1, image data can be stored one-dimensionally with close-packed backing.

Further, as is clear from the above description, there are a write-related area determination circuit 402, an address generation counter 103, a read-related area determination circuit 408, and an address generation counter 409.
have exactly the same circuit configuration except for the sub-scanning clock. Up until now, to simplify the explanation, these circuits have been separated and addresses have been selected by the selector 404 at the time of writing and at the time of continuous output, but since writing and continuous output are not performed at the same time,
This circuit is common and only one need be provided.

<d-9> The adder 622 uses a CPU
A fixed offset a from 25 is given. This gives the start address of the next image to be registered, and allows a new image to be registered without deleting the previously registered image. For example, as shown in FIG. 14, if the required capacity of the registered images is m, the images can be registered one after another with the fixed offset amounts a and 2m. The same applies when the required capacity of the registered image is n. In the following, we have shown the case where each σ-recorded image has the same capacity, but if registered image 1 requires fv1 address and registered image 2 requires N addresses, then
As shown in FIG. 15, a new image may be registered with MIN as a fixed offset amount.

The CPU 25 stores the fixed offset amount and program data XY regarding the registered image at the time of image registration, and can read out any registered image by setting these values according to the user's selection. Yes (second
(See Figure 5). It is also possible to read out a plurality of registered images.

Note that if a plurality of area discrimination circuits and address generation counters as described above are provided in parallel, images of a number of stages can be selected from among the images registered in the memory 401, and a plurality of one image on the paper can be selected.
Can be synthesized in thousands of positions.

(c) Picture setting circuit FIG. 16 is a circuit diagram of the image tone setting circuit 2.

The picture setting circuit 2 performs color correction (
This is a circuit that performs color adjustment).

A masking processing circuit 24 located before the picture setting circuit 2 extracts Y (yellow), M (magenta), C (cyan), and K (black) from the image signals of three colors B, G, and R. Image signals for printing corresponding to each print color (
A print signal) is generated in accordance with the characteristics of the toner in the developing devices 45a to 15d.

Generally, from the original image signals B, G, R to the print signals YM, C
The conversion formula for converting to is expressed as follows.

Each conversion coefficient a. Q'=822 is preset to an appropriate value based on theory and experiment so that an image with a color as close as possible to the original image is printed.

The color adjustment in the image tone setting circuit 2 is performed using the following equations for each print signal Y, M, and C output by the masking processing circuit 24 obtained by the above-mentioned calculation: Y=, XY Ml = k, XM CI=, The purpose is to calculate XC and obtain adjusted print signals y, , M, , c. Here, k, , k, ko are the color adjustment coefficients mentioned above.

In the format of the mosaic monitor image GM shown in FIG. 7, the Y (yellow) color adjustment body \Ik does not change in the sub-scanning direction, but y-+, yo in the main-scanning direction.

The color adjustment coefficient k of M (magenta) is
It does not change in the main scanning direction, but for each block in the sub-scanning direction "-1+ 1llo, a+,, ff1-+, rI
l. -, and the coefficient of C (cyan) does not change in the main scanning direction, but every 3 blocks in the sub-scanning direction, "-l"
+eo+01.

Therefore, in the image tone setting circuit 2, each print signal Y.

As described above, the color adjustment coefficients for M and C can be changed sequentially for each block of the mosaic monitor image.

Now, the image tone setting circuit 2 shown in FIG. 15 executes calculations to obtain the above-mentioned print signals Y, , M, , C. The image tone setting circuit 2 includes a first latch 302 . to set three different coefficients for three blocks in the main scanning direction.
Second latch 303. A latch circuit 305 consisting of a third latch 304 is provided, and these latches 302 to 3
04 is set to a coefficient output from the CPU 25.

Latch circuit 305 consisting of three latches 302 to 304
The reason why is provided is that the coefficient change cycle is short in the main scanning direction, and it is difficult to set it in real time by the CPU 25 in terms of speed. Note that if it is desired to have n types of coefficients, n latches may be provided in parallel.

In the mosaic monitor mode, the selector 306 selects the coefficients output by the latches 302, 303, and 304 from the selector 3.
Select according to the signal S2+ sent via 12,
Output to multiplier 301. Multiplication R330+ is the image data (Y2M, C) sent from the masking processing circuit 24.
The obtained print signal (Yl, lVL, C
+) is output to the electric magnification circuit 26.

The manual setting of each latch 302-304 is given a color adjustment coefficient for the following three blocks.

Every time the sub-scanning clock for magnification change is manually input to the CPU 25 as an interrupt signal, an interrupt process (see FIG. 24) is performed.
(a) and (b) are performed, and the overflow signal Y is sent as a latch signal to the latch circuit 405 via the selector 313, and the color adjustment coefficient is set.

Furthermore, selection of coefficients to be set in the multiplier 301 will be explained. The overflow signal X in the main scanning direction generated when reading the image memories ll 01a, 40 lb, and 401c in the registered image memory circuit 1 described above is input to the first selection signal generation circuit 3+1, and the first selection signal generation circuit 311 , each time fi when overflow signal X is input
Then, the selector 306 outputs a signal for sequentially selectively switching the outputs of the latches 302 to 304. The selector 312 transmits the output S2+ of the first selection signal generation circuit 311 to the selector 306 in the mosaic monitor mode. Therefore, the selector 306 selectively sequentially sends each coefficient latched in the latch circuit 305 to the multiplier 301 block by block in response to the signal S21.

On the other hand, in the registered image memory circuit 1, the image memory 40
The overflow signal Y in the sub-scanning direction that occurs when reading Ia, 40 lb, and 401c is input to the selector 313, and in the mosaic monitor mode, the selector 313 uses this as a latch signal to output the latch circuit 30.
Tell 5. As a result, each time the overflow signal Y is output, the latches 302, 303, and 304 latch and update the input data (color adjustment coefficients). Therefore, when the block changes in the sub-scanning direction, the set of coefficients is immediately changed.

The above color adjustment is performed for each print color Y, M, and C.

Next, color adjustment in superimpose mode will be explained. In the superimpose mode, coefficients for document copying and coefficients for superimposed area are set in the outputs of the first latch 302 and the second latch 303, respectively, as initial settings. Then, in order to transmit this value to the output of the latch circuit 305, the selector 313
Select the latch signal that generates the signal. Further, the selector 312 selects the output of the second selection signal generation circuit 314. The second selection signal generation circuit 314 uses the memory 40! OE of
='+[', the selector 312 is set to the first latch 302
is selected, and a signal S21 is generated so that the selector 312 selects the second latch 303 when OE='L'. With such a circuit, in the superimpose mode, when printing successive original images, color adjustment is performed according to the value set in the first latch 302, and when reading out the image in the memory 401, the color adjustment is performed in accordance with the value set in the second latch 303. Color adjustment can be performed according to the set values. Of course, the values of the latches 302 and 303 must be reset for each print color.

Note that when the mode is neither the superimpose mode nor the mosaic monitor mode, the image data is not processed by the image tone setting circuit 2 and is immediately sent to the electric scaling circuit 26.

(r) Copying control flow Figure 17 shows the CP controlling σ11 for the digital color copying machine.
The main flow related to the superimpose function and mosaic monitor mode of copying operation control of U25 is shown. When the function key 78 or 79 is pressed on the operation panel 70 to enter the superimpose mode or the mosaic monitor mode, this main flow is entered.

If there is a request for image registration (YES in step Sl, hereinafter "step" will be omitted), image registration processing is performed (S2
, see Figure 18). Image registration means to register the contents of an image in a designated area.

In the image registration process (S2), the user sets a desired area and registers the contents of the area in the memory.

Normally, selecting the mosaic monitor mode means YES' for both the image registration request (Sl) and the mosaic monitor output request (S3). Furthermore, selecting the superimpose mode means YES' to both the image registration request (Sl) and the superimpose output request (S5).

If there is a mosaic monitor output request (YES in S3), mosaic monitor output processing (S4, see FIG. 22) is performed.

In other words, the registered contents are successively added, and various colors are added to them.
Apply i correction and output a mosaic image. Next, when the user selects an image with the desired color balance from among the output mosaic images and copies it, the entire image is obtained with that color balance.

In the case of superimpose output request (YES in S5),
Superimpose output settings are performed (S6, see FIG. 25). That is, after checking whether there are a plurality of registered images, settings for reading from the memory are performed. Next, when a copy request is made (YES in S7), copying is performed (S8.
S9), the registered image is printed superimposed on one original image.

If there is no image registration request, mosaic monitor output request, or superimpose output request (Sl, S3.S5
(No in both cases), perform normal copying (97-S9)
.

FIG. 18 shows phase a of the image registration process (S2).

When the set key 76 is pressed on the operation panel 70, the area setting value that was set on the display section 84 at that time is input (S21). Furthermore, various other human power values (magnification, binary values, etc.) are set (S22). Then, it is determined whether the image registration can be started (S2
3). If not, the process advances to S31, clears the image registration request, and returns.

When starting image registration (YES in S23), first, the coordinates of the vertices (upper left corner and lower right corner) of the registered image area are calculated from the area setting value (S2+) (S24). Next, the registered image mode is read (S25).

This registered image mode includes (a) superimpose mode with multilevel storage (color), (b) mosaic monitor mode, (c) superimpose mode with binary storage (color), and (d) 21gl storage ( There are four types of superimpose modes (single color).

Next, if it is determined that there is a necessary blank area in the memory 401 (YES in S26), a fixed offset amount for setting the memory address is set and stored (527), and the registered image is set according to the registered image mode. Set various data in the memory circuit 1 (S28, see FIGS. 19 to 21)
. Then, the image registration request is cleared (S31), and the process returns.

If the memory 401 does not have the necessary remaining capacity, it waits for the human power to decide whether to delete the previously registered image data, and if it wants to delete it (YES in S29), after performing the deletion (S30
), the process returns to S26. If you do not want to delete it (No in S29)
, the process directly advances to S31, clears the image registration request, and returns.

The following blank FIG. 19 shows the flow of registered image writing (S28) when the registered image mode is superimpose mode or mosaic monitor mode using multi-value storage (color). First, various control data are set in the registered image memory circuit l. That is, the write area setting signals X and Y are sent to the write area determination circuit 402 (S41) to specify multi-level storage (542), and the data retention signal is sent to the memory 401.
L° binding (S43), both the superimpose successive signal and the trimming control signal are set to H'544)
, 1Σ/Read signal is set to L°545), ■ Control signal is set to 000° and all memories 401a401b, 4
01c is selected (S46). Then, the document is scanned (S47), and the multivalued data of the image registration area (writing area) is stored in the memories 401a and 40 lb.

401c1. :Write. Then, the cS control signal is set to II to inhibit writing to the memory 401, the data holding signal is set to H' to hold the data in the memory 401 (848), and the process returns.

FIG. 20 shows the flow of registered image writing (328) when the registered image mode is a superimpose mode using binary storage (color). First, various control data are set in the registered image memory circuit 1. That is, the write area setting signals X and Y are sent to the write area determination circuit 402 and ζ56
1), specify binary storage 562), set the data retention P'f signal to L° for the memory 401 563), set both the superimpose successive signal and the trimming control signal to If' S 64), / Read signal L
(S65). Next, scanning is performed in each printing color of Y, M, and C, and the image data is stored. First, select the memory 401a by setting the U-cho control signal to 110 degrees (966), scan for yellow (Y), and store the image data in the writing area as binary data (966).
S67). Similarly, for magenta (M), memory 4
01b (568) and stores the binary data by scanning (S69). Furthermore, the memory 401c is selected for Noan (C) (570), and the binary data is stored (S71).Then, the cs control signal is set to 'Ill' to prohibit writing to the memory 401, Memory 401 with data retention signal as ■4°
572) and returns. In addition, S
If there is a registered image in steps 67, S69, and S71, a fixed offset amount is set so that it is stored in the free space (see S27 in FIG. 18 and FIG. 11).

FIG. 21 shows registered image writing (
The flow of S2B) is shown. First, various control data are set in the registered image memory circuit l. That is, the write area setting signals X and Y are sent to the write area determination circuit 402 (S8
1), specify binary storage 582), set the memory data retention signal to Lo 583), set both the superimpose read signal and trimming control signal to I4
584), as explained using Figure 11,
The memory is selected so that the storage capacity of the memory 40+ can be used most effectively, that is, the memory selection data is
10", "101" or Olbi Toshik S8"5), 1
The cause/read signal is set to L'' (S86).

Next, set the Cy control signal to A (587), specify the memory, and specify appropriate color correction (for example, characteristics that match the relative luminous efficiency) to the masking processing circuit 24.
88), scan is performed (S89). Then, write to the memory 401 is prohibited by setting the τ10) control signal to °I I 1', and setting the data holding signal to H' to inhibit writing to the memory 401.
1 data is retained (590) and returns.

FIG. 22 shows the flow of mosaic monitor output processing (S4). First, the registered image data stored in the memory 401 is read out (5IOI, see FIG. 23), and the color Nli
The mosaic monitor image is printed (S103).

Next, when the user selects the desired color balance (S104
), and set its color adjustment coefficient (S105).

Next, when there is a copy request (YES at S+06),
Start copying the original with the desired color balance 5107
), Y, M, and C are printed. Then, copy ends (S
Read memory contents in mosaic monitor output processing that waits for I OI3 (YES) and returns 5101
) is performed according to the flow shown in FIG. First, set various control data in the registered image memory circuit ■. That is, in response to the user's instructions, the area setting signal X,
Sends Y to the successive area determination circuit 408 (SI21), specifies multi-level storage (5I22), sends the data holding signal to the memory 401 (5I23), and sets the superimpose successive signal to L (5I24). , set the trimming control signal to H' 5I25), specify successive output 5I26), and set the same-size data in the sub-scanning clock generator 29 for variable magnification (S127).In addition, in the mosaic monitor mode, the registered image is 1 Therefore, the one-plane constant offset m is set to 0°.

Next, set the CS control signal to “000” (S1
28), select all memory, enable interrupt processing (S
I29), enable the interrupt processing routine for setting color adjustment coefficients (FIGS. 2.1 (a) and (b)), and scan Y, M, and C (S130). )
.

After the scan is completed, interrupt processing is prohibited.S l 3I
), the memory 401 uses the CS control signal as II
Disable writing to SI 32) and return.

Figures 24(a) and (b) show the color adjustment coefficients, k
,, is a flowchart for performing the setting process of ko.

This process is executed as an interrupt routine by interrupting the CPU 25 every time the horizontal synchronization signal Hsync is generated.

Among these, the counter CtI counts the distance from the leading edge of the image in the sub-scanning direction, and detects the beginning and end of printing of the mosaic monitor image GM. The counter C1t counts the distance in the sub-scanning direction and detects changes in blocks of the mosaic monitor image.

T represents the distance in the sub-scanning direction from the leading edge of the image to the print position of the mosaic monitor image, and e represents the distance in the sub-scanning direction of the l block (see Figure 7), image registration processing (S2)
is set.

The state is determined by the square 5300, and its value is "0" ~
Branch according to "4".

When the state is "0", it is determined whether or not it is the leading edge of the image (leading edge of paper P) (S301), and when the leading edge of the image has passed, the counter C (, is initialized).
2) Set the state to rN (S303).

When the state is rlJ, wait until the counter Ct+ becomes T (S311), that is, the coordinate y which is the tip of the mosaic monitor image GM. Wait until it reaches the position of
Thereafter, the process jumps to one of states r2JJ3JJ4J depending on the color of toner in the developing device used.

That is, when Y (yellow) (YES in S312)
sets the state to "2" (S313). When M (magenta) (YES in S321), initialize the counter CLt (S322) and set the variable i to "0"5323.
), the state is set to "3" (S324). When C (cyan) (No in S321), initialize the counter Ct 5331), set variable #j to "0" 5332),
The state is set to ``4go'' (S333).

When the state is "2", latches 302 and 303
Substitute yYo and Y+ for the coefficients 1 to 3 set in 304 (5341), and the counter Ct + becomes (T+912).
), that is, wait until the position of coordinate y1, which is the rear end of the mosaic monitor image GM, is reached (S342
), the state is set to "0" (S343).

When the state is "3", assign m to coefficients 1 to 3 (5351) and count C1! Wait until becomes Q, that is, wait until one block of mosaic monitor is completed (
S352), initialize the counter CL+5353),
The variable i is incremented by one (S354). Next, wait until the rear end of the mosaic monitor image is reached (S35).
5), the state is set to "0" (S356). In other words,
Here, the coefficient! Assuming that the same Iam- is set for ~3, each time the mosaic monitor image changes I block in the sub-scanning direction, the coefficients 1~3 are set to a new value "i+1".
will be changed to

When the state is "4", assign C0 to coefficients 1 to 3 (5361) and wait for the counter Ct to become (3Q), that is, wait for one block of the mosaic monitor to complete (S362). ), counter Ct! Initialize 5363) and increment variable j by 1 (S3
6'4). Next, wait until the rear end of the mosaic monitor image is reached (S365), and set the state to "0" (536).
6). That is, here, the same value C5 is set for coefficients 1 to 3, and each time the co-mosaic monitor image changes by three blocks in the sub-scanning direction, coefficients 1 to 3 are changed to a new value C6 (j+1).

When the processing in each state is completed, the counter Ct.

C(, is incremented (S371).

Through the above processing, various coefficients are set for each print color, and color adjustment is performed.

FIG. 25 shows the flow of superimpose output setting (S6). First, it is determined whether there are a plurality of registered images (S20+). If there are more than one, the user is prompted to make a selection on the operation panel 70 (5202) and waits for the user to complete the selection (S203).

If there is a single registered image, that registered image is set as the selected image (S204).

Next, a fixed offset m for address setting corresponding to the registered image to be output is set (S205), and data regarding the selected image is set in the registered image memory circuit l according to the registered image mode, and print data is output. Te (320
6), Return.

FIG. 26 shows the flow of image output (S206) in superimpose mode using multi-value storage (color).

Here, MAGA is the magnification ratio of the image relative to the original, and M
AGB is the scaling factor of the superimposed image with respect to the memory. First, set the WΣ/read signal to H', specify multi-value storage, and set the data holding signal for the 40th memory to H'.
', and the superimposed readout signal is H° (S
221).

Next, it is determined whether the magnification ratio MAGA=MΔGB (S222).

If the magnifications are the same (YES in S222), MAGA data is set to the variable magnification sub-scanning clock generator 29 (5223), the trimming control signal is set to II' (5224), and the readout area determination circuit 408 is set to successive areas. Send signals X and Y (S225), and send M to the electric variable magnification circuit 26.
AGA data is set (S226). Then, (5227) set the control signal to 000°, select all the memories 401, and scan Y, M, C, (S228).

After scanning, send the τ control signal '! 11 (S229), successive access to the memory 401 is prohibited, and the process returns.

If the magnification ratio MAGA=MAGB (N in S222)
o) First, the original image is printed outside the continuous printing area. That is, set the MAGA data in the sub-scanning clock generator 29 for variable magnification (S234), set the trimming control signal to L (8232), cause the selector 426 to select °white ° data in the successive area, and select the successive area discrimination circuit. 40
8, the area setting signals X and Y should be set taking into consideration the difference between MAGA and MAGB 5233), and the electric magnification circuit 26.
MAGA data is set in (S234). and,
Set “000” to the CS control signal S23
5) Select all memories and press Y for the original.

A scan is performed on M and C (8236).

Next, the image in the memory 401 is superimposed on the continuous area. In other words, the trimming control signal is
Set the superimposed signal to "H" and set the superimposed signal to "L".
237), causes the selector 421 to select °white data,
A readout area signal according to MAGB is set in the continuous area determination circuit 408 (9238), and a readout area signal according to MAGB is set in the electric magnification circuit 26.
Set data 5239) and set MAGB data in the sub-scanning clock generator 29 for scaling (S240)
. And a superimposed picture (about the elephant, Y, M,
A GK scan is performed (S241). After scanning, the CS control signal is set to °II mode (S229).
, prohibits continued access to the memory 401, and returns.

FIG. 27 shows the flow of image output (9206) in the superimpose mode using binary notation tα (color). In the registered image memory circuit 1, specify binary storage (S25+) and set the data holding signal to H'5252.
), the superimposed readout signal is set to 52
53), the trimming control signal is set to I-1' (S254). In addition, a sub-scanning clock generator 29 for variable magnification
5255), and set successive area setting signals X and Y to the successive area determination circuit 408 (5256).
), designates successive output (S257).

Next, set the CS control signal to 110° (S26
1) Select the memory 401a and perform yellow scanning (S262). Next, change the positive y control signal to °
As IO video (S263), the memory 401b is selected and magenta scan is performed (3264). Next, C8
The D control signal is set as OlV (9265), the memory 401c is selected, and cyan scanning is performed (S26).
6), and further set the CS control signal to 11 bits (
8267), scan black (8268),
Return.

FIG. 28 shows the flow of image output (S206) in the superimpose mode using binary storage (single color). In the monitor image memory circuit I, binary storage is specified, the data holding signal is set to I-1', the superimpose readout signal is set to °H', and the trimming control signal is set to H' (S28+).

Also, set the same size data in the sub-scanning clock generator 29 for scaling (3282), set the successive area setting signals X and Y in the successive area determination circuit 408 (S283), and set the memory selection data A to IIO'. , "l Obi or 01bi" 5284) and designates reading (S285).

Next, depending on whether or not to print the image registered in the memory in yellow (YES is NO in S286), the CS control signal is changed to memory selection data A (9286) or °11 bit (9287), Perform yellow scanning (5289). As a result, when printing in yellow, the registered image is superimposed in yellow. .

Similar processing is performed for magenta, noan, and black.

Finally, the CS control signal is set to 11 degrees, the data holding signal is set to "H" (S290), and the process returns.

Margin below (effect of the invention) If there is no need to perform scaling or color adjustment after image registration,
If it is selected to register images in the image storage means as binary data, a wide range of superimposed images can be registered. For example, if the multivalued data is 8 bits, it is possible to register a superimposed image that is 8 times wider.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view of a digital color copying machine. FIG. 2 is a block diagram of the signal processing section. FIG. 3 is a timing chart of image data processing. No. 1119 is a plan view of the operation panel. FIG. 5 is a diagram of area setting. Figures 6(a), (b), and (c) are, respectively,
FIG. 7 is a diagram of copying a document image, a diagram of copying a registered image, and a diagram of a superimposed image in superimpose mode. FIG. 7 is a diagram of the output format of the mosaic monitor. FIG. 8 is a circuit diagram of the registered image memory circuit. FIG. 9 is a circuit diagram of the data selection circuit. FIG. 10 is a timing chart of SP conversion. FIG. 11 is an explanatory diagram showing a method of registering multivalued image data and binary image data in a mixed manner in a memory. FIG. 12 is a circuit diagram of an area discrimination circuit and an address generation circuit. FIG. 13 is a timing chart of the area discrimination circuit. FIG. 14 is a diagram showing the registration status of a plurality of image data of the same size M. FIG. 15 is a diagram showing the registration status of a plurality of image data of different capacities. FIG. 16 is a circuit diagram of the image tone setting circuit. FIG. 17 is a diagram of the main flow related to the superimpose mode and mosaic monitor mode of the digital color copying machine. FIG. 18 is a flowchart of image registration processing. FIG. 19 is a flowchart of image registration in superimpose mode and mosaic monitor mode using multi-value storage. FIG. 20 is a flowchart of image registration in superimpose mode using binary storage (full color). FIG. 21 is a flowchart of monochrome image registration in superimpose mode using binary storage. FIG. 22 is a flowchart of mosaic monitor output settings. FIG. 23 is a flowchart of memory contents successive additions. FIGS. 24(a) and 24(b) are flowcharts of interrupt processing. FIG. 25 is a flowchart of superimpose output setting. FIG. 26 is a flowchart of image output in superimpose mode using multi-value storage. FIG. 27 is a flowchart of image output in superimpose mode using binary storage (color). FIG. 28 is a flowchart of image output in superimpose mode using binary storage (single g!). ■...Registered image memory circuit, 2...Picture setting circuit, 2
0... Signal processing circuit, 25 - CPU. 70...Operation panel, 84...Display section, 401a,
40 lb, 401cm--Memory, 402...Writing area determination circuit, 403...Writing address generation counter, 408...
Successive area determination circuit, 409... Successive address generation counter, 422...
3-state buffer, 442...data selection circuit. Patent applicant Minolta Camera Co., Ltd. Agent Patent attorney Aoyama Aoyama and one other person CK8 Figure 10 Figure 14 Figure 15 Figure I Y 11 Programmer full V counter 617) Figure 17 Old figure 25 page 28 Figure X Hin-sama's Tribe

Claims (1)

[Claims] (1) An image storage means for storing image data, an area setting means for setting an attention area on a document and a prohibited area on copy paper, and converting multivalued image reading data into binary print data for image printing.
A binarization means for digitizing, a selection means for selecting whether to store multi-valued image read data or binary print data after binarization by the binarization means in the image storage means, and an area setting means. A binarization means is provided before or after the image storage means in accordance with the selection of the document image of the set attention area by the selection means, and the image data is stored in the image storage means as multivalued image reading data or binary print data. an image registration means for storing; a printing means for printing on copy paper based on image printing data; and a printing means for printing on copy paper based on the image printing data; It is characterized by comprising a registered image printing control means in which a value conversion means is interposed before or after the image storage means, reads out the image data of the registered image registered in the image storage means, and sends image printing data to the printing means. Digital color copying machine.