JPH0237777A - vertical field effect transistor - Google Patents

Abstract

PURPOSE:To reduce a capacitance between a gate and a drain without increasing an ON resistance by forming a gate electrode between source regions via a gate insulating film which has been formed so as to be thin on a base region and so as to be thick on a semiconductor substrate. CONSTITUTION:An N<-> semiconductor layer 2 and an N<+> type diffusion layer 3 are formed on an N<+> type semiconductor substrate 1; a low-concentration N-type diffusion layer 6 is formed on the N<+> type diffusion layer 3 between P-type base regions 4. The N<+> type diffusion layer 3 is formed at a concentration and in a depth so as not to lower the breakdown voltage. A gate insulating film 7 is formed so as to be thick on a P-type base region between N-type source regions 5 and so as to be thick on the N<-> type diffusion layer 6. Accordingly, since a gate electrode G is formed, via a thick part of the gate insulating film 7, on the N<-> type diffusion layer 6 acting as a drain, a parasitic capacitance between a gate and a drain is reduced. Thereby, it is possible to reduce a capacitance between the drain and the gate without increasing an ON resistance.

Description

[Detailed Description of the Invention] Field of Industrial Application] The present invention relates to a semiconductor device, and in particular to a vertical field effect transistor (hereinafter referred to as vertical MO8FET) in which the concentration of the drain region on the surface of the substrate is increased to reduce the on-resistance. ) regarding.

[Conventional technology]

Conventionally, in the case of an N-type semiconductor substrate, this type of vertical MO3FET has an N+ semiconductor substrate 1 as a drain electrode, an N- semiconductor layer 2 and an N+ diffusion layer 3 thereon, as shown in FIG. The diffusion layer 3 has a P-type base diffusion layer 4 and an N-type source diffusion layer 5, and these P-type base diffusion layer 4 and N-type source diffusion layer 5 are short-circuited by a source electrode 5. It has a structure in which a gate electrode G is provided between type source diffusion layers 5 with a gate insulating film 7 interposed therebetween.
A highly-concentrated N+ diffusion layer 3 was provided as a drain region directly under the structure to reduce on-resistance.

[Problem to be solved by the invention]

In the above-mentioned conventional vertical MO8FET, the impurity concentration on the surface of the part that acts as the drain region directly under the gate electrode is high, so the depletion layer spreads little when biased between the drain and source, and the feedback capacitance C6D between the gate and drain is large. This has the disadvantage that the switching time cannot be made faster.

[Means to solve the problem]

According to the present invention, a base region having portions facing each other across the semiconductor substrate is provided on the surface of a semiconductor substrate that acts as a drain region, and a source region is formed within the base region, and there is a gap between the source regions. A vertical MO8FET is obtained in which a gate electrode is provided through a thin gate insulating film on a base region and a thick gate insulating film on a semiconductor substrate. The semiconductor substrate surface below the thick portion of the gate insulating film preferably has a lower impurity concentration than the impurity concentration below.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.

An N- semiconductor layer 2 and an N+-type wide diffusion layer 3 are provided on an N++ semiconductor substrate 1. The P-type base region 4 is provided in an island shape or a lattice shape, and has a shape in which there are mutually opposing portions. A low concentration N- diffusion layer 6 is provided on the N+ type scattering layer 3 between these P type base regions 4. N+
The wide type diffusion layer 3 is formed with a concentration and depth that does not lower the withstand voltage, and the N- type diffusion layer 4 is formed by compensating the impurity concentration by implanting ions of, for example, boron into the N++ diffusion layer 3. A thin gate insulating film 7 is provided on the P type base region between the N type source regions 5 and a thick gate insulating film 7 is provided on the N − type diffusion layer 6 . The thick portion of the gate insulating film 7 is made approximately 10 times as thick as the thin portion by selectively oxidizing a portion of the gate oxide film that does not affect the channel thickly (so-called LOCOS oxidation).

A gate electrode G made of polycrystalline silicon is provided on the gate insulating film 7.

Next, the characteristic manufacturing process will be explained with reference to FIG. After forming the N+ type wide diffusion layer 3, an oxide film 7 which will become a gate oxide film is formed on the surface. It is then covered with a nitride film 8 and selectively etched using a resist film where an N-type layer is to be formed. Thereafter, poron ions are implanted to form an N''' type layer. Using the same nitride film as a mask, the gate oxide film is oxidized to have a thickness about 10 times that of the gate oxide film.

According to this embodiment, since the gate electrode G is provided on the N-type diffusion layer 6 which acts as a drain through the thick part of the gate insulating film 7, the gate-drain parasitic capacitance C
6D is reduced, and high-speed switching is possible even though the on-resistance is reduced by the N+ type wide diffusion layer 3. Furthermore, a large drain-gate breakdown voltage can be obtained.

Although the N-channel type vertical MO8FET has been described above, it is clear that the present invention is similarly applicable to the P-channel type vertical MO8FET.

〔Effect of the invention〕

As described above, the present invention can reduce the capacitance between the gate and drain without significantly increasing the on-resistance by compensating the concentration of the drain layer directly under the gate electrode on the substrate surface. Further, by thickening a part of the gate oxide film by LOCOS oxidation, the capacitance between the gate and drain can be further reduced and the switching time can be increased. Further, by performing LOCOS oxidation on the gate oxide film, there is an effect that the dielectric strength of the gate oxide film can be improved.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a vertical MO8FET according to an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view showing characteristic steps of the manufacturing method, and FIG. 3 is a vertical cross-sectional view of a conventional vertical MO3FET. . 1... N++ semiconductor substrate, 2... Old N- semiconductor, 3... N+ type diffused layer 4... Group P type diffused layer, 5... N-type diffusion layer, 6...N-diffusion layer, 7...Insulating film, 8...Nitride film,
9. River...Resist. Agent Patent Attorney Susumu Uchihara

Claims (2)

[Claims] (1) On the surface of a semiconductor substrate that acts as a drain, a base region and a source region therein are provided so as to have mutually opposing portions, and between the opposing source regions there is a thin layer on the base region and a source region therein. A vertical field effect transistor characterized in that a gate electrode is formed through a thick gate insulating film formed on a semiconductor substrate. (2) The vertical field effect transistor according to claim (1), wherein the surface of the semiconductor substrate under the thick portion of the gate insulating film has a low surface concentration.