JPH023295B2 - - Google Patents
Info
- Publication number
- JPH023295B2 JPH023295B2 JP57030293A JP3029382A JPH023295B2 JP H023295 B2 JPH023295 B2 JP H023295B2 JP 57030293 A JP57030293 A JP 57030293A JP 3029382 A JP3029382 A JP 3029382A JP H023295 B2 JPH023295 B2 JP H023295B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- threshold voltage
- fet
- etching
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
- H01L21/30621—Vapour phase etching
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- ing And Chemical Polishing (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体層のエツチング処理方法に係
り、特に、電界効果型トランジスタ（FET）の
ゲート閾値電圧を所定の値に制御良く且つ精度良
く設定する方法に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a method for etching a semiconductor layer, and particularly to a method for setting the gate threshold voltage of a field effect transistor (FET) to a predetermined value with good control and accuracy. Regarding how to.
(2) 従来技術と問題点
ガリウム・ヒ素（GaAs）或いはGaAs―アル
ミニウム・ガリウム・ヒ素（AlGaAs）ヘテロ接
合等の半導体基板若しくは半導体層（略して半導
体基体）上に形成したシヨツトキーゲート型
FETは、主に半導体基体のソース・ドレイン電
極間の能動領域の厚みｔと、該領域の不純物ドー
ピング量NDの関数としてゲート閾値電圧が決定
される。このFETのゲート閾値電圧の制御法と
して、能動領域の厚みｔを所定の値に設定して所
定のゲート閾値電圧値を得る方法が用いられてい
るが、微細構造を有するFETの能動領域の厚み
ｔを例えばウエツト化学エツチング法により制御
性良く且つ均一にエツチングコントロールするこ
とは非常に困難である。(2) Prior art and problems Schottky gate type formed on a semiconductor substrate or semiconductor layer (semiconductor substrate for short) such as gallium arsenide (GaAs) or GaAs-aluminum gallium arsenide (AlGaAs) heterojunction
In the FET, the gate threshold voltage is determined mainly as a function of the thickness t of the active region between the source and drain electrodes of the semiconductor substrate and the amount N D of impurity doping in this region. As a method of controlling the gate threshold voltage of this FET, a method is used to obtain a predetermined gate threshold voltage value by setting the thickness t of the active region to a predetermined value. It is very difficult to control etching t uniformly and with good controllability, for example, by a wet chemical etching method.
上記欠点を克服する方法として、ドライエツチ
ング法で厚みｔを制御する方法が知られている。
その一例として半導体基体の主面に離隔した２つ
の電極を配設し、これらの電極を抵抗測定器に接
続し、前記半導体基体をドライエツチングしなが
ら、抵抗測定器により、前記電極間の半導体基体
の抵抗値を測定し、抵抗値が所定の値に達したと
き、ドライエツチングを停止する方法が知られて
いる。 As a method of overcoming the above-mentioned drawbacks, a method of controlling the thickness t using a dry etching method is known.
For example, two electrodes spaced apart from each other are arranged on the main surface of a semiconductor substrate, these electrodes are connected to a resistance measuring device, and while the semiconductor substrate is dry-etched, the semiconductor substrate between the electrodes is measured by the resistance measuring device. A method is known in which the resistance value of the etching layer is measured and dry etching is stopped when the resistance value reaches a predetermined value.
しかし、上記方法を用いて能動領域の厚みｔを
制御してFETのゲート閾値電圧を所定の値に設
定しようとする場合、三極端子構造を有する
FETでは能動領域をエツチングする毎にゲート
電極を形成し、その能動領域の厚みｔに対するゲ
ート閾値電圧を測定しなければならない。従つて
所定の閾値電圧に制御良く且つ精度良く容易に設
定することは難しい。 However, when attempting to set the gate threshold voltage of the FET to a predetermined value by controlling the thickness t of the active region using the above method, it is necessary to
In a FET, a gate electrode must be formed every time the active region is etched, and the gate threshold voltage must be measured with respect to the thickness t of the active region. Therefore, it is difficult to easily set the threshold voltage to a predetermined threshold voltage with good control and accuracy.
(3) 発明の目的
本発明の目的は、従来有していた欠点を解決
し、FETの能動領域表面にドライエツチングを
施しながら、能動領域の厚みを所定の閾値電圧に
制御良く且つ精度良く設定する半導体層のエツチ
ング処理方法を提供するにある。(3) Purpose of the Invention The purpose of the present invention is to solve the conventional drawbacks, and to set the thickness of the active region to a predetermined threshold voltage with good control and precision while performing dry etching on the surface of the active region of the FET. An object of the present invention is to provide a method for etching a semiconductor layer.
(4) 発明の構成
本発明は基板の一方の主面に、半導体層を配設
し、該半導体層の表面に所定領域をはさんで互い
に離隔した第１及び第２の電極を配設し、前記基
板の他方の主面のうち該所定領域に対向する部分
に第３の電極を配設し、前記第１の電極と第２の
電極との間に第１の電圧を、また前記第１の電極
（若しくは第２の電極）と第３の電極との間に第
２の電圧を印加しつつ、前記第１の電極と第２の
電極との間に流れる電流をモニタしつつ、前記所
定領域の前記半導体層をエツチングすることを特
徴とするものである。(4) Structure of the Invention The present invention includes a semiconductor layer disposed on one main surface of a substrate, and first and second electrodes spaced apart from each other with a predetermined region interposed between them on the surface of the semiconductor layer. , a third electrode is disposed on a portion of the other main surface of the substrate facing the predetermined region, and a first voltage is applied between the first electrode and the second electrode; While applying a second voltage between the first electrode (or the second electrode) and the third electrode and monitoring the current flowing between the first electrode and the second electrode, This method is characterized in that the semiconductor layer is etched in a predetermined region.
通常のFETに於いて、例えばFETが形成され
た基体裏面に電極を設け、バイアスを加えると、
基体裏面側から伸びる空乏層により、ゲート閾値
電圧のシフトが起こるというバツクゲート効果を
本発明は積極的に利用している。即ち、FETに
於いて、バツクゲート電極に深いバイアスを印加
すると、ゲート電極と同様、バツクゲートバイア
スによる閾値電圧を測定することができる為、予
めこのバツクゲート効果による閾値電圧の値と、
ゲートによる閾値電圧の値を対比させておくこと
により、ゲート電極が形成されていない状態で
も、ゲート閾値電圧の値を精度良く知ることがで
きる。 In a normal FET, for example, if an electrode is provided on the back surface of the substrate on which the FET is formed and a bias is applied,
The present invention actively utilizes the back gate effect in which a shift in gate threshold voltage occurs due to a depletion layer extending from the back surface of the substrate. That is, in a FET, if a deep bias is applied to the back gate electrode, the threshold voltage due to the back gate bias can be measured in the same way as the gate electrode, so the value of the threshold voltage due to this back gate effect and the
By comparing the values of the threshold voltages due to the gates, the value of the gate threshold voltages can be known with high accuracy even in a state where no gate electrode is formed.
(5) 発明の実施例
以下、本発明の一実施例を第１図ａ，ｂ及び第
２図を参照しつつ詳述する。(5) Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1a, b and 2.
第１図ａはAlGaAs−GaAs系高電子移動度
FETに於いて、半絶縁性基板上に素子領域を構
成する各半導体層及びソース・ドレイン電極を形
成した状態を示す。同図に於いて、半絶縁性
GaAs基板１上には層厚が数1000〔Å〕のノン・
ドープGaAs層２、シリコン（Si）をドープした
不純物濃度が1018cm-3で層厚が数100〔Å〕の
AlxGa1−xAs層３、Siをドープした不純物濃度
が1018cm-3で、層厚が数100〔Å〕のGaAs層４が
順次配設され、更にGaAs層４上にソース電極５
及びドレイン電極６、そして基板１裏面にバツク
ゲート電極７が金・ゲルマニウム（AuGe）／金
（Au）から成る材料で形成されている。 Figure 1a shows the high electron mobility of AlGaAs-GaAs system.
This figure shows a state in which semiconductor layers and source/drain electrodes constituting an element region are formed on a semi-insulating substrate in an FET. In the same figure, semi-insulating
On the GaAs substrate 1, there is a non-conductive layer with a thickness of several thousand Å.
Doped GaAs layer 2 is doped with silicon (Si) with an impurity concentration of 10 18 cm -3 and a layer thickness of several 100 Å.
An AlxGa 1 -xAs layer 3, a Si-doped GaAs layer 4 with an impurity concentration of 10 18 cm -3 and a layer thickness of several hundred Å are disposed in sequence, and a source electrode 5 is further disposed on the GaAs layer 4.
, a drain electrode 6 , and a back gate electrode 7 on the back surface of the substrate 1 are formed of a material consisting of gold/germanium (AuGe)/gold (Au).
本実施例ではデイプレツシヨン型のFETを作
成することにする。この型のFETではソース・
ドレイン電極５，６間に電圧を印加するとヘテロ
接合界面、即ちGaAs層２と、AlxGa1−xAs層３
との界面に平行に走る電子により電流が生じる。
第１図ｂは第１図ａの半導体層構造を有する装置
に於いて、ソース・ドレイン電極５，６間に第１
の電源E1そしてソース・バツクゲート電極５，
７間に第２の電源E2を接続した状態を示す。 In this example, a depression type FET will be created. In this type of FET, the source
When a voltage is applied between the drain electrodes 5 and 6, the heterojunction interface, that is, the GaAs layer 2 and the AlxGa 1 -xAs layer 3
A current is generated by electrons running parallel to the interface.
FIG. 1b shows a device having the semiconductor layer structure shown in FIG.
power source E 1 and source/back gate electrode 5,
7 shows a state in which the second power supply E2 is connected between the terminals.
本発明の実施にあたつては、所望のゲート閾値
電圧を得る為に予めゲート閾値電圧とバツクゲー
トによる閾値電圧との関係を知つておく必要があ
る。第２図は半導体能動領域４の深さ（若しくは
半導体能動領域４の厚さ）をパラメータにしたと
きの前記構造を有するFETのゲート閾値電圧と
バツクゲートによる閾値電圧との関係を測定した
グラフである。 In implementing the present invention, in order to obtain a desired gate threshold voltage, it is necessary to know in advance the relationship between the gate threshold voltage and the threshold voltage due to the back gate. FIG. 2 is a graph measuring the relationship between the gate threshold voltage of the FET having the above structure and the threshold voltage due to the back gate when the depth of the semiconductor active region 4 (or the thickness of the semiconductor active region 4) is used as a parameter. .
今、ゲート閾値電圧の値を例えば−0.4〔Ｖ〕に
設定したい場合には、第２図のグラフからソース
電極５とバツクゲート電極７との間には−40〔Ｖ〕
の電圧を印加すればよいことがわかる。 Now, if you want to set the value of the gate threshold voltage to, for example, -0.4 [V], the voltage between the source electrode 5 and the back gate electrode 7 is -40 [V] from the graph of FIG.
It can be seen that it is sufficient to apply a voltage of .
本実施例では、エツチング装置として２極電極
構造からなる通常の反応性イオンエツチング装置
を用いる。そして、前記半導体装置を該装置内に
設置し、ソース電極５とバツクゲート電極７との
間の電源E2を−40〔Ｖ〕とし、ソース電極５とド
レイン電極６との間の電源E1を２〜５〔Ｖ〕とし
た状態で該ソース・ドレイン電極５，６間の能動
領域８のエツチングを行なう。 In this embodiment, an ordinary reactive ion etching apparatus having a bipolar electrode structure is used as the etching apparatus. Then, the semiconductor device is installed in the device, the power source E 2 between the source electrode 5 and the back gate electrode 7 is set to -40 [V], and the power source E 1 between the source electrode 5 and the drain electrode 6 is set to -40 [V]. Etching of the active region 8 between the source and drain electrodes 5 and 6 is performed under a condition of 2 to 5 [V].
このとき、電極引き出し用の導線はガスプラズ
マを乱さないような１〜２〔mm〕程度の径で且つ
絶縁物で被覆されたものを用いる。またエツチン
グ用ガスとしてはフロン１２（CCl2F2）を用い
る。尚、CCl2F2によるGaAsの反応性イオンエツ
チングは、二酸化シリコン（SiO2）及びレジス
トとの選択性も良好であり、又オーミツク電極と
の選択性も良好である。 At this time, a conductive wire for leading out the electrode is used, which has a diameter of about 1 to 2 mm and is coated with an insulating material so as not to disturb the gas plasma. Further, Freon 12 (CCl 2 F 2 ) is used as the etching gas. Note that reactive ion etching of GaAs using CCl 2 F 2 has good selectivity with silicon dioxide (SiO 2 ) and resist, and also with good selectivity with ohmic electrodes.
このようにして、前記半導体層４の能動領域８
のエツチングを行つてゆくと、ある時点におい
て、ソース電極５とドレイン電極６との間の電流
が零となる。これはエツチングの進行に伴つて半
導体層４の厚さが減少し、該半導体層４の表面に
おける表面準位により発生する空乏層と、前記バ
ツクゲート電圧によつて半導体層４内に生じてい
る空乏層とが接触し、ソース電極５とドレイン電
極６との間の電流通路が遮断されることによる。 In this way, the active region 8 of the semiconductor layer 4
As etching continues, the current between the source electrode 5 and the drain electrode 6 becomes zero at a certain point. This is because the thickness of the semiconductor layer 4 decreases as etching progresses, and a depletion layer occurs due to surface levels on the surface of the semiconductor layer 4, and a depletion layer occurs within the semiconductor layer 4 due to the backgate voltage. This is because the current path between the source electrode 5 and the drain electrode 6 is cut off.
このようにソース電極５とドレイン電極６との
間の電流が零となつた時点で、かかるエツチング
を停止する。 The etching is stopped when the current between the source electrode 5 and the drain electrode 6 becomes zero.
しかる後、かかる本発明によるエツチング処理
方法によつて、半導体層４の厚さが所定の値に加
工された前記FETの前記半導体層４の能動領域
８の表面に例えばチタン（Ti）白金（Pr）／金
（Au）からなるゲート電極を配設すれば、ゲート
閾値電圧が−0.4〔Ｖ〕のデイプレツシヨン型FET
が形成される。 Thereafter, by using the etching method according to the present invention, for example, titanium (Ti), platinum (Prium, ) / If a gate electrode made of gold (Au) is provided, a depletion type FET with a gate threshold voltage of -0.4 [V] can be created.
is formed.
尚、本実施例ではデイプレツシヨン型のFET
について述べたが、エンハンスメント型FETに
於いても同様な方法でゲート閾値電圧を所定の値
に精度良く設定できる。また、本実施例では
AlGaAs−GaAs系高電子移動度FETについて説
明しているが、リセス構造のFETのすべての製
造に本発明を適用することができる。 Note that in this example, a depression type FET is used.
As described above, the gate threshold voltage can be set to a predetermined value with high precision in an enhancement type FET as well using a similar method. Also, in this example
Although an AlGaAs-GaAs-based high electron mobility FET is described, the present invention can be applied to the manufacture of all recessed structure FETs.
(7) 発明の効果
本発明によれば、エツチングの均一性に優れた
ドライエツチングを用いて、半導体基板の能動領
域にゲート電極を形成することなしに、所定のゲ
ート閾値電圧を精度良く且つ容易に設定できると
いう効果がある。(7) Effects of the Invention According to the present invention, by using dry etching with excellent etching uniformity, a predetermined gate threshold voltage can be easily and accurately set without forming a gate electrode in the active region of a semiconductor substrate. This has the effect that it can be set to
第１図ａ及びｂはAlGaAs−GaAs系高電子移
動度FETの製造工程断面図、第２図は半導体能
動領域の深さ（若しくは半導体能動領域の厚さ）
をパラメータしたときの本発明の実施例における
前記FETのゲート閾値電圧とバツクゲートによ
る閾値電圧との関係を示したグラフである。
１……半絶縁性GaAs基板、２……GaAs層、
３……ｎ形AlxGa1−XAs層、４……ｎ形GaAs
層、５，６……ソース及びドレイン電極、７……
電極。
Figures 1a and b are cross-sectional views of the manufacturing process of an AlGaAs-GaAs high electron mobility FET, and Figure 2 is the depth of the semiconductor active region (or the thickness of the semiconductor active region).
12 is a graph showing the relationship between the gate threshold voltage of the FET and the threshold voltage due to the back gate in the embodiment of the present invention when . 1... Semi-insulating GaAs substrate, 2... GaAs layer,
3... n-type AlxGa 1 -XAs layer, 4... n-type GaAs
Layers 5, 6...source and drain electrodes, 7...
electrode.
Claims (1)
半導体層の表面に所定領域をはさんで互いに離隔
した第１及び第２の電極を配設し、前記基板の他
方の主面のうち該所定領域に対向する部分に第３
の電極を配設し、前記第１の電極と第２の電極と
の間に第１の電圧を、また前記第１の電極（若し
くは第２の電極）と第３の電極との間に第２の電
圧を印加しつつ、前記第１の電極と第２の電極と
の間に流れる電流をモニタしつつ、前記所定領域
の前記半導体層をエツチングすることを特徴とす
る半導体装置のエツチング処理方法。1. A semiconductor layer is provided on one main surface of a substrate, first and second electrodes are provided on the surface of the semiconductor layer separated from each other with a predetermined region in between, and the other main surface of the substrate A third portion is placed in a portion facing the predetermined area.
A first voltage is applied between the first electrode and the second electrode, and a third voltage is applied between the first electrode (or the second electrode) and the third electrode. A method for etching a semiconductor device, characterized in that the semiconductor layer in the predetermined region is etched while applying a voltage of 2 and monitoring a current flowing between the first electrode and the second electrode. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57030293A JPS58147123A (en) | 1982-02-26 | 1982-02-26 | Etching method for semiconductor layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57030293A JPS58147123A (en) | 1982-02-26 | 1982-02-26 | Etching method for semiconductor layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58147123A JPS58147123A (en) | 1983-09-01 |
| JPH023295B2 true JPH023295B2 (en) | 1990-01-23 |
Family
ID=12299679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57030293A Granted JPS58147123A (en) | 1982-02-26 | 1982-02-26 | Etching method for semiconductor layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147123A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02165641A (en) * | 1988-12-20 | 1990-06-26 | Sanyo Electric Co Ltd | Manufacture of field effect transistor |
| US7494596B2 (en) | 2003-03-21 | 2009-02-24 | Hewlett-Packard Development Company, L.P. | Measurement of etching |
| CN109887872B (en) * | 2019-03-29 | 2024-11-15 | 华南理工大学 | Precision etching device and etching method for preparing recessed gate enhancement type device |
-
1982
- 1982-02-26 JP JP57030293A patent/JPS58147123A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58147123A (en) | 1983-09-01 |
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