JPH0232562A - Manufacture of cmos semiconductor device - Google Patents

Abstract

PURPOSE:To make either of depression masks unnecessary by using a depression mask for well formation of an MOS semiconductor device also as an inversion preventing mask of a capacitor. CONSTITUTION:When an MOS semiconductor device having an MOS capacitor is manufactured, N-type impurity is introduced to specified two regions of a P-type semiconductor substrate 111 through ion implantation to form two N-wells 113, 115 simultaneously. During this process, other regions excepting the said regions are masked by a resist. Then a surface of the substrate 111 is selectively oxidized to form a field oxide film 17, and the substrate surface is isolated to a plurality of transistor formation regions 113, 119 and an MOS capacitor formation region 115. A p-channel FET 129 is formed on the region 113 through P-type ion implantation by using a mask from the substrate surface. In a divided region, an N-channel FET 139 and an MOS capacity 141 are formed on regions 119, 115, respectively by use of a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a CMOS semiconductor device, which forms a capacitor in the CMOS semiconductor device.

<Prior Art> Generally, the capacitance of a MOS type capacitor is set by a series connection of an oxide film capacitance and a depletion layer capacitance. This depletion layer capacitance changes depending on the gate voltage value. Therefore, the capacitance value cannot be kept constant. As a result, in a circuit that handles alternating current signals, the operation of the transistor becomes unstable. Therefore, it is desired to operate the capacitor in a region where no depletion layer capacitance is generated.

FIG. 5 is a graph showing the C-■ characteristics of a MOS capacitor.

Conventionally, a process such as ion implantation was added to form a pseudo channel directly under the gate to eliminate the influence of the depletion layer.

That is, in the case of an IC including a MOS capacitor or CMOS transistor, it has conventionally been manufactured by the following process.

FIGS. 4(a) to 4(f) show cross-sectional views at each step for explaining a conventional (7) method of manufacturing a CMOS type semiconductor device having four MO3 type capacitors.

First, as shown in FIG. 4A, a P-type semiconductor substrate 11, for example, is prepared. Next, as shown in FIG. 4B, an N-type impurity is introduced into a predetermined region of the semiconductor substrate 11 by, for example, ion implantation to form an N-well 13.

At this time, other areas are masked with resist.

Next, as shown in FIG. 1C, the surface of the substrate 11 is selectively oxidized to form a field oxide film 15 on the surface, and the surface of the substrate is separated into a plurality of transistor forming regions. A mask is also used in this case.

Next, as shown in FIG. 2D, N-type impurities are introduced into a predetermined isolation region (MOS capacitor formation region) of the substrate 11 by ion implantation. In this case, other areas are covered by resist. As a result, a predetermined N type region is formed in the MOS capacitor formation region.

Next, as shown in FIG. 3(e), the N well region 13
An insulator N17 and a gate electrode 19 are deposited and formed on the surface of the substrate 11 by a predetermined mask process, and insulators BF'27, 29 and 29 are formed on the other isolation regions (MOS capacitor formation region and NFET formation region) of the substrate 11, respectively. Gate electrodes 31 and 33 are formed using lithography technology. Furthermore, P-type impurities are introduced into the N-well region 13 from the surface of the substrate by, for example, ion implantation using a mask to form the source region 21 and the drain region 2.
form 3. A P-channel FET (field effect transistor) 25 is formed in the region 13.

Furthermore, as shown in the same figure (f), the above N
N-type impurities are introduced at a high concentration into a portion excluding the well region 13. As a result, an N-channel type FET 35 and an MO8 capacitor 1i37 are formed on the P-type semiconductor substrate 11.

<Problems to be Solved by the Invention> However, in such a conventional method for manufacturing a semiconductor device, a depression mask is required in addition to the normal MOS transistor formation process to form a MOS capacitor. The cost of the mask increased the unit price of the wafer. Therefore, the chip cost has also increased.

It is something that

<Operation> In the method for manufacturing a semiconductor device according to the present invention, MOS transistors of opposite conductivity types are arranged in parallel on a substrate, and a capacitor is also arranged.

<Means for Solving the Problems> The present invention includes a step of forming wells of a second conductivity type at a plurality of locations on a semiconductor substrate of a first conductivity type, and a step of forming wells of a second conductivity type in the semiconductor substrate of the first conductivity type. While introducing impurities to form a field effect transistor having a channel of the second conductivity type,
forming a capacitor in one of the wells of the second conductivity type; and introducing an impurity of the first conductivity type into the remaining one of the wells of the second conductivity type to form a capacitor of the first conductivity type. Embodiment A first embodiment of a CMOS semiconductor device according to the present invention will be described below with reference to the drawings. Refer to and explain.

FIGS. 1(a) to (f) show the M according to the first embodiment of the present invention.
1A and 1B are cross-sectional views at each step for explaining a method of manufacturing a CMOS semiconductor device having an OS capacitor.

First, as shown in FIG. 4A, a P-type semiconductor substrate 111, for example, is prepared.

Next, as shown in FIG. 2(b), this semiconductor substrate 111
Two N-wells 113 and 115 are simultaneously formed by introducing N-type impurities into two predetermined regions of the wells by, for example, ion implantation. At this time, other areas other than these are masked with a resist.

Next, as shown in FIG. 1C, the surface of this substrate 111 is selectively oxidized to form a field oxide film 117 on the surface, and the surface of the substrate is used to form a plurality of transistor formation regions.
13, 119 and an MO9 type capacitor forming region 115. A mask is also used in this case.

Next, as shown in the figure (d), insulating layers 121, 131
．． 133, gate electrodes 123, 135, 137 are deposited and formed by a predetermined mask process. Further, in this N-well region 113, a mask is used by, for example, ion implantation from the substrate surface (other regions 115.1
19) by introducing P-type impurities into the source region 125,
and a drain region 127. P channel type F
An ET (field effect transistor) 129 is connected to the region 113.
It is to be formed.

Furthermore, as shown in FIG.
In the formation region 119), a mask is used to form (PFET
N-type impurity is introduced at a high concentration in a self-aligned manner into a predetermined portion (covering 129). As a result, an N-channel type FET 139 and an MO5 type capacitor 141 are formed in predetermined regions 119 and 115 on the P-type semiconductor substrate 111, respectively.

As a result of the above, on the semiconductor substrate 111 there are a P-channel FET 129, an N-channel FET 139, and an M
An O5 type capacitor 141 is formed. Note that the order of the steps shown in (d) and (e) above may be reversed.

Next, FIGS. 2(a) to (e) show the second manufacturing method of the present invention.
This shows an example.

In this embodiment, CMO8 and MO5 type capacitors are formed on an N type semiconductor substrate 211.

That is, in FIG. 2(a), an N-type semiconductor substrate 2
Prepare 11. Next, as shown in FIG. 2B, P-type impurities are introduced into two regions of the substrate 211 by ion implantation using a mask to form P wells 213 and 215.

Next, as shown in the same figure (C), the field oxide film 21
7 is formed on the surface of the substrate 211 to form the substrate surface in the region 21.
Separate into 3.219.215.

Next, as shown in FIG.
．． 233, depositing gate electrode 223.235.237;
Form. Furthermore, N type impurities are introduced into this P well region 213 from the substrate surface by ion implantation to form a source and a drain. Other areas 215, 219 are masked.

N-channel FET (field effect transistor) 22
5.

Furthermore, as shown in FIG. 2(e), P-type impurities are also introduced into other isolation regions of the substrate 211. As a result, a P-channel type FET 227 and an MO3 capacitor 229 are formed on the N-type substrate 211.

FIG. 3 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

That is, in this embodiment, M of the first embodiment is
In the process of forming an OS type capacitor, the gate electrode 3
After forming 01, a predetermined opening 303 is formed therein. After the opening is formed, ions are implanted into the N well 305 through the opening 303 as well.

As a result, when one wide gate electrode 301 is formed, an N-type impurity is implanted into the N well 3.5 at a predetermined position 303. In the figure, 307 is a field oxide film, 309 is an aluminum wiring, and 311 is a field oxide film.
is an insulating layer.

As described above, in this embodiment, M
The O3 type capacitor is divided into small parts. As a result,
Since the carriers become more mobile, stable capacitance can be obtained and internal resistance can be reduced.

<Effects> As explained above, according to the present invention, it is possible to use both a depression mask for forming a well and a mask for preventing an inversion layer of a capacitor, making either one of the depression masks unnecessary. , the cost of the mask can be reduced. Furthermore, since the depression process is reduced, the number of process days can be reduced due to the reduction in the number of processes. Furthermore, by eliminating the depression process, the wafer unit price and chip cost can be reduced.

Also, due to the capacitor with this structure, the majority carriers on the board can
Since it is used in a stored state, it can be used in a state where the capacitance value is MAX, and as a result, a stable capacitance value can be obtained in a circuit that handles AC signals.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are cross-sectional views showing each process according to the first embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG.
a) to (e) are cross-sectional views showing each step according to the second embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 3 is a longitudinal cross-sectional view of a semiconductor device formed by the method of the present invention, and FIG. (a)
~(f) are vertical cross-sectional views showing each process related to a conventional semiconductor device manufacturing method, and FIG. 5 is a c-■ of a MOS capacitor.
It is a graph showing characteristics. 111...P-type semiconductor substrate, 113.1
15...N-type well, 129...
P-type FET, 139...N-type FET, 1
41・・・・・・MO3 type capacitor. Patent applicant ROHM Co., Ltd. agent Patent attorney Abe Itsube 2nd rI! :i Figure 4, Section 5

Claims (1)

[Claims] (1) Forming wells of a second conductivity type at multiple locations on a semiconductor substrate of a first conductivity type, and introducing impurities of a second conductivity type into the semiconductor substrate of the first conductivity type to form wells of a second conductivity type. forming a field effect transistor having a channel, and forming a capacitor in one of the wells of the second conductivity type;
The first conductivity type is placed in one of the remaining wells of the second conductivity type.
A method of manufacturing a CMOS semiconductor device, comprising the step of: introducing an impurity of a first conductivity type to form a field effect transistor having a channel of a first conductivity type.