JPH0231179A - Large scale integrated circuit device with scan path - Google Patents

Abstract

PURPOSE:To reduce planning cost and part cost by realizing a circuit part susceptible to a scanning test on a printed circuit board and a circuit insusceptible thereto by the same LSI. CONSTITUTION:At the time of a scanning test by an LSI alone, by falsely setting a scanning test prohibiting signal 16, a system lock 13 and a scanning test signal 15 are inputted to the first and second circuit parts 11, 12 and the scanning test using a scanning path is performed. At the time of the scanning test on a printed circuit board, by really setting the signal 16, a special lock 14 is inputted to the circuit part 12 in place of the system clock 13 and the route of the scanning path corresponding to the circuit part 12 is bypassed. Further, since the input of the signal 15 to the circuit part 12 is suppressed, the circuit part 12 is removed from the subject of the scanning test. During this time, the system lock 13 and the signal 15 are inputted to the circuit part 11 and the scanning test on the printed circuit board of the circuit part 11 is performed without exerting effect on the circuit part 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a large-scale integrated circuit device having a scan path for scan testing.

(Prior art) This type of large-scale integrated circuit device (hereinafter referred to as LSI)
Here, the flip-flop (hereinafter referred to as F/
A system clock is generally input to the clock input of the clock F (referred to as F).

In the scan test using the scan path, as shown below: (1) Set arbitrary data to all F/Fs by scan-in.

■ The level of the D (data) input of each F/F is taken into the F/F by the system clock input.

■ Read the values taken into each F/F by scan-out.

This is done through a series of steps. Therefore, for example, for a circuit part that uses a clock other than the system clock (hereinafter referred to as a special clock), such as a clock generation circuit, either configure it with a separate LSI or separate the scan path of that circuit part. Therefore, it was necessary to prevent a scan test of the circuit part from being performed even on a single LSI.

Nowadays, we use the scan path inside the LSI to
There is a demand for LSI testing with the SI mounted on a printed board (that is, at the board level), board wiring testing, and the like. However, if an arbitrary value is set to an LSI that generates scan test control signals during a scan test on the board, a problem will occur in the operation of the scan test itself, so it is not possible to execute the scan test on the board. It was impossible. For this reason, conventionally, the circuit section that generates scan test control signals has to be configured with a separate LSI, and if this is not possible, scan tests of other circuit sections on the board cannot be performed. There wasn't.

(Problems to be Solved by the Invention) As mentioned above, conventionally, when there is a circuit part within an LSI for which scan testing cannot be performed, other circuit parts are also tested on the printed board. There is a problem in that the scan test cannot be performed correctly, and therefore the circuit portions in which the scan test cannot be performed must be configured with independent LSIs.

Therefore, in this invention, even if a circuit part that can be scan tested on a printed board and a circuit part that cannot be scan tested are realized in the same LSI, the scan test of both circuit parts can be performed with a single LSI, and the circuit part that can not be scan tested can be printed. The problem to be solved is to enable the scan test of the former circuit section to be performed correctly on the board without being affected by the latter circuit section.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a first circuit portion that operates with a system clock and is capable of performing a scan test on a printed board, and a first circuit portion that operates with a special clock in a normal state. , a second circuit portion that cannot be scan tested on a printed board;
A scan path used for a scan test of the first and second circuit portions is realized by the same LSI, and the second circuit is activated in response to a scan test prohibition signal for prohibiting the scan test of the second circuit portion. means for selectively bypassing a path of a scan path corresponding to the section; and a means for selectively bypassing a path of a scan path corresponding to the section; The present invention is characterized in that it is provided with a gate means for inhibiting the clock according to the scan test inhibit signal, and a clock selection means for selecting either the system clock or the special clock according to the scan test inhibit signal and inputting the selected clock to the second circuit portion.

(Operation) According to the above configuration, LSI! By setting the scan test prohibition signal to false during a scan test in a Ji body, the system clock and scan test signal are input to the first and second circuit parts, and both the first and second circuit parts are targeted. A scan test using a scan path is performed. Furthermore, by setting the scan test inhibit signal to true during a scan test on a printed board, a special clock is input to the second circuit section instead of the system clock, and a scan path corresponding to the second circuit section is input. Since the path is bypassed and input of the scan test signal to the second circuit portion is inhibited, the second circuit portion is excluded from the scan test target.

During this time, the system clock and scan test signals are manually applied to the first circuit section in the same way as during the scan test on a single LSI, and the printed board-L of the first circuit section is
A scan test is performed without being influenced by the second circuit portion.

(Embodiment) FIG. 1 shows a schematic configuration of an LSI according to an embodiment of the present invention, and 10 is a scan path (
(not shown).

11 is the internal circuit part of LSIl0 (circuit part #1),
12 is also an internal circuit portion (circuit portion #2) of LSI10. The circuit portion 11 is operated by a system clock 13, which will be described later, and a scan test can be performed on the LSI10 alone or when it is mounted on a printed board (not shown) (even on the board). On the other hand, the circuit portion 12 operates in a normal state using a special clock 14, which will be described later, and a scan test on the board is not possible.

13 is a system clock supplied to the circuit portions 11 and 12; 14 is a special clock supplied only to the circuit portion 12; and 15 is an LSI for controlling the scan test operation.
This is a scan test signal given from outside the I-mouth. The scan test signal 15 is input to the circuit portion 11 unconditionally. 1B is a scan test prohibition signal applied from outside the LS 110 to prohibit a scan test on the board of the circuit section 12; 17 is a scan test signal 1;
5 is a gate (G) for inhibiting input to the circuit portion 12 according to the state of the scan test inhibit signal 16.

FIG. 2 shows a part of the configuration around the external scan path included in the LSI 10 of FIG. In the same figure, P1
~P4 is the external terminal (pad) of LS110, 21~
24 is an F/F provided corresponding to the external terminal Pi-P4
(flip-flop) circuit. This F/F circuit 2
Reference numerals 1 to 24 designate F/Fs (not shown) that are serially connected and form part of a kind of shift register in a normal state. Also, among the F/F circuits 21 to 24, the circuit corresponding to the external terminal for human power inputs the data set in the F/F in the circuit (via the corresponding external terminal) like external input data. The circuit, which has well-known circuit elements (not shown) for guiding the output data (from the internal random logic) to that external terminal, and corresponds to the external terminal for output, F/F in the same circuit
It has well-known circuitry (not shown) for guiding. F/F circuits 21 and 24 are included in the circuit portion 11, and F/F circuits 21 and 24 are included in the circuit portion 11, and
F circuits 22 , 23 are included in circuit portion 12 .

30 is a signal line for transmitting scan data to the F/F circuit 21, and 31.32 is a signal line for transmitting scan data from the F/F circuit 21.22 to the next stage F/F circuit 22.23. It is. 33.34 is the F/F circuit 23,
A signal line for transmitting scan data from 24 to the next stage, 35 a signal line for transmitting scan data to the F/F circuit 24, and 3B a scan test prohibition signal for either signal line 31 or 33. Signal line 35 according to 16
This is a multiplexer that switches and connects to the

FIG. 3 shows a part of the configuration around the internal scan path included in LSI10 of FIG. In the same figure, 41 to 44
is an F/F with scan input/output that is connected serially and forms part of a kind of shift register in a normal state. F
/F41, 44 are included in the circuit portion 11, F/F42.
43 is included in the circuit portion 12.

In this embodiment, F/Fs 42 and 43 are used to form a frequency dividing circuit. 50 is a signal line that transmits scan data to the serial input (Sl) of F/F 41, 51 and 52 are F/F 4L, and scan data from the serial output (SO) of 42 is transmitted to the next stage F/Fs 42 and 43, respectively. This is a signal line for transmitting data to the serial human power (SI).

53.54 is the serial output (SO) of F/F43 and 44
A signal line for transmitting scan data from to the next stage,
55 is a signal line for transmitting scan data to the serial input (Sl) of the F/F 44. Note that in FIG. 3, the scan clock input necessary for serial input/output of scan data targeted at F/Fs 41 to 44 is omitted.

56 is a multiplexer that switches and connects one of the signal lines 51 and 53 to the signal line 55 in response to the scan test prohibition signal 16; 57 is a multiplexer that connects either the system clock 13 or the special clock 14 to the
This is a multiplexer that selectively outputs the clock (CK) of /F42 and 43 manually. Note that the F/F in the circuit portion 11
The system clock 13 is constantly supplied to the clocks 41 and 44.

Next, the operation of one embodiment of the present invention will be explained using a scan test on a single LSI10 as an example.

■ When performing a scan test on LSI10 alone,
The scan test prohibition signal 1B is set to "0° (false). In this case, the gate 17 shown in FIG. It is also transmitted to circuit portion 12.

■ Also, in Figure 2, scan test prohibition signal 1
By setting B to “0”, multiplexer 3
6 connects the signal line 33 of the signal lines 31 and 33 to the signal line 3.
Selectively connect to 5. As a result, the signal line 30-F/
F' circuit 21 - signal line 31 - F/F circuit 22 → signal line 3
2 → F/F circuit 23 → signal line 33 → (multiplexer 3
6→) An external scan path extending over the circuit portion 11 and the circuit portion 12 is formed as follows: signal line 35→F/F circuit 24→signal line 34-.

(2) On the other hand, in FIG. 3, when the scan test prohibition signal 16 is set to "0", the multiplexer 56 selectively connects the signal line 53 of the signal lines 51 and 53 to the signal line 55. As a result, the signal line 50-F
/F41-signal line 51-F/F42-signal line 52→F/
F circuit 43-signal line 53-(multiplexer 5B=) signal line 55→F/F 44-signal line 54-, etc.
An internal scan path spanning circuit portion 11 and circuit portion 12 is formed. Further, when the scan test prohibition signal 16 is "0", the multiplexer 57 outputs the system clock 1 out of the system clock 13 and the special clock 14.
Select 3 and F/F in circuit part ll 42.43
''s clock (CK) is output to human power.

As a result, all F/Fs on the internal scan path including F/Fs 41 to 44 (F/Fs with scan input/output
/F) clock (CK) system clock 13 manually
will be done manually.

According to the above ■～■, L S I to alone, LS
A scan test can be performed on both circuit portions 11 and 12 within I10.

Next, a scan test in a state where the LSI10 is mounted on a printed board will be described.

■ When performing a scan test on the board, the scan test prohibition signal 16 is set to "1" (true).

In this case, the gate 17 shown in FIG. 1 is in an output disabled state. As a result, scan test signal 15 is transmitted only to circuit portion 11.

■ Also, in Figure 2, scan test prohibition signal 1
6 is set to “1”, multiplexer 3
B selectively connects the signal line 31 to the signal line 35. As a result, the signal line 30 - F/F circuit 21 - signal line 31 → (
Multiplexer 36→) Signal line 35→F/F circuit 24-
Like the signal line 34-, an external scan path is formed in which the external scan path portion corresponding to the circuit portion 12 is bypassed.

■ On the other hand, in FIG. 3, the scan test prohibition signal 16 is set to 1", so that the multiplexer 5
6 selectively connects the signal line 51 to the signal line 55. As a result, signal line 50-F/F41-signal line 51->(multiplexer 56-) signal line 55-F/F44->signal line 5
4→, an internal scan path is formed in which the internal scan path portion corresponding to the circuit portion 12 is bypassed. Also, if the scan test prohibition signal 1B is °1",
The multiplexer 57 selects the special clock 14 and outputs it to the clock (CK) inputs of the F/Fs 42 and 43 in the circuit section 11.

As a result of the above ■ to ■, on the board "2, only the circuit section 11 of the circuit sections 11 and 12 in the LSI10 can perform a scan test, and operates with the special clock 14 in the normal state (scan test on the board The circuit portion I2 (which is impossible) is not subject to the scan test.

[Effects of the Invention] As described in detail above, according to the present invention, a circuit portion on a printed board that can be scan tested (first circuit portion) and a circuit portion that cannot be scan tested (second circuit portion) Even if both circuit parts are implemented using the same LSI, scan tests of both circuit parts can be performed using a single LSI. Further, according to the present invention, since the second circuit part on the printed board can be excluded from the scan test, the scan test of the first circuit part can be performed on the first circuit part (operating with a clock different from the system clock). It can be executed correctly without being affected by the circuit part 2. In this way, connect both circuit parts to the same -L
Since it can be realized by SI, it is possible to reduce the design cost and component cost, and since the scan test is an iJ function, it is possible to improve the failure detection rate and improve the reliability.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an LSI (large scale integrated circuit device) according to an embodiment of the present invention, FIG. 2 is a diagram showing a partial configuration around an external scan path included in the LSI of FIG. 1, FIG. 3 is a diagram showing a part of the configuration around the internal scan path included in the LSI shown in FIG. 1. 10...LSI, 11...Circuit part (first circuit part) 12999 circuit part (second circuit part), 13...
・System clock, 14...Special clock, 15・
...Scan test signal, 16...Scan test prohibition signal, 17...Gate (G), 21-24...F
/F circuit, 3B, 5G, 57...multiplexer, 41-44...F/F. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3 Figure 2

Claims (1)

[Claims] A first circuit portion that operates with a system clock and is capable of performing a scan test while mounted on a printed board;
A second circuit portion that operates with a special clock different from the system clock in a normal state and cannot perform a scan test while mounted on the printed board; In a large-scale integrated circuit device equipped with a scan path to be subjected to a scan test, the second circuit section is operated in response to a scan test prohibition signal applied from the outside to inhibit the scan test of the second circuit section. means for selectively bypassing a path of said scan path corresponding to said scan path, and a scan test signal externally applied to said first and second circuit portions for controlling a scan test operation is applied to said second circuit portion. gate means for inhibiting the input of the system clock or the special clock in response to the scan test prohibition signal; and selecting one of the system clock and the special clock in response to the scan test prohibition signal and inputting the selected clock to the second circuit portion. clock selection means, and when performing a scan test on the large-scale integrated circuit device alone, sets the scan test prohibition signal to false and inputs the system clock and scan test signal to the first and second circuit portions. and execute a scan test targeting the first and second circuit portions, and during the scan test with the large-scale integrated circuit device mounted on the printed board,
Setting the scan test prohibition signal to true and selectively inputting the special clock to the second circuit portion, bypassing the path of the scan path corresponding to the second circuit portion, and performing the scan test. The signal is the second one above.
1. A large-scale integrated circuit device having a scan path, characterized in that the second circuit section is excluded from a scan test by inhibiting input to the circuit section.