JPH0225904A - Link system for programmable controller - Google Patents

Abstract

PURPOSE:To simply cope with occurrence of the abnormality of an opposite station by setting or resetting a reception data clear flag to an interface module via a user and clearing the reception data or keeping it as it is to a CPU module in case the opposite station of transmission has an abnormal state. CONSTITUTION:The interface modules 20 and 70 of a master station 100 and a slave station 200 contain the reception data clear flag memory means 21 and 71 where the standard flags are set to clear the reception data and the reception data check means 22 and 72 which checks the presence or absence of the abnormality of the reception data respectively. Then the data on the CPU modules 10 and 60 are reset based on the ON signals of flags ZF of the reception data clear flag memory means 21 and 71 at reception of the output showing the presence of the abnormality of both means 22 and 72. Thus it is possible to easily cope with the abnormality of communication.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a link system for a programmable controller that exchanges data between a master station and a slave station via an interface module, and particularly to a link system for a programmable controller that exchanges data between a master station and a slave station. Regarding processing in case of communication abnormality.

(Prior art and problems to be solved by the invention) Conventionally, in the link system of this type of programmable controller, the partner station is in an abnormal state due to a no-communication error occurring due to power off, etc., or a parity error occurring. When this occurred, the data received from the other station was cleared. In the link system of a programmable controller, an interlock with the partner station is normally programmed, and even if the partner station is in a normal stopped state, the data will be cleared when the power is turned off. I couldn't do it. Therefore, in order to avoid such a situation, unnecessary costs are incurred, or it is not possible to perform repairs by turning off the power only to that part.

As a way to improve this inconvenient situation, instead of clearing the data when an error occurs, an error flag (internal relay) is set up in the CPU module and the user can process the data (clear/not clear) using the program. I was letting it happen.

However, the CPU module program that processes data using the abnormality flag has a problem in that as the number of input data points increases, the processing program also becomes large in capacity.

The present invention was made to solve these problems, and an object of the present invention is to provide a link system for a programmable controller that can be easily dealt with when a communication abnormality occurs.

(Means for Solving the Problems) In the programmable controller link system according to the present invention, the interface modules of the master station side and the slave station have reception data clear flag storage means in which a flag is set as a reference for clearing the reception data. and a received data checking means for checking whether there is an abnormality in the received data.

Furthermore, it has arithmetic means for resetting the data of the CPU module based on the ON signal of the flag of the received data clear flag storage means when there is an output indicating that there is an abnormality from the received data checking means.

(Operation) In the present invention, when the received data check means detects that an abnormality has occurred in the partner station, and the flag in the received data clear flag storage means is set and turned on, the calculation means Reset the received data to the CPU module.

(Embodiment) Fig. 1 is a block diagram showing the relationship between a master station and a slave station in an embodiment of the present invention, Fig. 2 is a block diagram of the entire link system of a programmable controller, and Figs. 3A and 3B. is a flowchart showing the operation of the interface module of FIG. 1, and FIG. 4 is an explanatory diagram showing a table of system data.

In FIG. 1, (lO) is the CPU module of the master station programmable controller (100), and (20) is its interface module (hereinafter referred to as IF module). The CPU module (lO)
(11), ROM (12), RAM (12), etc. The IF module (20) is composed of a shared RAM (21), a signal processing circuit (22) composed of a CPU, etc., and a serial port (23).

(60) is the slave station programmable controller (200)
(70) is its interface module (hereinafter referred to as IF module). C
The PU module (60) includes the CPU (61), RO
It consists of RAM (62), RAM (82), etc. The IF module (70) has a shared RAM (71
), a signal processing circuit (72) consisting of a CPU, etc., and a serial board (73).

As described above, the hardware configuration of the programmable controller of the master station and the hardware configuration of the programmable controller of the slave station are basically the same, but their functions are different as will be described later.

As shown in FIG. 2, the overall configuration of the programmable controller link system includes a master station programmable controller (10G) and a plurality of slave station programmable controllers (200) connected via a bus.

Now, returning to Figure 1 again, we will explain the IF module (2) of the master station.
The operation of step 0) will be explained based on the flowcharts of FIGS. 3A and 3B.

Signal processing circuit (22) of the IF module (20) of the master station
performs a self-diagnosis on its own system after it is powered on (SO). In this self-diagnosis, R in the arithmetic circuit is
Check whether OMSRAM, transmission boat, transmission power supply, etc. are normal. If it is normal (St), proceed to the next step and check whether the system data setting of the CPU module (10) is completed (S2
).

Here, when the system data settings for the CPU module (lO) are completed, the shared RA
The configuration is such that a setting completion flag (SF) is set in M (21), and therefore, the signal processing circuit (22) checks whether the flag (sp) is set or not, and the CPU module ( 10) Determine whether the system data setting is completed.

This system data, as shown in the explanatory diagram of Fig. 4,
It consists of the large blade head address, manual points, blade head address, and output points for each slave station.

Once the system data settings for the CPU module (10) have been completed, next the CPU module (10) RA
Read the contents from M (13) and store it in the shared RAM.
(21) (S3).

Next, check the own station settings (S4). The contents of this self-station setting check include checking the station numbers of the master station/slave station, collating the number of transmission points, and spring checking of the start address. If it is determined that there is an abnormality (S5), the process returns to step (S2) and waits for the setting of new system data' to be corrected.

Next, when it is determined that the own station settings are normal (S5),
It is determined whether the link confirmation sequence is normal (S6). Although the details are omitted here, no-communication abnormalities, parity abnormalities, setting abnormalities, etc. are checked, and if an abnormality is found, the process returns to step (S2) and new system data is set. Once the link verification sequence is complete (S
7) Set the link confirmation completion flag (CF) (S
8).

Thereafter, transmission data is read from the CPU module (IO) and read through the shared RAM (S9), and data is transmitted and received according to the communication sequence (810).

Here, the corresponding data is sequentially transmitted to each slave station,
Next, data from the slave station is received. At that time, if there is no communication error or parity error (Sll), the received data is written to the common RAM (21). Common RAM (2
The received data written in 1) is sent to the CPU module (l
O) is written to RAM (13) (812).

Next, it is checked whether the restart flag (RF) is set (S13). This restart flag (RF) is set when changing a program, etc., and is instructed by the CPU module (IO).

If the restart flag is not set, the process returns to step (S9), reads the transmission data from the CPU module (10), and repeats transmission and reception.

If the restart flag is set, reset the link confirmation completion flag (CP) (514), then return to step (S2) and set the setting completion flag (SP) again.
is set, and if so, the newly set system data is read (S3). The same operation is repeated below.

On the other hand, if a no-communication error, parity error, etc. occurs (
sti), then check whether the received data clear flag (ZF) is set and turned on (
S15). This received data clear flag (2F) is a flag that is set or reset in advance in the common RAM (21) by the user via the CPU module (IO). When the receive data clear flag (ZF) is set and turned on, the shared RAM (21)
81B).

After this step (S113), or if the received data clear flag (zp) is turned off, it is next checked whether the restart flag (RP) is set and turned on (S17). Restart flag (RF
) is off, the process returns to step (815) and steps (815) - (81B) - (817)
Alternatively, the loop of steps (S15)-(S17) is repeated. If the restart flag (RF) is on, the step (S
Return to 2).

On the other hand, the IF module (70) of the slave station also operates in the third mode.
This is similar to the flowcharts in Figures A and 3B, and in step (810) data is received from the master station and transmitted to the master station. If the transmission data from the station includes a link confirmation sequence (in this case, the settings of the master station have been changed) (SLOa), the link confirmation completion flag (CP) is reset (SlOb) and then step (S2 ),
Repeat the same operation as above to install the CPU module (60
) and change the system by setting new system data.

As described above, when changing the system at each of the master station and slave station, the restart flag (R3) is set and the link data of the CPU module is read. Also, when synchronizing the master station and slave stations, if the system data is changed on the master station, a link confirmation sequence is sent to the slave station and the slave station's system is changed at that timing. There is.

Furthermore, the user can set or reset a received data clear flag (ZP) in the IF module to cope with the occurrence of an abnormal condition at the transmission destination station.

(Effects of the Invention) As described above, according to the present invention, the user can set or reset the received data clear flag in the IF module, and when an abnormal state occurs in the transmission destination station, the CPU
Since the received data to the module is cleared or left as is, it is easy to respond when an abnormality occurs in the partner station.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a programmable controller showing the relationship between a master station and a small station in an embodiment of the present invention, FIG. 2 is a block diagram of the entire link system of the programmable controller, and FIGS. 3A and 3B are block diagrams of the programmable controller. FIG. 4 is a flowchart showing the operation of the IF module shown in FIG. 1, and FIG. 4 is an explanatory diagram showing a table of system data.

Claims (1)

[Claims] (1) It has a programmable controller as a master station and a programmable controller as a slave station, each programmable controller is equipped with a CPU module and an interface module, and data is exchanged between the master station and slave stations via the interface module. In a programmable controller link system that performs It is characterized by having a received data checking means, and a calculation means for resetting the data of the CPU module based on the ON signal of the flag of the received data clear flag storage means when there is an output indicating that there is an abnormality from the received data checking means. A programmable controller link system.