JPH02254541A - Control system for conditional branch instruction - Google Patents

Abstract

PURPOSE:To minimize the number of execution cycles at the time of success of conditional branch to increase the execution speed by using one register of another register group to share the branch destination address calculated at the time of decoding a conditional branch instruction and performing decision of the branch condition and copy of the branch destination address to the instruction address for success of the branch condition in the same cycle. CONSTITUTION:Either of at least two registers 4-2 and 4-3 where operand address A is stored is used as the register where a branch destination address B of the instruction to be fetched at the time of success of the branch condition is stored. Decision of the branch condition and copy of the branch destination address B to an instruction address C at the time of success of the branch condition are performed in the same cycle. Thus, the amount of hardware is reduced, and the cycle to set the branch destination address from a private register to the instruction register is unnecessary because the private register is provided, and the number of execution cycles for success of the condition is minimized to increase the execution speed.

Description

[Detailed description of the invention] [e&required] Regarding a control method for conditional branch instructions in a computer equipped with an address counter n mechanism, the purpose of this invention is to minimize the number of execution cycles when a conditional branch is established and speed it up. The branch destination address calculated when decoding the conditional branch instruction is
By using one of the other registers that stores the operand address necessary for condition judgment, it is shared, and the judgment of the branch condition and the copying of the branch destination address to the instruction address when the branch condition is met can be performed in the same cycle. Configure it to do so.

[Industrial Field of Application] The present invention relates to a control system for conditional branch instructions in a computer equipped with an address calculation mechanism.

In recent years, with the demand for faster computer systems, pipeline control has become common as a method for interpreting and executing instructions, but conditional branch instructions that disrupt the flow of pipes have become a bottleneck to speeding up. It is desirable to reduce the number of execution cycles as much as possible.

[Prior Art] Pipeline control, which has been implemented in recent years in response to the demand for faster computer systems, divides the interpretation and execution of instructions into several stages, and each stage mechanism handles the execution of a certain instruction. After that, the next instruction is executed at that stage without waiting for the completion of execution at all stages of this instruction. Regarding branch instructions where branching or non-branching is determined depending on the memory contents of the address indicated by , which is a bottleneck in speeding up the process.

FIG. 5 shows a configuration diagram of the conventional system.

In Figure 5, 1 is an instruction buffer that buffers instructions fetched from memory 6, 2 is an instruction decoder that interprets the fetched instructions, and 3 is a computer that calculates operands and branch destination addresses from general-purpose registers and the address of the instruction being executed. This is the address calculation section. 4 is an address register, which includes an instruction address register 4-1, a first operand address register 4-2, a second operand address register 4-3, and an instruction branch address register 4-1.
Equipped with 4 types of 4.

Further, 5 is an instruction execution unit, which performs operand read/write and various operations according to the decoding result of the instruction decoder 2. Furthermore, 6 is a memory as a main memory.

Next, the operation will be explained with reference to the timing explanatory diagram of FIG.

Instruction buffer 1 is transferred from memory 6 to instruction address register 4.
The instruction addressed by -1 is fetched and buffered. If the decoded result is a conditional branch instruction, the instruction decoder 2 instructs the address calculation unit 3 to calculate the address of an operand necessary for condition determination. The operand addresses calculated by the address calculation unit 3 are the first and second operand addresses.
One of the operand address registers 4-2 and 4-3 is set.

Next, the instruction decoder 2 instructs the address calculation unit "3 to calculate the address of the instruction to be fetched when the branch condition is met, that is, the branch destination address, and the calculation result is stored in the dedicated instruction branch destination address register 4-4. is set to

When the above address calculation is completed, assuming that the branch instruction is not taken, the instruction address register 4-1 is counted up, and the next instruction specified by the counted up instruction address is fetched from the instruction buffer 1. .

On the other hand, the instruction execution unit 5 reads the operand on the memory 6 when the operand address necessary for determining the branch condition is determined, and then determines whether the branch condition is met.

If the branch condition is not satisfied, the operations after decoding the next instruction buffered in the instruction buffer 1 at that time are executed.

Conversely, if the branch condition is met, the value of the instruction branch destination address register 4-4 is transferred to the instruction address register 4-1.
and re-execute from fetching the branch destination instruction.

[Means for Solving the Problems] However, in such a conventional conditional branch instruction control method, a dedicated register 4-4 is required to store the calculation result of the branch destination address, and When determining this, there is a problem in that the number of execution cycles increases because the instruction is fetched and re-executed after the value of the dedicated register storing the instruction branch destination address is stored in the instruction address register.

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a control method for conditional branch instructions that minimizes the number of execution cycles when a conditional branch instruction is established and increases speed. do.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, when a conditional branch instruction is decoded, the present invention calculates the operand address A necessary for determining the branch condition and sets it in a register, and then calculates the branch destination address B of the instruction to be fetched when the branch condition is met. and set it in the register, and on the other hand, the operand address A necessary for determining the branch condition.
When the branch condition is established, the operand on the memory is read to determine whether the branch condition is met, and if the branch condition is not met, the next instruction is fetched using the incremented instruction address C, and conversely, when the branch condition is met, the branch destination is The subject is a control method for a conditional branch instruction that fetches an instruction using address B as the instruction address.

Regarding the control system for such conditional branch instructions, in the present invention, one register storing the branch destination address B is shared with one of at least two registers 4-2 and 4-3 storing the operand address A. In addition, the determination of the branch condition and the copying of the branch destination address B to the instruction address C when the branch condition is satisfied are performed in the same cycle.

[Operation] In the conditional branch instruction control method according to the present invention having such a configuration, the branch destination address of the instruction is not stored in a dedicated register, but is stored in one of at least two operand registers in an empty state. Since the branch condition is judged and the branch destination address is copied from the operand register to the instruction register in the same cycle, the amount of hardware can be reduced. The provision of a dedicated register eliminates the need for a cycle for setting a branch destination address from a conventional dedicated register to an instruction register, and it is possible to minimize the number of execution cycles when a condition is met and increase speed.

Embodiment FIG. 2 is a block diagram of an embodiment of the present invention.

In FIG. 2, 1 is an instruction buffer for buffering instructions fetched from the memory 6, and 2 is an instruction buffer 1.
3 is an address calculation unit that calculates operands and branch destination addresses from general-purpose registers and the address of the instruction being executed; 4 is an address register; Address register 4-1, address register 4-1 for first operand
There are three types of address registers 4-3 for operands 2 and 4-3 for second operands, and no address register for branching is provided as in the conventional art. Reference numeral 5 denotes an instruction execution section, which performs operand reading, writing, and various operations according to the instruction decoding result by the instruction decoding section 2. Furthermore, 6 is a memory as a main memory.

In the embodiment of the present invention shown in FIG. 2,
Control shown in the branch instruction operation timing explanatory diagram of FIG. 3 is performed for the conditional branch instruction.

First, the instruction buffer 1 fetches the instruction addressed by the instruction address register 4-1 from the memory 6 and buffers it. If the decoded result is a conditional branch instruction, the instruction decoding unit 2 instructs the address calculation unit 3 to calculate the address of the operand in the memory 6 necessary for condition determination. The result of the operand address calculation by the address calculation unit 3 is set in either the first or second operand address register 4-2 or 4-3.

Subsequently, the instruction decoding unit 2 instructs the address calculation unit 3 to calculate the address of the instruction to be fetched when the branch condition is satisfied. The branch destination address obtained by this address calculation is set in the register of the first and second operand address registers 4-2 or 4-3 that is not used as an operand address at the time of execution of this instruction. .

When the above address calculation is completed, the instruction address register 4-1 counts up assuming that the branch condition is not satisfied, and the instruction buffer 1 fetches the next instruction based on the counted up instruction address.

On the other hand, the instruction execution unit 5 reads the operand on the memory 6 when the operand address is determined, and then determines the branch condition. If the branch condition is not satisfied, the operations after decoding the instruction buffered in the instruction buffer 1 at that time are executed. Conversely, if the branch condition is satisfied, the value of the instruction branch destination address stored in either operand address register 4-2 or 4-3 during the same cycle as the judgment of this branch condition is stored in the instruction address register. 4-1, and then re-executes from instruction fetch.

Now, if we compare the operation timing of the branch instruction according to the present invention shown in FIG. 3 with the conventional operation timing shown in FIG. The number of cycles is the same, but when the branch condition in (a) is satisfied, the conventional example shown in Figure 6 requires three cycles for operand fetch, branch condition determination, and instruction address set. According to the present invention shown in FIG. 3, only two cycles are required for determining the operand fetch condition and setting the instruction address.

Next, the embodiment of FIG. 2 will be specifically explained using a TH instruction (Test Half Word), which is one of the conditional branch instructions.

The format structure of the TH instruction is as shown in Figure 4.
This is a 4-byte long instruction with a P code of 96. This T
In the H instruction, the base part B (2 bits) of the 2nd byte
The register value and index part X (
Refers to the halfword (16 bits) in the memory of the address obtained by adding the register value indicated by the 2nd and 3rd bytes (12 bits) and the displacement (12 bits) indicated directly in the instruction. do.

The halfword value in this memory is the branch condition, and if the value indicating the branch condition is O, the address where this instruction is stored is the address Ad directly specified in the instruction.
Branch to the address to which r (, 8 bits) is added.

Conversely, if the value of the branch condition is other than O, the value added to the address where this instruction is stored plus the instruction length 4 becomes the next instruction.

Regarding such a TH command, the control shown in FIG. 2 will be explained in detail as follows. Note that the numerical values in FIG. 2 are expressed in hexadecimal.

It is now assumed that the TH instruction shown in FIG. 4 is stored at address a on memory 6, and that instruction address register 4-1 holds the value of address a.

First, 4-byte data on the memory 6 starting from the address a set in the instruction address register 4-1 at this time is fetched into the instruction buffer 1. The instruction decoding unit 2 decodes that this instruction is a TH instruction from the value 96 of the first byte, and sends the first instruction to the address calculation unit 3.
Instructs calculation of operand address C.

The address calculation unit 3 is the 2-byte value 62 following the OP code.
00 to the value of the first register, the value of the second register, and the displacement value 200 directly specified in the instruction.
is added to obtain the value C of the first operand address, and the calculated value of the operand address C is stored in the first operand register 4-2.

Next, the remaining 1 byte of Adr value 31 and the value a of the instruction address register 4-1 at that time are added (a+3
1) and stores this (a+31> in the second operand address register 4-3 as the instruction address to be fetched when the branch condition is satisfied.

After completing the above address calculation and register setting,
The instruction address register 4-1 counts up by the instruction length 4 and becomes (a+4>), and the instruction buffer 1 fetches the instruction XX at the address (a+4>).

On the other hand, the instruction execution unit 5 reads the operand YYYY on the memory 6 addressed by the value C stored in the first operand address register 4-2, and then determines the branch condition.

Here, if the value of the operand YYYY is other than O, the branch condition is not satisfied, so the operations after the decoding of the instruction X× fetched into the instruction buffer 1 at that time are executed.

Conversely, if the value of operand YYYY is O, it is determined that the branch condition is satisfied, and the address l for the second operand is set during the same cycle.
Copy the instruction branch destination address value (a+31> stored in the register 4-3 to the instruction address register 4-1, fetch the data ZZ existing at address (a+31) as the next instruction, and re-execute it. .

It should be noted that, although the above-described embodiment takes a specific example of the TH instruction, the present invention is not limited thereto, and can be applied as is to any appropriate conditional branch instruction.

[Effects of the Invention] As described above, according to the present invention, there is no need for a dedicated register for storing the calculation result of a branch destination address, so that the amount of hardware can be reduced.

In addition, it is possible to determine the branch condition and copy the branch destination address when the branch condition is met to the instruction address in the same cycle, minimizing the number of execution cycles for conditional branch instructions, which can become a bottleneck in pipeline control. It is possible to reduce the burden caused by conditional branch instructions and achieve higher speeds.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is a diagram illustrating the configuration of an embodiment of the present invention; Fig. 3 is a diagram illustrating the branch operation timing of the present invention; - Mat explanatory diagram; FIG. 5 is a configuration diagram of the conventional system; FIG. 6 is an explanatory diagram of the operation timing of the conventional system. In the figure, 1: Instruction buffer 2: Instruction decoding section 3 Near address calculation section 4 Near address register 4-1: Instruction address register (FA) 4-2 = 1st
Operand address register (DA) 4-3 = 2nd operand address register (SA) 5: Instruction execution unit 6: Memory

Claims (1)

[Claims] (1) When a conditional branch instruction is decoded, calculate the operand address (A) necessary for determining the branch condition, set it in a register, and then set the branch destination address (B) of the instruction to be fetched when the branch condition is met. On the other hand, when the operand address (A) necessary for determining the branch condition is determined, the operand on the memory is read to determine whether the branch condition is met, and if the branch condition is not met, the In the conditional branch instruction control method, the next instruction is fetched according to the incremented instruction address (C), and when a branch condition is established, the instruction is fetched using the branch destination address (B) as the instruction address (C). The register storing the branch destination address (B) is shared with one of the at least two registers (4-2, 4-3) storing the operand address (A), or the branch condition is judged and the branch condition is met. A control method for a conditional branch instruction, characterized in that a branch destination address (B) is copied to an instruction address (C) in the same cycle.