JPH01292551A - Memory retention status check device - Google Patents

Abstract

PURPOSE:To correctly check the storage holding state of a memory by estimating the remaining terminal voltage of a capacitor measured at application of a power supply and necessary for checking said storage holding state based on the terminal voltage of the capacitor measured after a fixed time and the charging characteristics. CONSTITUTION:When a power supply is applied again at the time ton, the control voltage E1 reaches the level of the prescribed voltage VE1 of a logic circuit in a short period. At the same time, the memory back-up voltage E2 rises up to the level of the voltage VE2 from the level of the remaining voltage V0 of a capacitor. The value of the VE2 is equal to the value obtained by subtracting the value of the forward voltage of a diode D1 from the value of the control power supply voltage V1. Then the level of the terminal voltage EC of the capacitor C rises up based on the time constant obtained between a resistance R and the capacitor C. A CPU 2 obtains the back-up voltage V0 at the second application of the power supply and compares this with the minimum voltage VS necessary for back-up of a memory M. Then the alarm output, etc., are processed when V0<VS is satisfied. In such a way, the voltage V0 is compared with the terminal voltage of the capacitor C when a fixed time passed after the application of the power supply. Thus the storage state of the memory M is checked.

Description

[Detailed Description of the Invention] [Objective of the Invention 1 (Industrial Application Field) This invention provides a memory retention state checking device for checking the memory retention state of a memory whose power is backed up by a capacitor when the power is turned on again. Regarding.

(Prior Art) In a control device such as a programmable controller, a memory (for example, a CMOS memory) whose power is backed up by a capacitor is used to hold data and programs.

The memory retention state of this type of memory depends on the value of the residual terminal voltage of the power supply backup capacitor, and the value of the residual terminal voltage gradually decreases while drawing a predetermined time constant curve during power interruption.

Therefore, in a control device using this type of memory, the residual terminal voltage of the memory power backup capacitor when the power is turned on again is compared with the specified voltage required to retain the memory in the memory. A memory retention state checking device is provided for checking the retention state.

By the way, the value of the terminal voltage of the memory power backup capacitor immediately starts to rise following a predetermined time constant curve when the power is turned on again, whereas
etc. cannot operate until its driving voltage reaches the specified value after the power supply official.

Therefore after power cycling the microprocessor.

If the terminal voltage of the power backup capacitor is detected and compared with the specified voltage after waiting for the logic IC or the like to operate, the memory retention state cannot be accurately checked.

Therefore, in the conventional memory retention status check device,
After the power is turned on, until the microprocessor, logic IC, etc. are activated, a method is adopted in which the terminal voltage of the memory power supply backup capacitor is maintained at the state at which the power was turned on again.

(Problem to be Solved by the Invention) However, such a conventional terminal voltage holding type memory retention state checking device stops charging the power backup capacitor for a predetermined time after the power is turned on again, and then stops charging the power backup capacitor. In this case, a switching circuit is required to automatically perform charging, which poses the problem of complicating the hardware configuration of the system.

An object of the present invention is to stop charging the power backup capacitor for a predetermined period of time after the power is turned on again, and then automatically start charging. To provide a memory retention state checking device capable of accurately checking a memory retention state.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention reduces the residual terminal voltage of the memory power backup capacitor when the power is turned on again to maintain the memory of the memory. In a memory retention state checking device that checks the memory retention state of the memory by comparing it with a specified voltage, the capacitor residual terminal voltage required for checking the memory retention state of the memory when the power is turned on again is determined when the power is turned on. The memory retention state is checked based on the estimated residual terminal voltage based on the capacitor terminal voltage and the charging characteristic of the capacitor charging circuit at the time when a certain period of time has elapsed in the subsequent charging transition period. It is something to do.

(Function) According to this configuration, the residual terminal voltage of the capacitor when the power is turned on again is calculated based on the capacitor terminal voltage after a certain period of time has elapsed during the charging transition period after the power is turned on, and the charging characteristics of the capacitor charging circuit. Since this is estimated, the backup capacitor can be charged immediately when the power is turned on again, and as a result, the memory retention status of this type of memory can be accurately checked without using a complicated switching circuit. .

(Embodiment) FIG. 1 is a block diagram showing the hardware configuration of a programmable controller to which a memory retention state checking device according to the present invention is applied.

In the figure, the memory M is composed of volatile memories such as CMO8 and RA'M, and after the power is cut off, the power is backed up by a large capacity capacitor (such as a supercapacitor) C.

The diode D1 prevents backup current from flowing backward when the power is turned off, and in order to reduce the forward voltage drop when the power is turned on, the diode D1 may be replaced with a transistor.

Since the capacitor C has a large capacity, the resistor R is used to limit the inrush current when the power is turned on again, and to prevent delays in power supply startup time and damage to power supply related elements due to excessive charging current. belongs to.

The terminal voltage EC of the capacitor C can be read through the A/D converter 1 into a CPU 2 mainly composed of a microprocessor, ROM, and RAM.
As will be described later, calculations necessary for checking the storage retention state of the memory M are performed.

If the memory retention state is found to be abnormal as a result of checking, processing such as issuing an alarm output A is performed.

That is, as shown in FIG. 2, in the CPtJ2, as an initial process immediately after the power is turned on, the value of the terminal voltage EC of the capacitor C is A/D converted, and this is stored as ■1 (step 201). Every time the time to elapses, the second. A third A/D conversion process is performed, and the value of the terminal voltage EC at that time is stored as v2, V, 3 (steps 202 and 203).

Thereafter, using the values 1 to V3, the value of the residual terminal voltage V(,) of the capacitor C when the power is turned on again is estimated by calculation based on the following equation (step 204).

If the value of the residual terminal voltage VO estimated by the calculation is less than the specified voltage VS necessary for memory retention in the memory M (step 205 NO), an alarm output is issued as a backup voltage abnormality, or a necessary alarm is issued. Processing etc. are performed (step 206).

Next, the operation of the memory retention state checking device having the above configuration will be explained with reference to the voltage waveform diagram in FIG.

FIG. 3 shows the control power supply voltage El in FIG.

5 is a voltage waveform diagram showing temporal changes in memory backup voltage E2 and capacitor terminal voltage EC. FIG.

Before the power is turned on again, the control power supply voltage E
The value of 1 is OV, but the value of memory backup voltage E2 is backed up by capacitor C, so
Maintains a predetermined potential.

At this time, the current to the memory M is generally a very small value (on the order of microamperes or less), and the value of the current limiting resistor R is generally from several ohms to several 100 ohms, so when the power is turned on again, The value of the memory backup voltage E2 before TON is approximately equal to the value of the capacitor terminal voltage EC.

When the power is turned on again at time t on in this state, the value of the control power supply voltage E1 reaches the specified voltage VEI of the logic circuit (generally 5V) in a short time, and the value of the memory backup voltage E2 increases due to the residual voltage of the capacitor. Terminal voltage Vo
It increases from to VB2.

Here, the value of VB2 is the value obtained by subtracting the value of the forward voltage of diode D1 from the value of control power supply voltage V1.

Thereafter, the value of the terminal voltage EC of the capacitor C increases according to the following equation based on the charging characteristic determined by the time constant of the resistor R and the capacitor C and the voltage VE2.

EC=VE2×(1-e-=)...(1
) Here, TC is a time constant determined by the resistance value R of the resistor R and the capacitance value C of the capacitor C (TC=CXR).

Each time after power on 1. Assuming that the values of the capacitor terminal voltage EC at ~t3 are 1 to 3, 1 to V3 exist on the hole (1) described above.

Also, if tR is the time it takes for the CPU 2 to first read the value of the capacitor terminal voltage EC through the A/D converter 1 after the power is turned on, then the value of the time tR is the reset time of the CPU 2 and the first reading after the CPU operates. This becomes the sum of time, and this value is approximately constant.

On the other hand, the subsequent reading interval t of the capacitor terminal voltage EC
o is kept at a constant value by a timer function built into the CPU 2.

For example, if t R = t D, the following condition holds true from the exponential characteristic of equation (1) described above.

K=Constant When the equation (2) is transformed, the CPU 2 can calculate the backup voltage Vo at the time of turning on the power again (ton) based on the equation (3).

Here, equation (3) can be applied regardless of changes in the time constant.

Next, the CPU 2 compares the value of the residual terminal voltage Vo estimated by calculation with the minimum voltage VS required for memory backup, and if Vo<VS, it determines that the memory backup power supply voltage is insufficient and performs processing such as outputting an alarm. It is.

As described above, according to the device of this embodiment, the value of the capacitor residual terminal voltage Vo, which is required to check the storage retention state of the memory when the power is turned on again, is set at the time t1 when a certain period of time has elapsed in the charging transition period after the power is turned on. ．． t2. It is estimated based on the capacitor terminal voltages 1, v2, v3 at t3 and the charging characteristics of the capacitor charging circuit, and the estimated residual terminal voltage is used to check the memory storage retention state. Therefore, charging of the capacitor C can be started immediately after the power is turned on again, and as a result, there is no need to provide a complicated charging switching circuit as in the conventional device.

In addition, in Fig. 3, if the residual terminal voltage Vo at time t, R≦, tD is set to Vo・-, then the capacitor residual terminal voltage Vo can also be determined by linear interpolation as shown by the following equation. .

Further, when the time constant TO is sufficiently large compared to the time tR, the value of Vl becomes approximately equal to Vo, so that it is possible to roughly determine the backup power supply voltage based only on Vl.

In the above explanation, since the capacity of the backup capacitor C is on the order of O, OIF ~ 1, OF level, the value of the time constant TO is generally a value of about several seconds to several hundred seconds, and as a result, the value of the time constant TO is on the order of several seconds to several hundred seconds. This allows sufficient processing.

Next, FIG. 4 is a block diagram showing an embodiment in which a CPU 3 with an analog input is used.

In this embodiment, the backup current when the power is turned off is A
In order to prevent leakage to the input side of the /D converter as shown by the arrow IL, a diode D2 is added.

If the pull-up resistor Rχ connected to the control power supply voltage E1 is made sufficiently larger than the current limiting resistor R and smaller than the impedance of the analog input circuit, the voltage of the capacitor terminal voltage EC will be reduced by the forward voltage drop of the diode D2. can be calculated by correcting.

In each of the above embodiments, the memory retention state was checked using part of the functions of the CPU used to control the programmable controller. The process of calculating and estimating the residual terminal voltage of the backup capacitor when the power is turned on again based on the capacitor terminal voltage at the elapsed time and the charging characteristics of the capacitor charging circuit is carried out by a dedicated hardware circuit. Of course, you can do it. .

[Effect of the Invention J As is clear from the above explanation, according to the present invention, the residual terminal voltage of the capacitor when the power is turned on again, which is necessary for checking the storage retention state of the memory, is measured after a certain period of time has elapsed during the charging transition period after the power is turned on. Since the memory retention status of the memory was checked using the estimated residual terminal voltage based on the capacitor terminal voltage and the charging characteristics of the capacitor charging circuit at the time when the capacitor was turned on again, the capacitor was Therefore, the complicated switching circuit required in the conventional device is not required, and the hardware configuration can be simplified.

In addition, as in the example, if the capacitor terminal voltage is read multiple times at predetermined time intervals from the time the power is turned on, and the residual terminal voltage when the power is turned on again is estimated by calculation based on those values, the capacitance variation of the backup capacitor can be reduced. Alternatively, it is possible to correct the deviation of the charging characteristic curve due to secular change, etc., and to check the memory storage retention state more reliably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the hardware configuration of a programmable controller to which the present invention is applied, FIG. 2 is a flowchart showing the software configuration, and FIG.
FIG. 4 is a waveform diagram showing the signal states of each part in the figure, and FIG. 4 is a block diagram showing another embodiment of the present invention. 1...A/D converter 2.3...CPU M...Memory C...Memory power supply backup capacitor EC...
・Capacitor terminal voltage Co...Residual terminal voltage agent when power is turned on again
Patent Attorney Noriyuki Chika Agent Patent Attorney Yamashita −

Claims (1)

[Claims] (1) Memory retention state in which the memory retention state of the memory is checked by comparing the residual terminal voltage of the memory power backup capacitor when the power is turned on again with the specified voltage required for memory retention of the memory. In the checking device, the residual terminal voltage of the capacitor when the power is turned on again, which is necessary to check the storage retention state of the memory, is determined by the capacitor terminal voltage at the time when a certain period of time has elapsed during the charging transition period after the power is turned on, and the charging characteristics of the capacitor charging circuit. A memory retention state checking device characterized in that the memory retention state is checked using the estimated residual terminal voltage.