[go: up one dir, main page]

JPH01211935A - Probing device for wafer - Google Patents

Probing device for wafer

Info

Publication number
JPH01211935A
JPH01211935A JP63037277A JP3727788A JPH01211935A JP H01211935 A JPH01211935 A JP H01211935A JP 63037277 A JP63037277 A JP 63037277A JP 3727788 A JP3727788 A JP 3727788A JP H01211935 A JPH01211935 A JP H01211935A
Authority
JP
Japan
Prior art keywords
defective
pellet
pellets
wafer
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63037277A
Other languages
Japanese (ja)
Inventor
Kenichi Nagatome
永留 賢一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP63037277A priority Critical patent/JPH01211935A/en
Publication of JPH01211935A publication Critical patent/JPH01211935A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To measure the pellets on wafers efficiently by a method wherein only the pellets on several sample wafers are measured to set up assumed defective distribution regions so that the measurement of larger regions out of acceptable and defective pellets may be skipped over. CONSTITUTION:Within the title probing device 2, when multiple semiconductor pellets on multiple wafers 1 to be tested are successively probed to test the electric characteristics, if a pellet is disclosed to be defective, the pellet is marked with a defective mark. Besides, a mapping memory 8 storing the defective frequency distribution region of the pellets corresponding to the wafer shape as well as an assumed region setting up control circuit 12 setting up the assumed defective distribution regions by binary coding said regions in the region with the frequency exceeding specified value and the other region with the other frequencies are provided. Furthermore, a pellet measurement skip control circuit 13 making the defective marks only without performing the measurement process when the pellet positions of wafers 1 to be tested in the same lot to be measured after setting up the assumed defective distribution region are contained in the assumed defective distribution is provided. Through these procedures, the pellet can be measured efficiently even if the pellet yield of semiconductor wafers is unfavorable.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はウェーハのプロービング装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a wafer probing apparatus.

〔従来の技術〕[Conventional technology]

近年ICの目ざましい発達に伴い、ペレットの良・不良
を判定するICテスタやそれと組合せてウェーハ中のペ
レットを測定するためにプローブを当てるプロービング
装置もますます高性能化が要求され、高価なものとなっ
てきた。
With the remarkable development of ICs in recent years, IC testers that determine whether pellets are good or bad, and probing equipment that uses probes to measure pellets in wafers, are required to be more sophisticated and expensive. It has become.

一方、IC自体への低価格化の要求に対応して、ICI
ケ当りの測定時間の短縮化、複数個同時測定及びマシー
ンインデックスの短縮等の測定技術の向上がますます要
求されてきた。
On the other hand, in response to the demand for lower prices for ICs themselves, ICI
There has been an increasing demand for improvements in measurement technology, such as shortening the measurement time per piece, simultaneous measurement of multiple pieces, and shortening the machine index.

従来のプロービング装置は、ウェーハ上の全ベレットを
、1ケ又は複数個同時に電気的特性測定を行うためのハ
ンドリング機構と、電気的特性試験評価装置(以下IC
テスタと呼ぶ)からの不良信号を受はウェーハ上の各々
のペレットに対し伺らかの方法で不良マークを付加する
装置であった。
Conventional probing equipment includes a handling mechanism for simultaneously measuring the electrical characteristics of one or more pellets on a wafer, and an electrical characteristics testing and evaluation device (hereinafter referred to as IC).
It was a device that received a defect signal from a tester (called a tester) and added a defect mark to each pellet on the wafer using a certain method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したウェーハのプロービング装置は、基本的には全
ペレットの電気的特性試験を行っているので、ICの開
発段階におけるウェーハ・ベレットのように良品率、い
わゆる歩留りの悪いウェーハロッドの場合には測定時間
が無駄に長くかかり、前工程への品買データのフィード
バック、従ってICの開発が遅れる等の問題があった。
The above-mentioned wafer probing equipment basically tests the electrical characteristics of all pellets, so in the case of wafer rods that have a poor yield, such as wafer pellets during the IC development stage, it is difficult to measure them. There were problems such as it took an unnecessarily long time, and feedback of purchasing data to the previous process was delayed, thereby delaying IC development.

また、低歩留対策としてプロービング装置ヲ多く設置す
ると量産段階になると一般にICのベレット歩留が向上
するので大量の専用のブロービング装置が余剰設備とな
るという問題があった。
Furthermore, if a large number of probing devices are installed as a measure against low yield, the pellet yield of IC will generally improve at the mass production stage, so there is a problem that a large number of specialized probing devices will become redundant equipment.

本発明の目的は、半導体ウェーノ・のベレット歩留りの
悪い場合にも効率よく測定できるウェーハのブロービン
グ装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer blowing apparatus that can efficiently measure semiconductor wafers even when the pellet yield is poor.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のウェーハプロービング装置は、複数の被試験ウ
ェーハ上の複数の半導体ベレットにプローブを順次轟て
て電気的特性試験を行い前記ベレットが不良の場合には
該ベレットに不良マークを付加するウェーハのブロービ
ング装置において、前記被試験ウェーハのサンプル枚数
のペレットの不良度数分布領域をウェーハ形状に対応し
て記憶するマツピングメモリ部と、前記不良度数分布領
域を所定の度数以上とそれ以外の度数とを2値化して推
定不良分布領域を設定する推定領域設定制御回路と、前
記推定不良分布領域の設定後に測定する同一ロッドの前
記被試験ウェーへのペレットの位置が前記推定不良分布
領域内にある場合は測定せずに前記不良マークの付加の
みを行うベレット測定スキップ制御回路とを設けた測定
領域制御部を有して構成されている。
The wafer probing apparatus of the present invention sequentially bombards a plurality of semiconductor pellets on a plurality of wafers to test electrical characteristics, and if the pellets are defective, a defective mark is added to the pellets. In the blowing device, a mapping memory unit stores a failure frequency distribution area of pellets of a sample number of the tested wafer in correspondence with the wafer shape; an estimated area setting control circuit that binarizes the estimated failure distribution area to set an estimated failure distribution area, and a position of a pellet of the same rod to the tested wafer to be measured after setting the estimated failure distribution area is within the estimated failure distribution area. In this case, the measuring area control section is provided with a pellet measurement skip control circuit that only adds the defect mark without performing measurement.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

ウェーハのブロービング装置2は、被試験ウェーハlの
上のベレットに当てるグローブ9aを有しICテスタ部
3と接続するベレット測定部9と、被試験ウェーハlの
搬送、認識及びステージ制御等を制御するグローバ制御
部7と、入力端がICテスタ部3の良・不良判定回路1
1の不良信号SFを受は出力端がスキップ信号Ssxを
出力する測定領域制御部15とを有している。
The wafer blowing device 2 has a glove 9a that is applied to the pellet on the wafer under test l, and a pellet measurement section 9 that is connected to the IC tester section 3, and controls the transportation, recognition, stage control, etc. of the wafer under test l. a glober control section 7 to perform
The measurement area control section 15 which receives the defective signal SF 1 and whose output end outputs a skip signal Ssx is provided.

測定領域制御部15は、不良信号SFを受けてベレット
不良の推定領域を設定する推定領域設定回路12と、そ
の分布領域データSDを記憶するマツピングメモリ部8
と、プローバ制御信号Scとマツプ信号Sns  を入
力して測定のスキップ信号Ssx  を出力する測定ス
キップ制御回路13とを有している。
The measurement area control section 15 includes an estimation area setting circuit 12 that receives the defect signal SF and sets an estimation area of pellet defects, and a mapping memory section 8 that stores the distribution area data SD.
and a measurement skip control circuit 13 which inputs a prober control signal Sc and a map signal Sns and outputs a measurement skip signal Ssx.

次に、ウェーハのブロービング装置によるペレットの測
定手順を説明する。
Next, a procedure for measuring pellets using a wafer blowing device will be described.

第2図(a)〜(C)は第1図のブロックの動作を説明
するための初期、サンプル試験後の不良度数分布領域及
びウェーハロッドの推定不良分布領域に対応するマツピ
ングメモリ部の状態図である。
FIGS. 2(a) to (C) are states of the mapping memory section corresponding to the initial failure frequency distribution area after sample testing and the estimated failure distribution area of wafer rods for explaining the operation of the blocks in FIG. 1. It is a diagram.

まず、複数の被試験ウェーハよりなるウェーハ・ロフト
について推定不良分布領域を設定するために、3枚のウ
ェーハのサンプリング試験を行う。
First, a sampling test is performed on three wafers in order to set an estimated failure distribution area for a wafer loft consisting of a plurality of wafers to be tested.

プローパ制御信号Scは搬送信号S T I  認識信
号SN及びステージ制御信号Ssを順次出力させ一 て、被試験ウェーハをベレット測定部9にセットし、プ
ローブ9aを指定されたベレットに当てる。
The properr control signal Sc sequentially outputs the carrier signal S T I recognition signal SN and the stage control signal Ss, and the wafer to be tested is set in the pellet measuring section 9, and the probe 9a is applied to the specified pellet.

定回路11は規格値に対応して不良と判定した場合は、
不良信号Svを不良マーク発生回路14と測定領域制御
部15に供給する。
If the constant circuit 11 is determined to be defective in accordance with the standard value,
The defective signal Sv is supplied to the defective mark generation circuit 14 and the measurement area control section 15.

不良マーク信号SMは不良マーク発生装置を駆動し、当
該ベレットに何らかの不良マーク表示付加を行い、順々
に次のペレットの測定に移る。    ゛同時に不良信
号SFは、推定領域設定回路12を通して、第2図G)
に示すように初期状態が良品″0”に設定されたウェー
ハ領域を有するマツピングメモリ部8上の当該ベレット
位置へ、不良の数”1”を記憶させる。
The defective mark signal SM drives the defective mark generator, adds some defective mark to the pellet concerned, and then moves on to measuring the next pellet in sequence.゛At the same time, the defective signal SF is sent through the estimation area setting circuit 12 (G in Fig. 2)
As shown in FIG. 3, the number of defects "1" is stored in the corresponding pellet position on the mapping memory section 8 which has a wafer area whose initial state is set to "0" as a non-defective product.

サンプル数3枚のウェーハlこついて、測定し、マツピ
ングメモリ部8のベレット対応位置に累積不良度数(θ
〜3)を記憶させる。
Three wafers are sampled, measured, and the cumulative defect count (θ
~3) is memorized.

第2図(b)に示すように、ウェーハ領域W1は、′″
0″の良品ベレット領域と1〜3″′の不良度数分布領
域Aに区分される。
As shown in FIG. 2(b), the wafer area W1 is
It is divided into a non-defective pellet area of 0'' and a defective frequency distribution area A of 1 to 3''.

次に、予め不良度数“l”以下を良品“0”に、12“
以上を不良”l”に2値化する処理を推定領域設定回路
12にて行い、第2図(C)に示すように、前体である
クエーハ日ットの推定不良分布領域Bを有するウェーハ
領域W2をマツピングメモする。
Next, in advance, the defective frequency “l” or less is classified as a non-defective product “0”, and 12”
The process of binarizing the above into defective "l" is performed by the estimation area setting circuit 12, and as shown in FIG. Make a mapping memo for area W2.

サンプル試験によって、ウェーハ領域W2 の推定不良
分布領域Bの面積が50%以上の場合には、被測定ベレ
ットの位置が推定不良領域B内に対応すると被測定ペレ
ットは測定せずにスキップして不良マークを付加し、次
のベレットの測定へと進む。
According to the sample test, if the area of the estimated defective distribution area B in the wafer area W2 is 50% or more, if the position of the pellet to be measured corresponds to the estimated defective area B, the pellet to be measured is skipped without being measured and declared defective. Add marks and proceed to measuring the next pellet.

また、B領域外に対応する良品の位置では、被測定ペレ
ットを測定し、工Cテスタ部3からの不良信号SFがあ
る場合のみ不良マークを付加し、次のベレットへと進む
Further, at the position of the non-defective product corresponding to outside the B area, the pellet to be measured is measured, and only when there is a defective signal SF from the work C tester section 3, a defective mark is added, and the process proceeds to the next pellet.

従って、被試験クエーハ内のベレットのうち、不良とな
る確率が多い大半のベレットの測定はスキップされ、5
0%上メモの面積の良品領域に対応するベレットのみが
測定されるので、試験効率は約2倍に改善される。
Therefore, the measurement of most of the pellets in the tested quafer, which have a high probability of being defective, is skipped, and the
Since only the pellets corresponding to the non-defective area of the 0% upper memo area are measured, the test efficiency is improved by about twice.

上述の実施例は、良品領域が少い時の場合を示したもの
であるが、逆に、良品領域が不良領域よりも多い場合は
、本ウェーハロッドの良品領域は測定せずスキップして
不良分布領域B内に対応するベレットのみを測定し、不
良信号SPがある場合のみ不良マークを付加し次のベレ
ットへと進む。
The above example shows a case where the number of non-defective areas is small, but conversely, if there are more non-defective areas than defective areas, the non-defective areas of this wafer rod are not measured and are skipped. Only the corresponding pellets within the distribution area B are measured, and only when there is a defective signal SP, a defective mark is added and the process proceeds to the next pellet.

ウェーハロッドが変るごとに、前述のサンプルウヱーハ
による推定不良分布領域の設定を行う。
Every time the wafer rod changes, the estimated defective distribution area is set using the sample wafer described above.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、数枚のサンプルウェーハ
上のベレットのみ測定して推定不良分布領域を設定して
、良・不良のうち面積の大きい領域を測定スキップして
それ以降のウェーノ・上のベレット測定を大巾に効率化
することにより、品質の早期向上及びIC開発の促進が
期待できるという多大な効果がある。
As explained above, the present invention measures only the pellets on several sample wafers, sets the estimated defect distribution area, skips the measurement of areas with large areas among good and defective, and then measures the pellets on subsequent wafers. By greatly increasing the efficiency of pellet measurement, it is possible to expect early improvement in quality and promotion of IC development, which is a significant effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図、第2図(a)
〜(C)は第1図のブロックの動作を説明するための初
期、サンプル試験後の不良度数分布領域及びウェーハ日
ットの推定不良分布領域に対応するマツピングメモリ部
の状態図である。 l・・・・・・被試験ウェーハ、2・・・・・・ウェー
八プロービング装置、3・・・・・・ICテスタ部、8
・・・・・・マツピングメモリ部、9・・・・・・ベレ
ット測定部、9a・・・・・・グローブ、11・・・・
・・良・不良判定回路、12・・・・・・良度数分布領
域、B・・・・・・推定不良分布領域。 代理人 弁理士   内 原   音 羊 l  画
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
-(C) are state diagrams of the mapping memory section corresponding to the initial failure frequency distribution area after the sample test and the estimated failure distribution area of the wafer date for explaining the operation of the block in FIG. 1. l... Wafer under test, 2... Wafer 8 Probing device, 3... IC tester section, 8
...Mapping memory section, 9...Bellet measurement section, 9a...Glove, 11...
... Good/bad judgment circuit, 12... Good frequency distribution area, B... Estimated defective distribution area. Agent Patent Attorney Otoyo Uchihara Illustrator

Claims (1)

【特許請求の範囲】[Claims]  複数の被試験ウェーハ上の複数の半導体ペレットにプ
ローブを順次当てて電気的特性試験を行いペレットが不
良の場合には該ペレットに不良マークを付加するウェー
ハのプロービング装置において、前記被試験ウェーハの
サンプル枚数のペレットの不良度数分布領域をウェーハ
形状に対応して記憶するマッピングメモリ部と、前記不
良度数分布領域を所定の度数以上とそれ以外の度数とに
2値化して推定不良分布領域を設定する推定領域設定制
御回路と、前記推定不良分布領域の設定後に測定する同
一ロッドの前記被試験ウェーハのペレットの位置が前記
推定不良分布領域内にある場合は測定せずに前記不良マ
ークの付加のみを行うペレット測定スキップ制御回路と
を設けた測定領域制御部を有することを特徴とするウェ
ーハのプロービング装置。
In a wafer probing apparatus that sequentially applies a probe to a plurality of semiconductor pellets on a plurality of wafers to be tested to perform an electrical characteristic test and adds a defective mark to the pellet if the pellet is defective, the sample of the wafer to be tested is a mapping memory unit that stores a defective frequency distribution area of the number of pellets corresponding to the wafer shape; and an estimated defective distribution area is set by binarizing the defective frequency distribution area into a predetermined frequency or higher and other frequencies. an estimated area setting control circuit, and if the position of the pellet of the test wafer of the same rod to be measured after setting the estimated failure distribution area is within the estimated failure distribution area, only the addition of the failure mark is performed without measuring; A wafer probing apparatus characterized by having a measurement area control section provided with a pellet measurement skip control circuit.
JP63037277A 1988-02-18 1988-02-18 Probing device for wafer Pending JPH01211935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63037277A JPH01211935A (en) 1988-02-18 1988-02-18 Probing device for wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63037277A JPH01211935A (en) 1988-02-18 1988-02-18 Probing device for wafer

Publications (1)

Publication Number Publication Date
JPH01211935A true JPH01211935A (en) 1989-08-25

Family

ID=12493193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63037277A Pending JPH01211935A (en) 1988-02-18 1988-02-18 Probing device for wafer

Country Status (1)

Country Link
JP (1) JPH01211935A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379093B1 (en) * 1998-08-31 2003-07-23 앰코 테크놀로지 코리아 주식회사 Marking method of semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379093B1 (en) * 1998-08-31 2003-07-23 앰코 테크놀로지 코리아 주식회사 Marking method of semiconductor package

Similar Documents

Publication Publication Date Title
CA1065062A (en) Non-logic printed wiring board test system
EP2064562B1 (en) Testable integrated circuit and ic test method
JPH10335395A (en) Contact position detecting method for probe card
KR19990013738A (en) IC test apparatus and method
CN114152858A (en) Electrical test device and test method for cutting channel device
US20020000826A1 (en) Semiconductor parametric testing apparatus
US5654632A (en) Method for inspecting semiconductor devices on a wafer
US6262586B1 (en) Probing method and apparatus utilizing an optimal probing mode
JPH01211935A (en) Probing device for wafer
US6693434B2 (en) Automated system for estimating ring oscillator reliability and testing AC response and method of operation thereof
JPH0252446A (en) Testing apparatus for integrated circuit
JPH11219997A (en) Electronic device inspection system and electronic device manufacturing method
US6815969B2 (en) Semiconductor inspection device capable of performing various inspections on a semiconductor device
JPS6111465B2 (en)
JP2767291B2 (en) Inspection device
JP3696009B2 (en) Semiconductor test apparatus, semiconductor test method, and recording medium
JP2006038791A (en) Prober needle switching device, prober device and method for measuring semiconductor element
JPH01244380A (en) Ic tester
KR0177987B1 (en) Multiple semiconductor chip test method
JP3147855B2 (en) Inspection method for mounting boards
JP2002156404A (en) Semiconductor measuring method and semiconductor measuring device
JPH01307679A (en) Automatic failure analysis equipment for semiconductor devices
KR200146658Y1 (en) Test apparatus for semiconductor device
JP3070439U (en) Semiconductor test equipment
JPH03179278A (en) Testing method for semiconductor