JPH01163812A - How does a high-speed bus circuit work? - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data transfer in electronic computers, and particularly to a high-speed bus circuit suitable for MO8 circuits.

[Conventional technology]

In order to increase the speed of the precharge circuit in conventional dynamic operation, as described in Tokuden@56-6062, the peripheral circuits that require precharging are divided into six peripheral circuits.

[Problem that the invention seeks to solve]

The above-mentioned prior art attempts to decentralize the precharge circuit, but it is aimed at increasing the speed of the chip, and is used in an inter-chip bus circuit with a large capacity load. Points were not allocated for multiple simultaneous switching points, and noise problems caused by precharge currents were rare.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus precharge circuit using a large number of tristate gates.

[Means for solving problems]

The above objective is achieved by distributing the precharge current by providing a precharge circuit function to each tristate gate that is a component of the bus, and precharging all tristate gates at the same time. be done.

[Effect]

First, all tristate gates constituting the bus precharge their pass lines to the same level (high or low level) simultaneously during the precharge period. As a result, the precharge current is distributed to all tri-state gates, which reduces the noise generated in the power supply and ground.

Since erroneous pulses are not generated in other output gates, there is no possibility of malfunction.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The MOS LSIs ol, tl, and nl have a large number of tristate gates 02 in each LSI, and the output bits corresponding to each LSI are interconnected by a pass line 07, forming a bus structure. Of course, this pass line 07 also includes a gate for inputting data, which is unnecessary for the explanation of the present invention, and will therefore be omitted.

The dry state game 02 has a data manpower 05 and a pass line predischarge manpower 06, and operates according to the time chart shown in FIG. L
Tri-state gate 02 in SI is the final stage NMO
It consists of an 8 push/pull buffer, a gate in the preceding stage, and an inverter control section. The ground line inductance 03 and the power line inductance 04 of the buffer and the control section are not common impedances of the charging and discharging current paths of the buffer, and are separated and connected to the outside of the LSI in order to prevent noise from occurring in the control section. Connect each to the power and ground of the printed circuit board.

The operation of the bus circuit of FIG. 1 will be explained using the waveforms of the timing chart of FIG.

Clock input 06 is supplied with an a-clock for grid-discharging the pass line 07 at the beginning of every cycle of the bus. Immediately after this pre-discharge is completed, Data 05 sends data to the bus. At this time, when the data input 05 is set to the a-level, the tri-state gate 02 outputs a polarity inverted output, ie, a high-level signal, to the bus 2-in 07, and charges the pass line 07ft, which was at the a-level, to a high level. bus? If you do not want to send data to the input, if you keep the data input 05 at a high level, the output of the tristate gate 02 becomes high impedance, and the pass line 07 becomes a
- Maintain level.

〔Effect of the invention〕

According to the present invention, the pre-discharge round discharge current of the pass line is operated simultaneously by all tri-state gates 02 of each L81 connected to the bus, so it can be distributed to all LSIs. Ground noise due to the ground line inductance 03 can be made extremely small. One L selected on the other hand
When sending an 8I or low level to the pass line 07, it is necessary to supply all the bus charging current with one dry state gate (02), but in this embodiment, the NMO8 push circuit is used. Noise caused by the inductance 04, which is a stain source, is not generated in the pass line 07 due to the fact that the power supply is separated.

Therefore, regardless of whether the VCS is at low level or high level, it is effective in preventing the generation of current noise due to simultaneous driving of the bus circuit.

[Brief explanation of the drawing]

Figure 1 is a bus circuit diagram of one embodiment of the present invention, and Figure 2 is a bus circuit diagram of an embodiment of the present invention.
3 is a time chart showing waveforms of various parts of the bus circuit shown in the figure. 01 ・L8I 01. 0.2-) Fistate gate, 03-...Ground line inductance, 04-
Power line inductance, 05・-data input, 06・-clock input, 07・-
Pass line, 1l-4tS111. 15-Data entry.

Claims (1)

[Claims] 1. High level, low level and high impedance 3.
In a bus circuit that connects the outputs of multiple tristate gates that have two output states, a precharge operation is first performed to determine the bus level, and then a selected tristate gate is enabled. In a so-called dynamic bus operation in which data is sent onto the bus using a precharge mode, the precharge operation for determining the bus level is performed by enabling all tristate gates connected to the bus during the precharge period. This is done by outputting the same level, setting the number of circuits with precharging according to the increase in the number of tristate gates connected to the bus, and then enabling only one selected tristate gate and precharging. A high-speed bus circuit characterized by sending data output on the bus that is opposite to the bus level.