JPH099258A - Decoding device for encoded video data - Google Patents

Abstract

(57) [Abstract] [Purpose] In addition to the standard decoding mode, realize a special decoding mode that supports freeze and high-speed display. [Structure] In standard decoding, decoding is performed based on time information multiplexed with encoded video data, and in the special decoding mode, decoding is performed based on the presence or absence of encoded video data in the buffering means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device for decoding and displaying coded video data which has been coded and data compressed, and more particularly to a decoding device having a function of repeatedly displaying the decoded video data.

[0002]

2. Description of the Related Art A digitized video signal has an enormous amount of information, and it is necessary for it to have a high speed and a large capacity for recording on a recording medium such as an optical disk, and also for transmission and broadcasting. A wide bandwidth transmission line is required, and its realization is not easy. Therefore, a coding method is used in which the digitized video data is highly efficiently coded and the data amount is compressed.

ISO / IE is used as such an encoding method.
MPEG standard defined by C ("Journal of the Television Society"; V
ol. 48, no. 1, pp. 44-49). The MPEG standard defines encoding of video data, encoding of audio signals, and a method of multiplexing encoded video data and audio data.

In the MPEG standard, the unit of video data to be encoded is a frame or field and is called a picture. The video data is subjected to a motion-compensated difference between it and the picture before or after it, or both of them, and is compressed using discrete cosine transform and variable length coding.

According to the motion compensation reference method, three of I, P and B are used.
There are pictures classified into one coding type. This is shown in FIG. The arrows in the figure represent the reference picture at the start point and the picture to be encoded at the end point. An image is not referred to in an I picture, and all the information necessary for decoding is encoded in that picture (intra-picture encoded image). Although the I picture can be decoded independently, the generated data amount is the largest. For the P picture, the I picture or the P picture decoded immediately before is used as a reference image (forward predicted image). The generated data amount is the second largest after the I picture. The B picture uses I or P pictures existing immediately before and immediately after it as a reference screen (bidirectional prediction image). Generates the least amount of data.

According to the MPEG standard, the amount of data generated for each picture is different as described above. In order to make such encoded video data a constant bit rate, the encoding device and the decoding device are provided with a buffer memory for the encoded video data, and further, the buffer memory overflows or falls within the range defined by the standard. Encoding and decoding are performed so that underflow does not occur. This will be described with reference to FIG. The figure is a decoding data amount transition model showing a transition of the data amount inside the buffer memory of the decoding device. The horizontal axis represents time and the vertical axis represents the amount of data.

Coded video data is input, and the data amount in the buffer increases accordingly. Decoding is performed once per picture period, and the amount of data in the buffer is reduced by the amount corresponding to one picture at that time. Since the above is repeated, the transition of the data amount in the buffer becomes a sawtooth shape as shown in the figure. The slope of the graph when the data increases indicates the transmission rate of the encoded video data input.

On the encoding side, assuming the above-mentioned decoded data amount transition model, the peak of the data amount may exceed the specified capacity of the buffer memory, or conversely, the minimum value of the data amount may become zero and the data may be insufficient. The code generation amount for each picture is controlled so as not to exist.

On the decoding side, it is indispensable for the decoding start timing to be decoded at the timing assumed by the coding side in the decoded data amount transition model. Underflow may occur earlier than this timing,
If it is late, overflow may occur. In order to enable this, the encoding side adds time information by multiplexing the encoded video data. As the time information, a PCR (Program Clock Referer) indicating time is used.
ence) or SCR (System Clock Reference)
e), DTS (Decoding Time Stamp) indicating the decoding start time of the coded video data at the beginning of the picture, and PTS (Pre) indicating the display time of the decoded picture data.
sentation time stamp), PCR or S
The time is matched with the code side by CR, the decoding is started at the time indicated by DTS, and the display is started at the time indicated by PTS.

By the way, in such a device for decoding encoded video data, not only the decoding assumed by the encoding side, but also the function of displaying the decoded image in the middle of freezing is desired to improve usability. .

On the other hand, regarding a method for realizing decoding including such a function, in the MPEG standard, a decoded data amount transition model assumed on the code side is converted into a decoded data amount transition including a display such as freeze. It is recommended that the encoded video data be partially modified to match the model and then decoded.

However, in order to realize this, a device for analyzing and rewriting the coded video data must be provided in front of the decoding device, which increases the hardware scale.
This causes a problem of increasing costs.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to realize a display function such as a freeze, which is not assumed in encoding, without causing an increase in hardware scale. Is to realize.

[0014]

In order to solve the above-mentioned problems, the present invention provides a parser means for encoded video data,
A means for buffering the encoded video data, a decoding means, a decoding start control means, and a buffering monitoring means, and means for repeatedly displaying the already decoded video data on the video data decoding means. Prepare for.

[0015]

The parser means extracts the time information at the time of the code multiplexed in the coded video data and supplies the information such as the decoding start time to the decoding start control means. The buffering means is
The coded video data is temporarily stored before being decoded, and the decoding means decodes the coded video data read from the buffering means and outputs display video data.

In the first decoding mode, the decoding start control means reads the coded video data from the buffering means based on the information such as the decoding start time and supplies it to the decoding means to start decoding. As a result, the standard decoding mode for performing the same decoding as assumed on the coding side is realized.

In the second decoding mode, the decoding start control means reads the coded video data from the buffering means based on the monitoring result of the buffering monitoring means and supplies it to the decoding means to start decoding. This mode is a special decoding mode in which decoding can be performed without using information such as the decoding start time. For example, in this mode, the means for repeatedly displaying the decoded video data repeatedly displays the decoded video data when the decoding is stopped. Thus, by intentionally stopping the supply of the encoded video data to the decoding means or skipping the encoded video data of some pictures, it is possible to perform decoding corresponding to freeze display or high-speed display.

[0018]

Embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing a decoding apparatus for coded video data and coded audio data. 1 is a clock generation section, 2 is a system parser section, 3 is a data selection section, 4 is a control interface section, and 5 is a control interface section. Is the video data decoding unit,
Reference numeral 6 is a main memory unit, and 7 is an audio data decoding unit.

The coded video data and the coded audio data are multiplexed with the timing information as described above.
Enter the system parser unit 2 as ta_stream. In the system parser, PCR or SC on data_stream
The R clock information (PCR / SCR) is extracted and sent to the clock generator 1. In the clock generator 1, this P
Based on CR / SCR, the same time as the encoding side (system_clo
ck_time) is reproduced, and an operation clock signal (clock_pulse) of each part is generated. system_time_clock is sent to the video data decoding unit 5 and the audio data decoding unit 6, and cl
ock_pulse is sent to all blocks.

In the system parser unit 2, data_strea
Discrimination of encoded video data and encoded audio data from m (a_
v) and timing information of decoding and display start (DT
S / PTS), coding type information (pic_type) for each picture of the video is identified, and a_v and pict_type are data_str.
As the DTS / PTS, the DTS / PTS corresponding to the video data decoding unit 5 and the audio data decoding unit 7 is sent to the data distribution unit 3 together with the eam.

In the data distribution unit 3, the system parser unit 2
Data_sterem input via a_v, pict_type and control interface 4 selection
With reference to _info, the encoded video data (v_stream) is sent to the video data decoding unit 5, and the encoded audio data (a_stream) is sent to the audio data decoding unit 7.

An operation command is externally input to the control interface unit 4 by a signal indicated by command in the figure. Further, the video data decoding unit 5 and the audio data decoding unit 7 are supplied with the state signals vd_req and ad_req indicating whether or not the encoded data can be received, and output them to the outside.

Selection_i output to the data selection / distribution unit 4
nfo is a normal decoding operation mode, that is, in a mode in which the decoding operation assumed on the encoding side is performed, v_stream desired to be decoded from a plurality of encoded video data and encoded audio data,
It indicates a_stream, and when data_sterem includes only one set of encoded video data and encoded audio data, selection_info has no meaning.

On the other hand, in the special decoding operation mode such as freeze, selection_info selects the desired v_stream for decoding, stops the output of v_stream and a_stream from the data selection / distribution unit 3, and selects a specific value in the encoded video data. It carries the information to select and output only the coding type data.

Further, it is sent to the video data decoding section 5.
ignore_TS is a command signal for decoding the coded data input to the video data decoding unit 5 as soon as possible without using the above-mentioned DTS / PTS for the timing of decoding and displaying the coded video data. Ignore_T when a special decoding operation mode is instructed
S instructs the decoding operation without using DTS / PTS.

The video data decoding unit 5 decodes the coded video data input as v_stream to generate a video signal (vide
o) is output. The decoding operation in the video data decoding unit 5 may be performed based on DTS / PTS or may be ignored by ignore_TS. Further, the main memory 6 is used for buffering the encoded video data and storing the reference video signal data, which are required in the decoding process. The memory bus (memory_bus) of the main memory 6 is also connected to the video data decoding device 5 and the audio data decoding unit 7,
It is also used for buffering encoded audio data.

FIG. 2 shows the video data decoding unit 5 shown in FIG.
FIG. 3 is a diagram showing details of a main memory 6; In the video data decoding unit 5, 501 is an encoded data interface circuit,
502 is a parser circuit for encoded video data, 503 is an inverse quantization circuit, 504 is an inverse DCT circuit, 505 is a reference video data generation circuit, 506 is an addition circuit, 507 is an output data interface circuit, and 508 is a buffer occupation ratio management circuit. , 509 is an encoded data buffer writing circuit, 51
Reference numeral 0 is an encoded data buffer read circuit, 511 is a forward reference video data read circuit, 512 is a backward reference data read circuit, 513 is a decoded video data write circuit, 514 is a display video data read circuit, and in the main memory 6. , 61 is an address decoding and data interface circuit, 62 is an encoded data buffer memory,
Reference numerals 63, 64 and 65 are frame memories. Although the main memory 6 does not show the function of buffering the encoded audio data in this figure, the encoded audio data is extremely small compared to the encoded video data, and the specific description of the present invention will be given. Does not affect.

The encoded video data (v_stream) is the encoded data interface circuit 5 in the video data decoding unit 5.
01, and the encoded data buffer write circuit 50
Write data to the encoded data buffer memory 61 in the main memory 6 via At the time of writing, the address in the encoded data buffer memory 61 where the specific data on v_stream corresponding to the DTS / PTS is stored is sent to the encoded data buffer read circuit 510 (DTS-a).
ddress). In addition, PTS is converted to DTS, and even if unified control is performed by DTS, decoded video data (vide
o) and audio data (audio) are output continuously, there is no problem.

Reading from the encoded data buffer memory 61 is controlled by the encoded data buffer read circuit 510. To the encoded data buffer read circuit 510,
The above-mentioned DTS / PTS (PTS is converted into DTS and handled), ignore_TS, system_time_clock, and D
In the mode based on TS_address input and DTS / PTS, when the time represented by system_clock_time matches DTS when reading from the encoded data buffer memory 61, the specific data on v_stream corresponding to this DTS is encoded data buffer. The read circuit 510 outputs the encoded video data to the parser circuit 502. In the mode in which ignore_TS instructs to ignore DTS / PTS, the read operation is continued as long as v_stream data exists in the coded data buffer memory 61 in a decodable state.

The buffer memory occupation ratio management circuit 508
If there is room to write the coded video data by comparing the write address of the coded data buffer write circuit 509 and the read address of the coded data buffer read circuit 510, vd_req requests the coded video data to the outside, If the encoded data for one picture does not exist in the encoded data buffer memory 61 prior to reading the encoded video data corresponding to one picture, under_flow
To the encoded data buffer read circuit 510 and the display video data read circuit 514.

The encoded video data is sent from the encoded data buffer read circuit 510 to the encoded video data parser circuit 502. The encoded video data parser circuit 502 performs variable-length decoding on variable-length-encoded DCT transform coefficient data and motion vectors, and the inverse quantization circuit 503 weights the DCT transform coefficient data. The inverse DCT circuit 504 performs inverse DCT conversion.
The inverse DCT-transformed data is pixel-level data of a motion-predicted video on the encoding side, and the addition circuit 50
In step 6, the video data of the reference screen is added to obtain the decoded video data.

The decoded video data is written to any one of the first frame memory 62 to the third frame memory 64 via the decoded video data writing circuit 512. The first frame memory 62 and the second frame memory are for storing data used later as video data of the reference screen, and the video data belonging to the above-mentioned I and P pictures correspond to this and the first frame The memory 62 and the second frame memory 63 are used alternately for each I and P picture. In the first frame memory 62 and the second frame memory 63, the temporally written first is the forward reference video data, and the temporally written is the backward reference video data. on the other hand,
The third frame memory 64 is dedicated to video data belonging to a B picture, and when a picture is defined as a frame, it divides the video data of one picture into two interlaced fields suitable for display. Used.

As the video data of the reference screen, the decoded video data is read from the first frame memory 62 and the second frame memory 63 by the front reference video data reading circuit 511 and the rear reference video data reading circuit 512, The reference video data generation circuit 505 generates reference video data used for motion compensation by selecting one of the reference video data and averaging two reference video data.

The display video data reading circuit 514 reads the video data from any one of the three frame memories of the first frame memory 62 to the third frame memory 64 according to the display order of the decoded video data. At this time, if the picture is defined as a frame, the video data of one picture is read by dividing it into two interlaced fields suitable for display, and the read video is output via the video output interface circuit 507. Output data (video).

The address decoding and data interface circuit 61 in the main memory 6 controls address signals and writing / reading, etc. via a memory_bus consisting of an address and data bus between the video data decoding section 5 and the main memory 6. A signal is received, the address signal is decoded, data on the data bus is written to a predetermined address, and data is read from the predetermined address onto the data bus.

FIG. 3 shows an operation example of a normal decoding mode in a decoded data amount transition model. The state of input of encoded video data input (v_stream) to the video data decoding unit 5 is shown under the decoded data amount transition model, and the state of display video data (video) is shown above the decoded data amount transition model. In the figure, I, P, and B indicate picture coding types, and the numbers attached to them indicate the arrangement in the display order. As for display video data, one picture is displayed during one picture (frame or field) period, but since the amount of data generated per picture is different, the input of encoded video data has an interval according to the data amount. Entered in. The decoding start timing is a time point indicated by a downward arrow in the figure, and one picture is decoded in one picture period in synchronization with the display cycle.
The conversion value of DTS or PTS into DTS indicates this decoding start time, but it is premised that regular decoding is performed such that one picture is decoded in one picture period, and DTS / PTS does not necessarily have to be decoded. It is not necessary for each picture, and on the encoding side, for example, I
It may be multiplexed only on the picture.

FIG. 4 shows an example of the decoding operation including the freeze period. Ignore_TS is shown at the top of the figure. ignor
e_TS rises in response to the command of freeze in FIG. 1, and selection_info outputs the encoded video data (v_stream) by the period data selection / distribution unit 3 in which ignore_TS is at the High level after the break of the next picture. To stop. As a result, the video data decoding unit 5 enters a state in which there is no encoded video data to be decoded, and
The display video data reading circuit 514 receives the under_flow and repeatedly displays the decoded video data already stored in the first frame memory 62 or the second frame memory 63 regardless of the display time indicated by PTS. To perform freeze display. In the figure, the display of the picture of P_1 which is old and undisplayed in time is repeated.

In response to the command instructing the return from the freeze mode, ignore_TS returns to the Low level. The restoration is performed from I51 which is the next I picture.
This is because an I picture that does not require the decoding result of encoded video data lost during the freeze period as reference video data is suitable for restoration, and the data selection distribution unit 3
Is the encoded video data (v_stream) from this I picture
Output is restarted, and the video data decoding unit 5 sets the system_time_
Decoding is restarted at the timing when the clock and DTS match.

FIG. 5 shows an example of a trick reproduction mode in which encoded video data is reproduced from a recording medium at high speed, and only I and P pictures are decoded and displayed. The encoded video data of the B picture is removed by the data selection / distribution unit 3,
High-speed reproduction is achieved by supplying the encoded video data to the decoding device at high speed.

When the trick play is instructed by the command, the control interface unit 4 causes the ignore_TS
This causes the video decoder unit 5 to ignore system-time_clock. The encoded data read circuit 510 in the video decoding unit 5 stores one frame in the buffer memory 62 for encoded video data in the main memory 2 at the time when decoding can be started, that is, in the middle of one frame period of the display image in the figure. If there are minutes of encoded video data, decoding is started, and if not, decoding is stopped for one frame period. The decoded image data is displayed and output with a delay of 0.5 frame in the example shown in the figure, but when the decoding is stopped, the display image data reading circuit 514 receives the under_flow signal, and the immediately preceding display image data is received. Is repeated.

[0042]

As described above, according to the present invention, it is possible to perform decoding based on the time information at the time of the code multiplexed on the encoded video data and the decoding without using them. Particularly in the latter decoding mode, decoding corresponding to freeze display can be realized by stopping the supply of the encoded video data to the decoding means, and further, a part of the encoded video data, for example, B picture data is skipped. Then, by supplying it to the decoding means, decoding corresponding to high-speed display can be realized.

[Brief description of drawings]

FIG. 1 shows an example of a decoding device for encoded video data according to the present invention.

2 is a configuration example of a video data decoding unit and a main memory in the encoded video data decoding device shown in FIG.

FIG. 3 is a decoded data amount transition model in standard decoding mode.

FIG. 4 is a decoded data amount transition model in a decoding mode corresponding to freeze display.

FIG. 5 is a decoded data amount transition model in a decoding mode compatible with high-speed display.

FIG. 6 is a diagram illustrating an encoding method.

7 is a diagram for explaining a decoded data transition model in the encoding method shown in FIG.

[Explanation of symbols]

 1 ... Clock generation part, 2 ... System parser part, 3 ... Data selection distribution part, 4 ... Control interface part, 5 ... Video data decoding part, 6 ... Main memory, 508 ... Buffer occupancy management circuit, 510 ... Encoded data Buffer read circuit, 502 ... Parser circuit for encoded video data, 5140 ... Display image data read circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yutaka Okada 5-20-1 Kamimizuhon-cho, Kodaira-shi, Tokyo Inside the Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Izushi Nabe 5-chome, Mizumizumoto-cho, Kodaira-shi, Tokyo No. 20 No. 1 Stock Company Hitachi Semiconductor Business Division

Claims (3)

[Claims] 1. The code amount per picture is not constant,
A device for decoding encoded video data in which time information at the time of encoding is multiplexed so that buffering of data is assumed in decoding and the control of the buffering can be matched between the encoding side and the decoding side. , A parser means for extracting time information at the time of coding from the encoded video data, a buffering means for buffering the encoded video data before decoding, and a buffering means for decoding and displaying the encoded video data. Decoding means, decoding start control means for reading the encoded video data from the buffering means, supplying the decoding video data to the decoding means, and controlling the start of decoding, and the presence or absence of decodable encoded video data in the buffering means And a coded video data buffering monitoring means for judging whether the coded video data to be decoded is not present. , A unit for repeatedly displaying already decoded video data, wherein the decoding start control unit is a first decoding mode for starting decoding based on decoding start time information included in the time information at the time of encoding, A decoding device for coded video data, comprising a second decoding mode for starting decoding based on a determination result of the coded video data buffering monitoring means. 2. The decoding start control means includes a stopping means for selecting a part of the encoded video data and outputting it to the decoding means, or for stopping the output of the encoded video data to the decoding means. The freeze display is performed by stopping the output of the encoded video data to the decoding means by the stopping means in the second decoding mode.
The encoded video data decoding device according to claim 1. 3. The decoding start control means includes a selection means for selecting a part of the encoded video data and outputting the selected video data to the decoding means, and the one selected by the selection means in the second decoding mode. The encoded video data decoding apparatus according to claim 1, wherein the encoded video data of the unit is output to the decoding unit for high-speed display.