JPH09306159A - Sequential read memory - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To reduce power consumption of a sequential read memory. A word line WL (n) for transmitting a selection signal
In the sequential read memory using the memory cell array 1 in which the memory cell M to be read is specified by the bit line BL (k) that transmits the data, the load resistance L (k) for pull-up and the power supply Vcc. The switch S (k) is connected, only the selected bit line is pulled up by the load resistance, and the unselected bit line is disconnected from the power supply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a first-in-first-out memory (FIFO).
ut) and sequential read-only memory, etc., to reduce the power consumption.

[0002]

2. Description of the Related Art The structure of a conventional sequential read memory is shown in FIG. 1 is a memory cell array, 2 is an X pointer, 3 is Y
A pointer 4 is a read circuit composed of a sense circuit,
Vcc is a power supply. The memory cell array 1 includes a word line WL (n) (n = 1, 1) that transmits a memory cell selection signal.
2, ..., N, the same applies hereinafter, and the semiconductor memory cell M is arranged at each intersection of the bit line BL (k) (k = 1, 2, 3, 4, same applies below) for transmitting read data. Consists of For convenience of description, the word line WL (n) is in the selected state at the “H” level (high voltage) and in the non-selected state at the “L” level (low voltage). A switch Y (k) is used to select the bit line BL (k). The switch Y (k) is used for the Y pointer 3
When the control signal supplied from is at "H" level, it is conductive, and when it is at "L" level, it is non-conductive. L (k) is a load resistance for pulling up the bit line BL (k).
Each of the X pointer 2 and the Y pointer 3 is composed of a circular shift register, and is initialized so that only one bit of the output is at "H" level and all the other bits are at "L" level.

The operation of the conventional sequential read memory shown in FIG. 4 is as follows. The figure shows a state in which the word line WL (3) is selected by the X pointer. When the word line is selected, all the memory cells located above it (four in this example) are activated, and the load resistance L
A current flows from the power supply Vcc to the memory cells via (k). This amount of current corresponds to the stored contents of the memory cell, and the signal voltage according to the stored contents is the load resistance L.
It occurs at both ends of (k). This phenomenon occurs for all load resistances L (k). Of the above signal voltages, the one selected by the switch Y (k) is amplified by the read circuit 4 and output to the outside as the stored content. In FIG. 4, the content of the memory cell selected by the word line WL (3) and the switch Y (2) is read.

In the sequential read memory, the reading order of the memory cells is uniquely determined, and an external input signal such as a clock is used to switch the memory cells to be read.
When the read operation of the memory cell located at the intersection of the word line WL (3) and the bit line BL (2) is completed and the next read operation is started, the word line WL (3) becomes the non-selected state, and instead the word line WL (3) WL (4) is in the selected state. Switch Y
(2) is still conductive, and bit line BL
(2) maintains the selected state. Similarly, the word line W
Until the data reading of the memory cell located on L (N),
It is done sequentially.

In the next read operation, the word line WL
(N) is deselected and the word line WL (1) is selected. At the same time, the "H" level output of the Y pointer 3 is also shifted by one (to be exact, rotate). As a result, the switch Y (2) becomes non-conductive, and instead the switch Y (2)
(3) becomes conductive. After that, by sequentially switching the selected word line as described above, the bit line BL
(3) The data in the memory cells above can be sequentially read out of the memory.

[0006]

As is apparent from the above, in the conventional sequential read memory, no special control is performed on the load resistance L (k) of the bit line. That is, in the read operation, all the load resistances L (k) are controlled to be conductive regardless of which bit line is selected. Therefore, there is a problem that power consumption increases according to the number of multiplexes of the bit line (4 in the example of FIG. 4).

An object of the present invention is to solve the above problems and to provide a sequential read memory with significantly reduced power consumption.

[0008]

SUMMARY OF THE INVENTION A first invention is a semiconductor memory of a sequential reading system using a memory cell array in which a memory cell to be read is specified by a word line transmitting a selection signal and a bit line transmitting data. In the first embodiment, the first means is provided for pulling up only the selected bit line with the load resistance and disconnecting the non-selected bit line from the power supply.

A second invention is the transistor according to the first invention, wherein the first means is a switch connected between the load resistance and the power supply, or an internal resistance when the load resistance is on. As the above, the switch or the transistor is controlled by a signal for selecting a bit line.

According to a third aspect of the present invention, in the first or second aspect, when the sequential reading method sequentially reads data of memory cells along a bit line, reading of data of all memory cells on a selected bit line is performed. Before completion of the above, second means for starting pull-up of the bit line to be selected next is added and configured.

According to a fourth aspect of the present invention, in the third aspect, the second means is provided by logically ANDing a selection signal of a bit line positioned before in a selection order and a selection signal of a last word line. It is composed of means for controlling.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a diagram showing a circuit configuration of a sequential read memory according to a first embodiment of the present invention. The same parts as those shown in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. S (k) is a switch for controlling the load resistance L (k).
It is controlled by the pointer 3. The configuration shown in FIG. 1 is different from the conventional configuration shown in FIG. 4 in that the switch S (k) is controlled by the output of the Y pointer 3 so that a specific bit line BL (other than the read target) at the time of reading ( The difference is that k) can be disconnected from the power supply Vcc.

The read operation from the memory cell specified by the selected word line and the selected bit line is the same as the operation of the conventional sequential read memory shown in FIG. For example, when the word line WL (3) and the bit line BL (2) are selected, the switch S (2) is controlled to be conductive, and a signal voltage according to the stored content appears in the load resistance L (2). By detecting this with the reading circuit 4, the stored contents can be read out.
However, in this embodiment, at this time, since the remaining switches S (1), S (3), and S (4) are controlled to be in the non-conducting state, the memory cell is selected by the word line WL (3). The load resistance L from the power supply Vcc
There is no current flowing into the memory cell via (1), L (3), L (4). Therefore, the power corresponding to the latter current can be reduced.

[Second Embodiment] By the way, a parasitic capacitance exists on the bit line BL (k). Therefore, in the first embodiment, when the selected bit line is switched, it takes a certain delay time until the voltage level of the selected bit line reaches the operating point. This delay time increases according to the parasitic capacitance of the bit line, that is, the number of memory cells connected to the bit line. As a result, in the memory cycle in which the selected bit line is switched, the access time becomes longer than other memory cycles. This causes a decrease in the speed performance of the memory, and thus becomes a problem in a memory for high-speed use. However, this problem can be easily dealt with by starting the pull-up of the next bit line one or several cycles before the selected bit line is switched by utilizing the sequential read method of the memory. is there.

As a second embodiment of the present invention, FIG. 2 shows an example in which pull-up of the next bit line is started in the cycle immediately before the switching of the selected bit line. The configuration of the circuit shown in FIG. 1 includes a 2-input AND gate 5 (k) and its AND gate 5 (k) for controlling the switch S (k).
2 and an OR gate 6 (k) for inputting the control signal from the Y pointer 3 is added. AN
The inputs of the D gate 5 (k) are the selection signal of the bit line positioned before in the selection order and the selection signal of the last word line WL (N). When the output of the AND gate 5 (k) becomes "H" level, pull-up of the bit line BL (k) to be selected in the next memory cycle is started.

In the second embodiment, the two switches S (k) and S (k + 1) are exceptionally turned on in the memory cycle immediately before the selected bit line is switched, and the power consumption is slightly increased. However, in the memory cycles other than this, as in the first embodiment, the conductive switch is the switch S corresponding to the selected bit line BL (k).
Only (k) can significantly reduce the power consumption.

[Third Embodiment] FIG. 3 shows a third embodiment of the present invention.
It is a figure which shows the circuit structure of the sequential read memory of embodiment. A D-type flip-flop 7 has a function of delaying its input signal by one cycle and outputting it. In the second embodiment, the same function as that of the second embodiment is realized by using the D-type flip-flop 7. Although the selection signal of the word line WL (1) is used as the shift control signal of the Y pointer 3 in the second embodiment, the selection signal of the word line WL (N) is used in the third embodiment. Is delayed by one unit time (corresponding to one cycle of the memory) by the D-type flip-flop 7 to realize an equivalent signal.

[Other Embodiments] In each of the above embodiments, the case where the number of bit line multiplexes is 4 has been shown, but there is no restriction. When the number of bit line multiplexes is K, it is 1 / K compared to the conventional configuration.
It is possible to reduce power consumption. Further, for convenience of description, although two components of the load resistance L (k) of the bit line and its switch Y (k) are used, for example, a MOS transistor realized by the internal resistance when the load resistance is turned on is used. You can also do it. In this case, the load resistance and the switch can be realized by one element by controlling the gate voltage of the transistor.

[0019]

As described above, according to the first and second inventions, there is an advantage that power consumption can be remarkably reduced. Therefore, FI
If the present invention is applied to a memory such as an FO or a microprogram ROM, which is mainly used for sequential reading, the power consumption of the system can be reduced, which is very effective. Further, according to the third and fourth inventions, in addition to the same effects as the first and second inventions, there is an advantage that a high speed operation becomes possible.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a sequential read memory according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of a sequential read memory according to a second embodiment of the present invention.

FIG. 3 is a circuit block diagram showing a configuration of a sequential read memory according to a third embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a configuration of a conventional sequential read memory.

[Explanation of symbols]

1: memory cell array, 2: X pointer, 3: Y pointer, 4: read circuit, 5 (k) [k = 1, 2,
3, 4]: AND gate, 6 (k): OR gate,
7: D flip-flop, M: memory cell, WL
(N) [n = 1, 2, ..., N]: word line, B
L (k): bit line, Y (k): switch forming a multiplexer of bit line, S (k): switch,
L (k): load resistance, Dout: output data, Vcc:
Power supply.

Claims (4)

[Claims] 1. A sequential read type semiconductor memory using a memory cell array in which a memory cell to be read is specified by a word line transmitting a selection signal and a bit line transmitting data, and only the selected bit line is loaded. A sequential read memory characterized by comprising first means for pulling up with a resistor and disconnecting an unselected bit line from a power supply. 2. The first means comprises a switch connected between the load resistance and the power source, or a transistor realized by an internal resistance of the load resistance when the switch or the transistor is turned on. The sequential read memory according to claim 1, wherein the sequential read memory is controlled by a signal for selecting a bit line. 3. When the sequential read method sequentially reads data of memory cells along a bit line, before reading data of all memory cells on a selected bit line is completed,
3. The sequential read memory according to claim 1, further comprising a second means for starting pull-up of a bit line to be selected next. 4. The second means is means for controlling the first means by a logical product of a selection signal of a bit line positioned before in the selection order and a selection signal of the last word line. The sequential read memory according to claim 3.