JPH09245474A - Semiconductor integrated circuit - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: To realize a memory macro in which the capacity can be freely changed from a small capacity to a large capacity, the data transfer speed can be made high, and the circuit overhead is small. A memory macro is configured by a combination of functional modules such as an amplifier module, a bank module, and a power supply, and row-system circuits that operate independently and a large number of I / O lines extending in the bit line direction are arranged in the bank module. The configuration is [Effect] Since the number of bank modules can be increased or decreased while keeping the number of I / O lines constant, the capacity can be freely changed from small capacity to large capacity while maintaining high speed of data transfer rate.
Also, since the power supply and amplifier can be shared, there is little overhead.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention realizes, in a semiconductor integrated circuit in which a memory circuit and a logic circuit are integrated on the same semiconductor chip, a high-speed memory macro whose memory capacity and the number of data input / output lines can be easily changed. It is related to the technology for doing.

[0002]

2. Description of the Related Art In recent years, with the high integration of LSIs, it is becoming possible to integrate a large-capacity memory and a large-scale logic circuit or arithmetic circuit on a semiconductor chip of about 1 cm square. In such chips, memory data input / output lines (hereinafter
Called O line. By setting the number of) to several hundreds or more,
Set the data transfer rate between the memory and the logic circuit or arithmetic circuit to 1
It is possible to achieve a very high speed of G bytes / second or more. Therefore, expectations are increasing for image processing applications that require high-speed data transfer with a memory.

The prior art applicable to the above uses is as follows:
For example, Toshio Sunaga, et al., "DRAM Macros for AS
IC Chips, "IEEE JOURNAL OF SOLID-STATE CIRCUIT, VO
There is an example of a memory macro described in L. 30, NO. 9, SEPTEMBER 1995. According to the conventional technique, the capacity of one memory macro is 256 Kbits to 1 Mbits, and 8 to 1
It has 6 I / O lines.

[0004]

SUMMARY OF THE INVENTION The present inventors have examined the case where an LSI for image processing is constructed using the memory macro. For example, if the capacity of the memory macro is 256 Kbits, the number of I / O lines is 8, and the number of I / O lines required by the LSI is 512, 64 memory macros are required. The capacity at this time is 16 Mbits.

When processing two-dimensional data in the field of image processing, for example, when restoring a blurred image or when recognizing a character or a specific pattern, the above memory capacity is not necessary. High speed is required. In this case, if only the speed is taken into consideration, a large number of conventional memory macros may be arranged and operated in parallel, but that would increase the memory capacity too much and increase the chip size.

On the other hand, when processing three-dimensional data, it is necessary to process a large amount of data at high speed. In this case, a large number of memory macros can be operated in parallel as described above. However, more I / O lines may be required or more capacity may be required depending on the difference in usage such as home use or industrial use and the type of data.

As described above, even in the same field of image processing, the required data transfer rate and memory capacity vary depending on the chip application and the type of data. Therefore, in the conventional memory macro, it is necessary to redesign the memory macro each time. There is a problem. Further, since all the circuits necessary for the operation are included in the memory macro, there is a problem that the circuit overhead becomes large when a large number of macros are arranged.

As described above, in the conventional memory macro, since the number of I / O lines is increased by increasing the number of memory macros, there is a problem that the number of I / O lines and the memory capacity cannot be freely set. is there. In addition, since all the circuits necessary for the operation are included in the memory macro, there is a problem that the circuit overhead becomes large when a large number of memory macros are arranged.

The problem to be solved by the present invention is to freely change the capacity of a memory macro from a small capacity to a large capacity. Another problem to be solved by the present invention is to increase the data transfer speed between the memory macro and the logic circuit module. Further, another problem to be solved by the present invention is to realize a memory macro in which the overhead of the circuit in the memory macro is small. Furthermore, another problem to be solved by the present invention is ASIC (Application Specific Integrated Circuit).
It is to realize a memory macro suitable for design.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a bank module (BANK: first
A large number of I / O lines (global bit lines (GBL)) extending in the bit line direction are arranged in the memory cell array of the module. Memory macro (MMACRO) amplifier module (AM
P: second module), bank module (BANK), power supply module (PS: third module), and other functional modules. Use multiple bank modules. The modules are connected by simply arranging them adjacently. Further, a circuit for activating and deactivating them in byte unit is provided in the amplifier module. One of the bank modules is a ROM module.

The word line (W) and the column selection line (YSi) of the memory macro extend in the same direction. A word driver (WD) and a column decoder (YD) on one side of the memory array are arranged. Sense amplifiers (SA) are placed on both sides of the memory array.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory macro according to an embodiment of the present invention will be described in order of items.

1. Configuration of memory macro and application example of memory macro FIG. 1 shows the configuration of memory macro MMACRO and memory macro MMAC.
An application example of RO to an image processing LSI is shown. In the semiconductor integrated circuit SIC shown in FIG. 1, a logic circuit block LOGIC and a memory macro MMACRO are formed on a single semiconductor substrate of single crystal silicon and resin-sealed (sealed in a plastic package). The arrangement and wiring of the modules and circuits shown in FIG. 1 generally correspond to the arrangement (layout) on the semiconductor chip.

1.1 Configuration of Memory Macro A feature of the memory macro MMACRO is that it is configured by a combination of a plurality of types of modules having different functions. Memory macro MMACRO is a bank module BA
It is composed of three types of modules: NK (BANK-0 to BANK-n), amplifier module AMP, and power supply module PS.

The bank module BANK includes a plurality of sub memory cell arrays SUBARY (SUBARY-00 to SUBARY-i7), a bank control circuit BNKCNT-1 and a bank control circuit BNKCNT-2.

The sub-memory cell array SUBARY has a plurality of pairs of bit lines B and / B, a plurality of word lines W (only one is shown in FIG. 1 due to the size of the drawing), and a plurality of word lines W. Memory cell (indicated by a circle in FIG. 1), a bit line precharge circuit PS that sets the potential of the bit line to a predetermined level before reading the memory cell, and a sense amplifier SA that amplifies the signal from the memory cell. And multiple pairs of bit lines B, /
Y selection circuit (Y switch Y-SW) to select one pair of B
And global bit lines GBL and / GBL connecting the selected bit lines B and / B to the amplifier module AMP. The sub memory cell array SUBARY is a bank module.
It is a division unit of I / O line in BANK. Note that a plurality of pairs of bit lines B and / B, a plurality of word lines W, and a plurality of memory cells are usually called a memory cell array, and therefore, they are properly used in the present application.

The bank control circuit BNKCNT-1 includes an X decoder (row decoder) XD for selecting a word line W and a bit line B,
It includes a Y decoder (column decoder) YD for selecting / B. The bank control circuit BNKCNT-1 automatically generates signals necessary for a series of memory cell read operations such as bit line precharge, word line selection, and sense amplifier activation in response to a bank address and a control signal described later. X decoder XD
One word line W is selected by, and a pair (n × 8 × i) intersecting with it is selected.
However, in the present embodiment, n = 8.
It is. The (8 × i) pair of the bit lines B and / B is further selected by the output signal YSi of the Y decoder YD. The selected bit lines B and / B exchange data with the amplifier module AMP through global bit lines GBL and / GBL arranged in parallel with the bit lines B and / B.

The bank control circuit BNKCNT-2 includes a group of sensors for detecting that the sense amplifier control signal has reached a certain level.

The amplifier module AMP is a bank module that synchronizes control signals, address signals and the like with clock signals.
It comprises a main control circuit MAINCNT for supplying to BANK, and a byte control circuit BYTCNT for controlling reading and writing of data from and to the bank module group (BANK-0BANK0n). This data input / output line DQ (DQ00,
.., DQ07, .., DQi7, .., DQi7) are input to the memory cells through here. Here, the byte control signal BEi is a signal for opening and closing the data input / output line DQ in byte units.

The power supply module PS is a bank module BA
VCH generation circuit VCHG, which generates word line voltage VCH (> power supply voltage VCC) required for word line drive circuit WD supplied to NK,
The voltage HVC required for bit line precharge (power supply voltage VCC /
2) A bit line precharge voltage generation circuit HVC that generates
G, a module that generates various voltages such as an array substrate voltage generation circuit VBBG that generates an array substrate voltage (back bias voltage) VBB (<power supply voltage VSS (ground potential)). When the operating voltage is to be lower than the external voltage in order to reduce the current consumption and improve the reliability of the device, a step-down circuit may be incorporated in the power supply module PS.

The control signals and address signals required for the bank module BANK are made common to each bank module BANK, and are arranged in the form of a bus in the bit line direction on the lower side of the bank module BANK. Therefore, these control signals and address signals can be included in the bank module BANK. That is, each bank module BANK
Can have the same cell structure including the control signal and the address signal.

However, since the row bank address Ri and the column bank address Ci are signals unique to each bank module BANK, the bank module BANK
You need only the number of Therefore, the row bank address Ri
To make each bank module BANK into the same cell including the wiring of the column bank address Ci and the column bank address Ci, a simple method is to wire the row bank address Ri and the column bank address Ci to the memory macro MMACRO of FIG. Input from the bottom or top.

On the other hand, in order to facilitate the interface with the logic circuit block LOGIC, the memory macro MMACRO
It is preferable to concentrate all control signals, address signals, and data input / output lines DQ on one side of the cell (left side in FIG. 1). Therefore, the row bank address Ri and the column bank address Ci from the left side of the memory macro MMACRO in FIG.
To input the wiring, the wiring is laid out as shown in FIG. If it is not necessary to make the same cell including the wiring, the wiring is laid out as shown in FIG.

The cell height of each module of the bank module BANK, the amplifier module AMP, and the power supply module PS is the same, and the global bit lines GBL, / GBL, the power supply lines, etc. are arranged at the same pitch.

As a result, by arranging the bank modules BANK in the required number in the bit line direction according to the capacity required in the system, and further disposing the amplifier module AMP and the power supply module PS on the left and right thereof, A desired memory macro module can be completed.

Bank module BA according to the embodiment of the present invention
NK has 256 word lines (8 X addresses), (8 × 8 × i) pairs of bit lines intersect one word line, and the Y decoder selects 1/8 (3 Y addresses). , (8 ×
i) A pair of global bit lines inputs and outputs. For example i =
When set to 16, one bank module BANK is 256K
With a capacity of (K = 1024) bits, data is input / output with a width of 128 bits. That is, it is possible to obtain a memory macro module whose capacity is variable in units of 256 Kbits.

For example, 1 bank with 4 bank modules
A memory macro of (M = 1048576) bits can be obtained with 8 bank modules. That is, the capacity does not increase four times as in the conventional general-purpose dynamic RAM (DRAM) such as 256K bits, 1M bits, 4M bits, and 16M bits, but a memory macro having a capacity necessary for an application can be obtained.

1.2 Operation Mode of Memory Macro FIG. 2 shows the relationship between the external signal and the operation mode of the memory macro MMACRO. The memory macro MMACRO uses the clock signal CL
Data input / output, address input, and control signal input are performed in synchronization with K. Here, Ai is an address signal, and the X address AXij and Y decoder Y input to the X decoder XD.
D Includes Y address AYi input. Unlike the conventional general-purpose DRAM, the address signal is not multiplexed in the X system and the Y system.

The row-system bank address Ri and the column-system bank address Ci for selecting the bank module BANK are signals unique to each bank module BANK that are not decoded because the number of bank modules is variable. The row-related and column-related command signals in the same bank module BANK are distinguished by the row-related bank address Ri and the column-related bank address Ci, respectively. CR, C as control signals
There are four, C, RW, and AC. DQij is an input / output I / O signal. The byte control signal BEi is a signal for independently controlling the data input / output line for each byte. With this signal, the amount of data read and written in parallel can be increased or decreased in byte units from 1 byte to a maximum of i bytes.

The activity of the bank module BANK (Bank Activ
e) and closing (Bank Close) are performed by taking in CR, AC and the address signal Ai at the rising edge of the clock signal CLK. CR ＝ “H” (High level), active at AC ＝ “H”, CR ＝ “
It is closed when H ", AC =" L "(Low level) .At this time, the address signal Ai to be fetched is only the low system, and the row bank address Ri selects the bank module BANK and the address signal Ai.
The word line W is selected with. S0 in FIG. 2 indicates the closed state of the bank module BANK. S1 is a bank module
Shows the active state of BANK. Further, S2 indicates a read or write state.

LA2 shown in FIG. 2 indicates the number of clocks at which the read or write command can be input from the active command input of the bank module BANK. LA indicates the number of clocks at which a read or write command can be input after changing the X address in the activated same bank module BANK. LR indicates the number of clocks from which a read command or a write command can be input to a command to close the bank module BANK.

Shown in the lower part of FIG. 2 is the relationship between the control signal of the column system and the operation mode. This is the clock signal
At the rising edge of CLK, CC, BEi, RW and the column address signal (the rest of the address signal Ai and the column bank address Ci) are fetched and read / write is controlled. In this embodiment, the number of clocks from the reception of the read command to the output of data, that is, the latency (Read latency) is 2, and the latency from the reception of the write command to the input of the write data (Write l
atency) is 1. As a result, the column system control signal can be input in non-wait state without going through the Nop state at the time of continuous read, continuous write, or change from write to read. There is a need to. Note that the latency described above is not optimal, and can be changed appropriately according to the system configuration.

1.3 Sense Amplifier and Bit Line Precharge Circuit FIG. 3 shows a circuit example of the sense amplifier SA and the precharge circuit PC in a portion corresponding to a pair of bit lines of the bank module BANK. Q1, Q2, Q3, Q4, Q7, Q8, Q9 and Q10 are N-channel MOS (N-MOS) transistors. Q5 and Q6 are P-channel M
It is an OS (P-MOS) transistor. In this example, a dynamic memory cell including one transistor (Q1) and one capacitor (MC) is used as the memory cell. Along with this, a bit line precharge circuit PC and a CMOS cross-coupled dynamic sense amplifier SA are used. The bit line precharge circuit PC precharges the bit lines B and / B with the voltage HVC when the bit line precharge signal FPC becomes high level. The CMOS cross-coupled dynamic sense amplifier SA operates when the P-channel sense amplifier common drive line CSP is at high level and the N-channel sense amplifier common drive line CSN is at low level. The read / write operation is the same as in a general-purpose DRAM.

1.4 Bank Control Circuit FIG. 4 shows the bank control circuit BN of the embodiment shown in FIG.
The operation waveform of KCNT-1 is shown. Bank control circuit BNKCNT-1
The feature is that it receives the row bank address Ri and the control signals CR and AC, and automatically generates the signals required for a series of memory cell read operations such as bit line precharge, word line selection, and sense amplifier activation. Is. That is, control is performed in an event-driven type. The operation will be described below.

First, consider the case where the bank module BANK of CR = "H", AC = "L", Ri = "H" is closed. When the clock signal CLK rises with CR = "H" and AC = "L", the main control circuit MAINC
Bank closing flag DCS rises in NT. The bank closing flag DCS is input to each bank module BANK. At this time, the row bank selection signal iRi rises in the bank module BANK where the row bank address Ri = "H". Since the logical product of the row bank selection signal iRi and the bank closing flag DCS is input to the set terminal S of the set / reset flip-flop RS-1, the row bank address Ri
The output STi of the set / reset flip-flop RS-1 of the bank module BANK which is "H" becomes "H".

On the other hand, since the result of the above logical product is input to the reset terminal of another set / reset flip-flop RS-2 through the logical sum circuit, its output WLPi
Becomes "L". When WLPi becomes "L", the output of the X decoder XD and the Y decoder YD in the bank control circuit BNKCNT-1
Gate signal YG becomes "L", followed by word driver WD
The output becomes "L" and the memory cell is disconnected from bit lines B and / B.

Next, the N-channel sense amplifier start signal FSA
Is "L", P-channel sense amplifier activation signal FSAB becomes "H", and sense amplifier SA stops operating. Here, the dummy word line DWL is a delay element having the same delay time as the word line W, so that the sense amplifier SA can be stopped after the level of the word line W becomes sufficiently low. This is to prevent the signal levels of the bit lines B and / B from being lowered due to the stoppage of the sense amplifier SA, thereby preventing the level of rewriting to the memory cells from being lowered.

Subsequently, the level sense circuit provided in the bank control circuit BNKCNT-2 above the bank module BANK detects "L" of the N-channel sense amplifier start signal FSA, and the output RE is "
L ". This signal is the precharge signal generation circuit XP in the bank control circuit BNKCNT-1 below the bank module BANK.
Bit line precharge signal FPC input to C and its output
Becomes "H". Bit line precharge signal FPC is a bit line
The bit lines B and / B are input to the precharge circuit PC provided for B and / B, and enter the precharge state. A series of states up to this point is named S0.

Next, from state S0, CR = "H", AC = "H", Ri = "H"
Consider the case of moving to the activity of the bank module BANK. CR
When the clock signal CLK rises in the state of "H" and AC = "H", the bank activation flag DCA rises in the main control circuit MAINCNT. Bank activation flag DCA is for each bank module B
Input to ANK. At this time, the row bank address Ri = "
The row bank selection signal iRi rises in the bank module BANK set to "H". The logical product of the row bank selection signal iRi and the bank activation flag DCA is input to the reset terminal R of the set / reset flip-flop RS-1. Therefore, the output STi of the set / reset flip-flop RS-1 of the bank module BANK having the row system bank address Ri = "H" becomes "L".

The logical product of the row system bank selection signal iRi and the bank activation flag DCA is simultaneously input to the X address latch circuit XLT, and the X address AXij is taken in during the "H" period to "L".
Latch. STi is input to the precharge signal generation circuit XPC, and the output bit line precharge signal FPC is set to "L".
To The bit line precharge signal FPC is
Bank control circuit BNKCNT while releasing precharge of / B
The level sense circuit in -2 is reached. When this level falls below a certain value, the output PCSEN becomes "H". This signal PCSEN is converted into a pulse having a narrow width of several nanoseconds by the one-shot pulse generation circuit ONESHOT in the bank control circuit BNKCNT-1, and then input to the S input terminal of the set / reset flip-flop RS-2. The resulting output WLPi
Becomes "H". When WLPi becomes “H”, first, the output of the X decoder XD selected by the X address AXij becomes “H”,
Then, the output of the word driver WD connected to it becomes "H" and the memory cell is connected to the bit lines B and / B.

Next, the N-channel sense amplifier start signal FSA
Becomes "H", the P-channel sense amplifier activation signal FSAB becomes "L", and the sense amplifier SA starts operating. Dummy word line DW
With L, the sense amplifier SA can be operated after the level of the word line W becomes sufficiently high and signals are sufficiently output to the bit lines B and / B. This is to prevent the sense amplifier SA from operating while the signal is small and malfunctioning. Subsequently, the level sense circuit provided in the bank control circuit BNKCNT-2 above the bank module BANK is an N-channel sense amplifier start signal.
The output RE becomes “H” upon detecting “L” of the common drive line on the N-MOS transistor side of the FSA. Signal RE is bank module BANK
Is ANDed with WLPi by the AND circuit in the lower bank control circuit BNKCNT-1, and its output YG becomes "H". This YG enables the Y decoder circuit YD. A series of states so far
Name it S1.

Next, from state S1 CR = "H", AC = "H", Ri = "H"
Consider the case of moving to the activity of the bank module BANK. CR
When the clock signal CLK rises in the state of "H" and AC = "H", the bank activation flag DCA rises in the main control circuit MAINCNT. Bank activation flag DCA is for each bank module B
Input to ANK. At this time, the row bank address Ri = "
The row bank selection signal iRi rises in the bank module BANK set to "H". The logical product of the row bank selection signal iRi and the bank activation flag DCA is input to the reset terminal R of the set / reset flip-flop RS-1. However, STi does not change because STi has already become "L" in the previous cycle .. Row system bank select signal iRi and bank activation flag DCA
The logical product of is simultaneously input to the X address latch circuit XLT,
Take in the X address AXij during the "H" period and latch it at "L".

The output of the logical product circuit is input to the R terminal of RS-2 via the logical sum circuit to set WLPi to "L". WLPi
Becomes "L", the word lines are in the same order as S0
The voltage of the W / N-channel sense amplifier activation signal FSA becomes "L" and RE becomes "L". When RE becomes "L", a pulse having a width of about several tens of nanoseconds is output from the one-shot pulse generation circuit ONESHOT in the precharge signal generation circuit XPC. This pulse is input to the drive circuit of the precharge signal generation circuit XPC,
It is output to the bit line precharge signal FPC with the width kept unchanged. This signal reaches the level sense circuit in the bank control circuit BNKCNT-2 while precharging the bit lines B and / B. When this level falls below a certain value, the output PCSEN becomes "H". This signal is a bank control circuit
It is converted into a narrow pulse by the one-shot pulse generator ONESHOT in BNKCNT-1, and then input to the S input terminal of the set / reset flip-flop RS-2. As a result, the output WLPi becomes "H". When WLPi becomes "H",
The output of the X decoder XD selected by the X address AXij becomes "H", and subsequently the output of the word driver WD connected to it becomes "H", and the memory cell is connected to the bit lines B and / B.

Next, the N-channel sense amplifier start signal FSA
Becomes "H", the P-channel sense amplifier activation signal FSAB becomes "L", and the sense amplifier SA starts operating. The subsequent operation is the same as S1 described above. After the above operation, the bank module BANK becomes ready for reading and writing.
This state is named S2.

1.5 Byte Control Circuit Next, the operation of the column system will be described. FIG. 5 shows an example of the byte control circuit BYTCNT. The i-th byte control circuit BYTCNT is inserted into the amplifier module AMP of FIG.

In FIG. 5, WA-0 to WA-7 are write circuits, and RA-0 to RA-7 are read circuits (main amplifiers). The eight write circuits WA and read circuits RA are thus arranged in the byte control circuit BYTCNT. Here, the write data input from DQ-i0 is transmitted to the global bit lines GBL-i0 and / GBL-i0 via the inverters I1 and I2 functioning as a buffer and the switch SW1. The global bit lines GBL-i0 and / GBL-0i are connected to the divided input / output lines IO and IOB in each bank module BANK as shown in FIG. Is transmitted to the bit lines B and / B and further to the memory cell. Here, the switch SW1 is provided to bring the global bit lines GBL-i0 and / GBL-0i into a high impedance state at the time of reading. This is controlled by the signal WAi.

The data read from the memory cell is passed through the global bit lines GBL-i0, / GBL-i0 and the switch SW2 from the input / output lines IO and IOB in each bank module BANK.
The signal is transmitted to the main amplifier including the MOS transistors QA4 to QA8. Here, the main amplifier is a drain input type dynamic amplifier, and its input node is precharged to VCC before reading signals from the global bit lines GBL-i0 and / GBL-0i. When the signal is transmitted, a voltage difference appears between the two input terminals, the signal MAi activates the main amplifier, and the difference is amplified. Here, the switch SW2 is the global bit line GBL-i, / G until just before the main amplifier operates.
Connect the BL-i to the main amplifier and disconnect it during operation.
This is to reduce the load capacity during amplification of the main amplifier and to enable high-speed operation. The switch SW2 is controlled by the signal MAGi. The signal amplified by the main amplifier is input to the latch circuit composed of N1 and N2 in the next stage, and further output to the terminal DQ-i0 via the buffer amplifier TI1.

The signal DOEi switches between high impedance and low impedance of the TI1 output. The TI1 output is set to high impedance when writing. P-MOS transistors QA1 to QA3 are global bit lines GBL-i, / GBL-i
The pre-charge circuit and P-MOS transistors QA9 to QA10 form the pre-charge circuit of the main amplifier. Controlled by IOEQiB and MAEQiB respectively. In addition, all the above control signals are read / write control circuit block RW.
Generated by external signals CC, BEi, RW, CLK in CNT. Here, the read / write control circuit block RWCNTR is provided for each byte control circuit BYTCNT.

FIG. 6 shows a timing chart of the column signals. At the rising edge of the clock signal CLK,
The read command (CC = "H", RW = "H") and the byte control signal (BEi = "H") are input, and the control signals described above are switched as shown in FIG. Then, the data is read out of the memory macro MMACRO during the period of DOEi = "H". “Byte dis.” Is BEi = “L”, indicating that the DQ-I0 to DQ-i7 are non-selected bytes.

1.6 Main Control Circuit FIG. 7 shows an example of the main control circuit MAINCNT. The main control circuit MAINCNT combines standard logic circuits such as NAND circuits, inverters, and D-type flip-flops from control signals CR, AC, CC, clock signal CLK, and address signal Ai input from the outside of the memory macro MMACRO. The bank closing flag DCS shown in FIG. 1 (in FIG. 7, its inverted signal / DC
S), bank activation flag DCA (in FIG. 7, its inverted signal / D
CA), column address enable signal YP, row address signal (X address signal) AXij, column address signal (Y
Address signal) Signals such as AYi are created.

Here, the circuit RSTCKT is a circuit for generating a reset signal RST when the power source of the bank control circuit BNKCNT described later is turned on, and generates a one-shot pulse when the power source is turned on. The feature of this circuit RSTCKT is that a capacitor is provided between the power supply line and the terminal so that the voltage of the input terminal of the inverter IV1 rises at a high speed even when the power supply voltage rises at a high speed. The operation will be described below. First, when the power supply voltage VCC rises, the gate and drain voltages of the N-MOS transistor QV3 rise. When this voltage is lower than the threshold voltage of the N-MOS transistors QV3 and QV5, no current flows through the N-MOS transistors QV3 and QV5.
The voltage at the input terminal of 1 rises at the same voltage as the power supply voltage.
Next, when the gate and drain voltages of the N-MOS transistor QV3 exceed the threshold voltage, a current flows through the N-MOS transistors QV3 and QV5, and the voltage at the input terminal of the inverter IV1 decreases. Thus, a one-shot pulse can be generated when the power is turned on. Here, the value of VCC at which the voltage at the input terminal of the inverter IV1 starts to fall is roughly QV2 and QV
It is determined by the threshold voltage of 3 and is represented by VCC = VT (QV2) + VT (QV3). This value can be further finely adjusted by changing the W / L ratio of the P-MOS transistor QV4 and the N-MOS transistor QV5, the N-MOS transistor QV3 and the P-MOS transistor QV1, or the N-MOS transistor QV3 and the QV5. . Here, a capacitor QV6 is connected between the power supply line and its terminal, which is connected to the inverter IV when the power supply voltage rises at high speed.
This is to prevent a phenomenon in which the rise of the voltage is delayed by the capacitance attached to the input terminal 1 and a current flows through QV5 before the voltage exceeds the logical threshold value of the inverter IV1, and the node does not exceed the logical threshold value of the inverter IV1. As described above, according to this circuit, a pulse can be reliably generated regardless of whether the power supply rises at a high speed or at a low speed.

1.7 Read / Write Control Circuit Block FIG. 8 shows an example of the read / write control circuit block RWCNT. Here, like the main control circuit MAINCNT, the control signal input from the outside of the memory macro MMACRO
RW, CC, clock signal CLK, byte control signal BEi, NA
MAEQiB, WA shown in Figure 5 by combining standard logic circuits such as ND circuits, inverters, and D-type flip-flops.
i, MAi, DOEi (inverted signal DOEiB in FIG. 8), MAGi
Signals such as (the inverted signal MAGiB in FIG. 8) are generated. D1, D2, and D3 are delay circuits. The CLK1B, CLK2B and CLK3B generation circuits shown in the lower part of the figure may be provided for each read / write control circuit block RWCNT, or only one may be provided for the main control circuit block MAINCNT.

1.8 Another Example of Memory Cell Array FIG. 9 shows another example of the memory cell array MCA portion in the bank module BANK. The feature of this example is that the sense amplifier SA and the bit line precharge circuit PC are arranged on the left and right sides of the memory cell array MCA for each pair of bit lines. Since the layout pitch of the sense amplifier SA is relaxed by this, the length of the sense amplifier SA in the bit line direction is shortened, which is particularly effective for the method of passing a large number of column select signals YSi in the word line direction as in the present invention. become. That is, by shortening the length of the sense amplifier SA in the bit line direction, the parasitic capacitance in that portion is reduced, and the signal from the memory cell can be increased.

1.9 Bank Control Circuit Block FIG. 10 shows an example of the bank control circuit block BNKCNT-1. In particular, it is suitable for the memory cell array in which the sense amplifiers are alternately arranged as shown in FIG. Similar to the read / write control circuit block RWCNT above, standard logic circuits such as NAND circuits, inverters, and D-type flip-flops are combined to combine the word line W, bit line precharge signal FPC, and column address select signal shown in FIG. Signals such as YSi, N channel sense amplifier start signal FSA and P channel sense amplifier start signal FSAB are produced. Where (R),
(L) are signals for the right-side sense amplifier SA and the left-side sense amplifier SA, respectively. The output RST of the power-on reset circuit described above is input to the WLPi and STi generation circuits, and at power-on, their outputs are the same as in the S0 state, "L" and "H" respectively.
To As a result, the memory cell array enters a precharge state, and an increase in power-on current due to the operation of the sense amplifier SA can be suppressed.

The lower part of FIG. 10 shows a bank control circuit block.
This is an example of BNKCNT-2. Here, PCS is a level sensor for the bit line precharge signal FPC, and SAS is a level sensor for the common drive line on the N-MOS transistor side of the sense amplifier SA. These are for detecting the end of precharge and the end of signal amplification, respectively. The feature of this example is that the logic threshold value of a CMOS logic circuit that receives an input signal is detected in order to detect the point where the input signal falls sufficiently.
That is, the voltage is lowered to near the threshold voltage of the N-MOS transistor. Thereby, even if the threshold voltage of the sense amplifier SA or the memory cell varies, it is possible to compensate to some extent. A differential amplifier may be used as this level sensor. In this case, if the reference voltage serving as the sense level is set lower than the threshold voltage of the N-MOS by the variation, the malfunction due to the variation can be prevented as in the above logic threshold method.

1.10 Logic Circuit Block The logic circuit block LOGIC shown in FIG. 1 is for processing functions such as image data arithmetic processing, image memory (memory macro MMACRO) drawing, and image memory reading to a display device. I do. Further, the logic circuit block LOGIC has an address signal Ai and a row bank address R in the memory macro MMACRO.
i, column bank address Ci, data input / output line DQ-i0 ~
DQ-i7, control signal CC, AC, CR, RW, byte control signal BEi,
The clock signal CLK and the like are supplied. Further, the logic circuit block LOGIC gives a refresh operation instruction and a refresh address to the memory macro MMACRO by using the control line, the address signal and the like.

The logic circuit block LOGIC also interfaces with the outside of the semiconductor integrated circuit SIC. A central processing unit CPU, a display device, etc. are connected to the outside, and the I / O of FIG.
Data and commands are exchanged by the control signal.

2. Second Application Example to Memory / Logic Embedded LSI FIG. 11 shows another application example to the memory / logic embedded LSI. The feature of this example is that four memory macros MMACRO according to the present invention are mounted, and all the data output from the memory macros MMACRO are arranged in parallel in the logic circuit block LOGIC-.
1, processing with LOGIC-2. As a result, the data transfer and processing speed can be quadrupled as compared with the case of only one memory macro MMACRO. Also, the data processing speed can be further improved by increasing the number of macros.
Here, the logic circuit block LOGIC-3 is the logic circuit block LOG
It has the function of processing the calculation results of IC-1 and LOGIC-2 into a data format that is easy to capture in the element outside the chip, and conversely processing the data from outside the chip into a format that is easy to calculate.
The method of processing data from a plurality of memory macros MMACRO in parallel in this way is particularly effective for applications that need to process a large amount of data at high speed, such as three-dimensional graphics.

Further, not only the memory macro MMACRO having the same capacity as in this example, but the memory macros MMACRO having different capacities may be used depending on the application. For example, when used together with a microprocessor, one or two bank modules BANK of the memory macro MMACRO are used, and an amplifier module is further provided.
The AMP can be changed to a high-speed type and used as a cache memory. Also, increase the number of bank modules BANK to increase the low or medium speed amplifier module AMP
Can be used as a main memory. Here, the main amplifier is set at low speed or medium speed in order to reduce the area occupied by the amplifier. As described above, according to the present invention, since the memory macro is a module system, the memory capacity and the capability of the amplifier can be freely changed.

3. Third Example of Application to Memory / Logic Mixed LSI FIG. 12 shows an example of application when the internal data bus width is small. In the figure, the data input / output line DQi is commonly connected for each byte. Therefore, one memory macro MMAC
The number of input / output lines from RO is only eight. The data is switched by the byte control signal BEi output from the selection circuit SELECTOR.
Done in By performing such a connection, the memory macro MMACRO can be used as a built-in memory of a normal 8- to 32-bit one-chip microcomputer.

4. ROM bank module Bank module BANK of memory macro MMACRO is shown in FIG.
An example in which a part of the above is replaced with a ROM (Read Only Memory) module is shown. An advantage of this example is that when used as a built-in memory of a one-chip microcomputer, a ROM and a RAM control circuit (such as an amplifier module AMP including a main control circuit MAINCNT) can be shared, so that a chip area can be reduced. In addition, an image processor and DSP (Digital Signal Process)
or)), if, for example, the coefficient of the product sum operation is put in the ROM, the RAM and the ROM are close to each other, so that the data can be read out at high speed and the operation can be performed.

FIG. 14 shows a circuit example of a memory array RMCA of a ROM module suitable for being applied to this memory macro MMACRO. The feature of this example is that some DRAM memory cells of the same size as the RAM module are used to match the number and pitch of global bit lines with the RAM module (bank module BANK shown in FIG. 1, FIG. 3, FIG. 9, etc.). Change
It is being used as a ROM cell. For use as a ROM cell, for example, after forming an insulating film of a memory cell, a mask for removing the insulating film may be added in accordance with data to be written. As a result, the cell from which the insulation film has been removed (MC1 in the figure) is in a short-circuit state with the common electrode of the memory cell, and the cell that has not been removed (MC2 in the figure) has the information written by maintaining the insulation. become.

The operation of the ROM module will be described with reference to FIGS. First, set the bit line precharge signal FPC to "H".
To turn on the N-MOS transistors QR3, QR4, QR5, and QR7, turning on the bit line B and the input terminals N1, N2 of the sense amplifier.
Becomes the voltage of VCC. Next, the bit line precharge signal FPC
To "L" and set the word line (W1 in this example) and the transfer signal SC to "H"
(VCC or more). Then N-MOS transistor QR
1, since QR6 and QR8 are turned on, the node of N1 drops to the voltage of HVC, and the node of N2 drops to the voltage of 3/4 VCC. This voltage difference is applied to the P-channel sense amplifier common drive line CSP.
The sense amplifiers (QR9 to QR12) are operated and amplified by setting the H ", N-channel sense amplifier common drive line CSN to" L ". Since the current continues to flow through the N-MOS transistor QR1, L "to turn off the N-MOS transistors QR6 and QR8. Thus, N1 becomes N2
Is the voltage of VCC. That is, information "0" is read.
Here, if W2 is started instead of W1, the node of N2 does not change to the voltage of 3/4 VCC, but the current of N1 node does not flow to the memory cell, so the voltage of VCC becomes the voltage of VCC and the potential relationship is reversed. This time, N1 becomes the voltage of VCC and N2 becomes the voltage of VSS.
That is, information "1" is read. Here, if YSi is set to "H", the global bit line GB is passed through the I / O lines IO and IOB.
A signal will appear at L and / GBL. Note that the word line is "L"
The timing can be set anywhere from when SC is set to "L" to when the precharge is started.

As described above, according to this example, since the same memory cell pattern as the RAM can be used as the ROM, the number and pitch of the global bit lines can be easily adjusted to that of the RAM module. Here, as an example,
Although the method of removing the insulating film of the DRAM cell was described,
Another method, such as removing the storage electrode of the memory cell, may be used. Also, if the pitch of the global bit line can be the same as other bank modules BANK,
ROM cells may be used.

Here, the ROM is a mask ROM with a fixed program in which information is written in advance in the chip manufacturing process.
Therefore, the nonvolatile memory retains the stored information even when the power is turned off. The RAM is a memory from which data can be rewritten, stored, and read at any time, and is a volatile memory that cannot store stored information when the power is turned off.

Up to here, the memory cell of the RAM is shown in FIG.
Although it has been described as the DRAM cell shown in
There is no problem in using cells. Also in this case RO
The ROM cell of the M bank module may be made by modifying a part of the SRAM cell.

[0069]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

The memory macro is composed of a combination of functional modules such as an amplifier module, a bank module and a power supply. A row-related circuit which operates independently and a number of I / O lines extending in the bit line direction are arranged in the bank module.
The I / O line is configured to be connected only by arranging each module adjacent to each other. Further, a circuit is provided in the amplifier module so that they can be activated and deactivated in byte units. As a result, the number of modules of the memory cell array can be increased or decreased while waiting for a large number of I / O lines, so that the capacity can be freely changed from a small capacity to a large capacity while maintaining high speed of data transfer rate. Furthermore, since I / O lines can be activated and deactivated in byte units in the amplifier module, the number of I / O lines that go out to the outside of the memory macro can be increased or decreased in byte units. Also, since the power supply and amplifier can be shared, there is little overhead.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a memory macro of the present invention and an application example to an image processing LSI.

FIG. 2 is a diagram showing a relationship between an external signal and an operation mode of the memory macro of the present invention.

FIG. 3 is a diagram showing an example of a sense amplifier and a precharge circuit of the present invention.

FIG. 4 is a diagram showing the operation timing of the bank control circuit of the present invention.

FIG. 5 is a diagram showing an example of a byte control circuit of the present invention.

FIG. 6 is a diagram showing write and read timings of the present invention.

FIG. 7 is a diagram showing an example of a main control circuit of the present invention.

FIG. 8 is a diagram showing an example of a read / write control circuit of the present invention.

FIG. 9 is a diagram showing a second example of the bank module of the present invention.

FIG. 10 is a diagram showing an example of a bank control circuit of the present invention.

FIG. 11 is a diagram showing a second application example of the memory / logic embedded LSI of the present invention.

FIG. 12 is a diagram showing a third application example of the memory / logic embedded LSI of the present invention.

FIG. 13 is a diagram showing a second configuration example of the memory macro of the present invention.

FIG. 14 is a diagram showing a configuration example of a ROM-BANK module of the present invention.

FIG. 15 is a diagram showing operation waveforms of the ROM-BANK module of the present invention.

FIG. 16 is a diagram showing an example of a wiring layout of bank addresses according to the present invention.

[Explanation of symbols]

MMACRO ... Memory macro LOGIC ... Logic circuit block AMP ... Amplifier module BANK ... Bank module PS ... Power supply module MAINCNT ... Main control circuit block BYTCNT ... Byte control block BNKCNT-1 ... Lower bank control block BNKCNT-2 ... Upper bank control block MCA ... Memory cell array SUBARY ... Sub memory cell array (I / in bank module)
(O line division unit) SA Sense amplifier PC Precharge circuit MC1, MC2 Memory cell WD Word driver XD X decoder YD Y decoder DWL Dummy word line ONESHOT One-shot pulse generation circuit RS-1, RS -2: Set / reset flip-flop D-FF: Delay flip-flop (D flip-flop) XLT: X address latch circuit YLT: Y address latch circuit XPC: Precharge signal generation circuit VCHG: VCH generation circuit VBBG: Substrate voltage in array Generator HVCG: Bit line precharge voltage generator D1, D2, D3, D5, D15: Delay circuits Qi, QAi, QRi: MOS transistors VCC: Power supply voltage VCH: Word line voltage VSS: Power supply voltage (ground potential) VBB: Power supply voltage HVC: Half the power supply voltage B, / B: Bit line GBLij, / GBLij: Global bit line I / O: Input / output line in sub memory cell array block YSi: Color Address select signal FPC ... bit line precharge signal FSA ... N channel sense amplifier activation signal FSAB ... N channel sense amplifier activation signal W, W1, W2 ... Word line CSP ... P channel sense amplifier common drive line CSN ... N channel sense amplifier common Drive line DQ-ij ... Memory macro data input / output line BEi ... Byte control signal CLK ... Clock signal DCA ... Bank activation flag DCS ... Bank closing flag YP ... Column address enable signal AXij ... Row address signal (X address signal) AYi … Column address signal (Y address signal) Ri… Row system bank address Ci… Column system bank address RST… Power-on reset signal.

Claims (14)

[Claims] 1. A memory array comprising a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells arranged at intersections thereof, and a memory array connected between each bit line pair of the plurality of bit line pairs. A sense amplifier for amplifying the signal of the bit line pair; a word driver for selectively driving the plurality of word lines; a plurality of bit line pairs divided into a plurality of groups; A data input / output line pair commonly connected to each bit line pair via a column switch, and a global bit line connected to the data input / output line pair and extending in the same direction as the bit line pair on the memory array. A column for opening and closing the column switch, selecting a bit line pair from a plurality of bit line pairs in the set, and outputting a column selection signal for connecting to the global bit line pair. The semiconductor integrated circuit having a first module and a coder. 2. The semiconductor integrated circuit according to claim 1, further comprising: an amplifier that amplifies a signal from the memory cell via the global bit line, and a memory for writing data into the memory cell via the global bit line. And a second module including a writing circuit. 3. The semiconductor integrated circuit according to claim 2, further comprising a third module including a circuit for generating a voltage used in the first module and the second module. 4. The semiconductor integrated circuit according to claim 3, comprising a plurality of the first modules, and the plurality of the first modules are not activated at the same time. 5. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the second module can control data input / output in byte units. 6. A memory cell of a semiconductor integrated circuit according to any one of claims 1 to 5 is a dynamic cell. 7. The semiconductor integrated circuit according to claim 4, wherein a memory cell of one of the plurality of first modules is a ROM. 8. The semiconductor integrated circuit according to claim 7, wherein the memory cell of the ROM is formed by adding a process for writing data to the same process as the memory cell of the RAM. 9. The semiconductor integrated circuit according to claim 1, wherein
The plurality of word lines and the column selection line extend in the same direction. 10. The semiconductor integrated circuit according to claim 9, wherein the word driver and the column decoder are arranged on one side of the memory array. 11. The semiconductor integrated circuit according to claim 10, wherein the sense amplifiers are arranged on both sides of the memory array. 12. The semiconductor integrated circuit according to claim 4, wherein the second module, the plurality of first modules, and the third module are arranged in this order, and the global bits of the plurality of first modules are arranged. The line pairs are arranged so that they are connected to each other at the ends of the module. 13. The semiconductor integrated circuit according to claim 12,
Further, it comprises a logic circuit block connected to the second module. 14. The semiconductor integrated circuit according to claim 13, wherein the logic circuit block has an image processing function.