JPH09181168A - Manufacture of silicon semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten a trench part in an SOI(silicon on insulator) substrate having isolation trenches. SOLUTION: A nitride film 2 and an oxide film 3 are formed on the surface of an SOI substrate 1, and the part corresponding to a region for forming trenches 5 is eliminated. The trenches 5 are formed by etching, and side wall oxide films 6 are formed in the trenches 5, which are filled with polycrystalline silicon 7. The nitride film 2 is used as a stopper, and the polycrystalline silicon 7 and the oxide film 3 are eliminated by selective polishing. After that, the nitride film 2 is eliminated. By the selective polishing using the nitride film 2 as the stopper, the part including the oxide film 3 can be eliminated, and protrusion of the polycrystalline silicon 7 in the trench 5 part after the nitride film 2 is eliminated can be reduced, so that the trench 5 part can be flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon semiconductor substrate, and more particularly to a method for forming a trench for element isolation on the surface of a substrate.

[0002]

In an SOI (Silicon On Insulator) substrate that is dielectrically isolated, a trench groove that reaches a buried oxide film is formed in order to perform element isolation in the lateral direction of the substrate. is there. After the trench groove is formed, an insulating film such as an oxide film is formed on the side wall of the groove and is filled with polycrystalline silicon or the like, and then the substrate surface is flattened.

FIG. 2 shows a manufacturing process in that case. A silicon oxide film (hereinafter, simply referred to as an oxide film) 12 for forming a groove on a substrate 11 manufactured by a wafer bonding method.
Are deposited (FIG. 2A). Then, dry etching (RIE) is performed using the oxide film 12 as a mask to form a trench groove 14 reaching the buried oxide film 13 (FIG. 2).
(B)).

Here, the oxide film 12 serving as a mask is also etched although its rate is smaller than that of silicon. For this reason, the oxide film is not removed during the etching for forming the groove, and the thin silicon oxide film may damage the underlying silicon (which will be the element formation surface) so that no damage occurs. The thickness of the deposited oxide film 12 is set in consideration of the oxide film thickness after etching.

When the oxide film 12 is formed by the CVD method (vapor phase growth method), the oxide film thickness varies. Further, since the etching rate of the oxide film 12 varies in the wafer surface in the groove forming step, the oxide film thickness further varies. Considering these variations, the oxide film thickness must be set so that the underlying silicon will not be damaged even in the thinnest state after etching, so the average thickness of the oxide film after etching becomes thicker. Will end up.

Thereafter, an oxide film 15 is formed on the side wall of the groove (FIG. 2 (c)), and polycrystalline silicon 16 is deposited (FIG. 2).
(D)). Then, selective polishing is performed to remove the polycrystalline silicon 16 on the mask oxide film 12 by polishing using the mask oxide film 12 as a stopper (FIG. 2E). The selective polishing is performed with a combination of a polishing agent and a polishing cloth, which polishes silicon but not oxide film.

In this selective polishing, since the oxide film 12 is not polished, if the mask oxide film 12 is removed after the selective polishing, polycrystalline silicon 16 having a height equal to the oxide film thickness is projected at the groove portion as shown in FIG. It will be. As described above, when the oxide film thickness is large, the amount of protrusion also becomes large, and when wiring is formed in the groove portion in a later step, problems such as step breakage occur.

Therefore, as shown in FIG. 4A, the polycrystalline silicon 16 in the groove portion is removed by etching or the like again by dry etching using the oxide film 12 as a mask, and then, as shown in FIG.
As shown in FIG. 5, when the oxide film 12 is removed, a step of making the polycrystalline silicon 16 as high as possible with the silicon surface is required. Further, variations in the oxide film thickness also cause variations in the amount of protrusion of polycrystalline silicon in the groove portion within the wafer surface (which also causes variations in the etching process of polycrystalline silicon in the groove portion).

Further, as shown in FIG. 5A, when there is a polishing residue 16a of polycrystalline silicon in the selective polishing,
When the oxide film 12 is removed by etching in (b), there arises a problem that the oxide film 12 cannot be removed in the region of the polishing residue 16a using it as a mask. Therefore, the polishing processing time must be set (excessive polishing) longer than the time calculated from the film thickness of polycrystalline silicon and the polishing rate, which causes a problem that throughput is deteriorated.

The various problems mentioned above are that the selective polishing is carried out by using the oxide film 12 as a stopper. Therefore, an object of the present invention is to improve the flatness of the groove portion by removing even the oxide film functioning as a mask during polishing.

[0011]

In order to achieve the above object, in the invention described in claims 1 to 3, the stopper film is formed on the surface of the silicon substrate, and then the oxide film functioning as a mask is formed. In addition, the polysilicon film and the oxide film are removed by using the stopper film as a stopper during the chemical-mechanical polishing.

Therefore, since the stopper film under the oxide film is used for polishing during the chemical-mechanical polishing, the oxide film can be removed and the flatness of the groove can be improved. The stopper film may be a silicon nitride film as described in claim 2. When the stopper film is a silicon nitride film, the oxide film can be formed only on the sidewall of the trench groove by thermal oxidation as in the third aspect of the invention.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the embodiments shown in the drawings. FIG. 1 shows a cross-sectional structure of a main part of a dielectric isolation substrate in the order of manufacturing steps. Less than,
This embodiment will be described in the order of manufacturing steps. As shown in FIG. 1A, an SOI substrate 1 manufactured by a wafer bonding method
Then, a nitride film 2 having a thickness of, for example, 20 to 30 nm is formed by a CVD method, and then an oxide film 3 is formed by a CVD method, for example, 1 μm.
Form thick. 20 to 100 nm before forming the nitride film 2
A thick pad oxide film may be formed in advance. Then, the oxide film 3 and the nitride film 2 (and the pad oxide film when the pad oxide film is formed) corresponding to the region for forming the trench isolation groove are removed by a method such as dry etching using a resist as a mask.

Next, as shown in FIG. 1B, the oxide film 3
Using the mask as a mask, a trench groove 5 (width is, for example, 2 μm) reaching the buried oxide film 4 from the substrate surface is formed by dry etching. After that, the oxide film 6 is formed on the side wall of the groove by the CVD method, the thermal oxidation method, or the like. The oxide film 6 is formed for the purpose of improving the breakdown voltage. When the oxide film 6 is formed by thermal oxidation, the oxide film does not grow on the substrate surface, and the oxide film 6 is formed only on the side wall of the groove.

Next, as shown in FIG. 1C, polycrystalline silicon 7 is deposited by LPCVD (Low Pressure Vapor Deposition), for example, to a thickness of 3 μm, and trenches 5 are buried. Next, FIG.
As shown in (d), the polycrystalline silicon 7 and the oxide film 3 are removed by chemical-mechanical polishing (selective polishing) using the nitride film 2 as a stopper. The polishing conditions are polycrystalline silicon 7
It is possible to polish the oxide film 3 and the oxide film 3,
The polishing rate of the nitride film 2 with respect to the polycrystalline silicon 7 is low. A combination of a polishing agent and a polishing cloth is used. For example, the polishing agent and polishing cloth used for planarizing the interlayer insulating film in the process of forming the multilayer wiring are used. Do it.

Next, as shown in FIG. 1E, the nitride film 2
Is removed with phosphoric acid or the like (if there is a pad oxide film, removed with hydrofluoric acid). As a result, the height at which the polycrystalline silicon 7 of the groove portion projects with respect to the substrate surface (silicon surface) becomes the thickness of the nitride film 2 (the thickness including the pad oxide film when the pad oxide film is formed). It is possible to obtain substrates that are equal and have small variations over the entire surface of the substrate.

When the pad oxide film is formed,
After removing the nitride film 2, only the polycrystalline silicon 7 in the groove may be polished again using the pad oxide film as a stopper to perform planarization polishing to make the pad oxide film surface and the polycrystalline silicon 7 at the same height. After that, by removing the oxide film, it becomes possible to form a substrate with a small flatness of the polycrystalline silicon 7 in the groove portion and good flatness. The nitride film 2
It is desirable that the thickness of both the oxide film 3 and the oxide film 3 be as thin as possible because the amount of protrusion of polycrystalline silicon can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a dielectric isolation substrate according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a conventional dielectric isolation substrate.

FIG. 3 is a diagram for explaining a problem in a conventional manufacturing process.

FIG. 4 is a diagram for explaining another problem in the conventional manufacturing process.

FIG. 5 is a diagram for explaining still another problem in the conventional manufacturing process.

[Explanation of symbols]

1 ... SOI substrate, 2 ... nitride film, 3 ... silicon oxide film, 5
… Trench trench, 7… Polycrystalline silicon.

Claims (3)

[Claims] 1. A stopper film (2) having a slower chemical-mechanical polishing rate than silicon oxide is formed on the surface of a silicon substrate (1), and a silicon oxide film (3) is formed on the stopper film. After that, the step of removing the silicon oxide film and the stopper film in the region where the trench groove is formed, the step of forming the trench groove (5) by etching using the silicon oxide film as a mask, and the polycrystalline silicon on the silicon substrate. A step of depositing (7) to fill the trench groove, and a step of removing the polycrystalline silicon and the silicon oxide film by chemical-mechanical polishing using the stopper film as a stopper. Method for manufacturing silicon semiconductor substrate. 2. The method for manufacturing a silicon semiconductor substrate according to claim 1, wherein the stopper film is a silicon nitride film. 3. After forming the trench groove, thermal oxidation is performed to form an oxide film (6) on the sidewall of the trench groove, and thereafter, an oxide film (6) is formed.
The method for manufacturing a silicon semiconductor substrate according to claim 2, wherein the trench groove is filled with the polycrystalline silicon.