JPH09167500A - Confirming device for operation of semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a confirming device for operation of a semiconductor memory which is easily set and can efficiently confirm operation of a semiconductor memory. SOLUTION: This confirming device for operation of a semiconductor memory attached with a DRAM device 1 being a body to be tested is placed on a stage 3 in a black box 9. A defect address of the DRAM 1 is accessed, and an input waveform and an output waveform at the time are observed by an oscilloscope 4. Here, photons discharged by recombination of hot electrons generated in a defect part are captured by an emission microscope 5, and displayed on a picture monitor 7. The confirming device 2 for operation of a semiconductor memory is constituted with a single substrate on which all circuits for generating an input signal and a control signal required for operating the DRAM device 1 are mounted. An address signal can be set by a manual binary switch, and an input signal can be set by a manual switch.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a DRAM (Dynamic R
and a semiconductor memory operation checking device for checking the operation of a semiconductor memory such as an andom access memory).

[0002]

2. Description of the Related Art In recent years, in semiconductor memory devices such as DRAMs (hereinafter referred to as semiconductor memories), the degree of integration has dramatically increased, and ultra-miniaturization has been further advanced. However, when such ultra-miniaturization progresses, it becomes more and more difficult to analyze the cause when the semiconductor memory causes a malfunction.

Conventionally, such an operation failure analysis of a semiconductor memory has been carried out, for example, in Japanese Patent Laid-Open Nos. 5-152408 and 5-5.
-335394, JP-A-6-5679, JP-A-6-
As disclosed in Japanese Patent Laid-Open No. 302663, Japanese Patent Laid-Open No. 7-14899, etc., it has been carried out as follows. That is, first, by using a high-precision memory LSI tester, a high-precision and high-performance pulse generator of about 24 channels, etc., after writing data to a specific address having a possibility of failure, the data is read out and its output waveform is determined. Check with an oscilloscope. Next, after confirming the defective portion based on the output waveform, the semiconductor memory is brought into an operating state and the internal state of the memory cell at that time is observed by an emission microscope. As a result, the cause of operation failure such as leak failure has been analyzed. This emission microscope counts the energy released in the form of photons when hot carriers are recombined, which are generated due to a pn junction leak of a diffusion layer of an operating semiconductor device or a breakdown of an insulating film. It is stored two-dimensionally in the memory, and this luminescent image is superposed on the optical image and output. Therefore, in order to analyze the operation failure of the semiconductor memory using this emission microscope, the emission microscope is arranged in a dark box, and the pulse generator is connected from the outside of this dark box to supply power or It was necessary to capture various signals inside the dark box.

[0004]

As described above, conventionally,
While using an expensive and highly accurate memory LSI tester,
Since it was necessary to connect the signal of the pulse generator from the outside of the dark box and take in the power supply and the signal into the dark box, the configuration of the analysis device was complicated. In particular, when the semiconductor memory has a multi-bit configuration, the number of channels for inputting address signals, clock signals, input signals and the like increases, so that the device configuration becomes more complicated. For example, the capacity is 1
A 20-channel signal line is required for an M-bit 4-bit memory, and a 40-channel signal line is required for a 4-Mbit 16-bit memory. Therefore, there is a problem that it takes a lot of labor and time to set the device, and it is not possible to efficiently check the operation of the semiconductor memory.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory operation confirmation apparatus which can easily set the apparatus and can efficiently confirm the operation of the semiconductor memory. is there.

[0006]

According to another aspect of the present invention, there is provided a semiconductor memory operation confirming device comprising a single substrate for writing and reading data to and from an arbitrary address of the semiconductor memory and confirming the memory operation. An apparatus, a memory mounting portion for mounting a test semiconductor memory to be inspected, a write data setting unit for setting data to be written to the semiconductor memory to be tested, and the semiconductor memory to be tested. Control signal generating means for generating a control signal for controlling the operation of the semiconductor memory, address setting means for setting a write address or a read address of the semiconductor memory to be tested, and data read from the semiconductor memory to be tested. Output means for receiving the address value, and the address setting means receives an arbitrary address value manually input. An address value converter for converting it into binary, 2 converted by the address value conversion unit
And a multiplexer for inputting a binary address signal to the semiconductor memory under test in a time division manner.

In this semiconductor memory operation confirmation apparatus, all the means for generating the write data and control signals necessary for operating the semiconductor memory under test are formed on a single substrate, so that it can be externally applied. The semiconductor memory under test can be operated without giving a control signal or the like. Especially,
The address value can be arbitrarily set by manual operation,
The set address value is converted into a binary number and input to the semiconductor memory under test in a time division manner. As a result, the address of the defective portion to be analyzed is specified.

According to a second aspect of the present invention, there is provided a semiconductor memory operation confirming device according to the first aspect, wherein the memory mounting portion is arranged in a central portion of the substrate.

[0009]

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a semiconductor memory analysis system to which a semiconductor memory operation confirmation device according to an embodiment of the present invention is applied. Here, the semiconductor memory to be tested will be described as a DRAM device.

This system is connected to a semiconductor memory operation confirmation device 2 equipped with a DRAM device 1 as a semiconductor memory to be tested, a stage 3 on which the semiconductor memory operation confirmation device 2 is mounted, and a semiconductor memory operation confirmation device 2. For controlling the operation of the emission oscilloscope 4, the emission microscope 5 arranged above the DRAM device 1, the image monitor 7 for displaying the image output from the emission microscope 5, and the operation of the emission microscope 5. It includes a controller 8, a semiconductor memory operation confirmation device 2 in which the DRAM device 1 is mounted, and a dark box 9 that houses the emission microscope 5.

The semiconductor memory operation confirmation device 2 is a device composed of a single substrate as shown in FIG. 3, and a semiconductor memory DR to be inspected is provided in a socket provided at the center thereof.
The AM device 1 is attached. The stage 3 is usually a movable stage used for mounting a semiconductor wafer, and has a circular shape with a diameter of about 16 cm. The oscilloscope 4 is for observing the output signal waveform from the DRAM device 1, and is arranged outside the dark box 9.
The oscilloscope 4 has an observable upper limit frequency of 1
00 MHz to 400 MHz is used. The emission microscope 5 magnifies and images the inside of the chip of the DRAM device 1, and senses weak photons emitted when hot electrons generated due to leak current in the CMOS device portion are recombined. It is for. The image monitor 7 is used to visually display the photon image sensed by the emission microscope 5 by superimposing it on the two-dimensional image inside the DRAM device 1, and is arranged outside the dark box 9.
The controller 8 is for controlling the operation and magnification of the emission microscope 5, the moving operation of the stage 3, the display state on the image monitor 7, and the like, and is arranged outside the dark box 9. The dark box 9 has a height of 150 cm and a width of 1
It is a box having dimensions of about 00 cm and a depth of about 100 cm, and is for blocking external light from entering the inside.

FIG. 2 shows a schematic configuration of an analysis system including the semiconductor memory operation checking device 2, and FIG. 3 shows an actual circuit arrangement of the semiconductor memory operation checking device 2. This semiconductor memory operation confirmation device 2 has a length of 10 cm and a width of 15 c.
A substrate 20 (FIG. 3) having a relatively small size of about m, a write data setting unit 30 (FIG. 2) for setting write data (input signal), and writing and reading to and from the DRAM device 1 (FIG. 1). A control signal generation unit 40 (FIG. 2) for generating various control signals for controlling
An address setting unit 50 (FIG. 2) for setting an address signal designating a write address or a read address of the DRAM device 1 is provided. As shown in FIG. 3, the semiconductor memory operation confirmation device 2 also inputs sockets 28 and 29 for mounting the DRAM device 1 as the semiconductor memory to be tested and the output waveform from the DRAM device 1 to the oscilloscope 4. Output waveform terminal 2 for
1 and 22 are provided. Here, the socket 28 and the output waveform terminal 21 are for a 1-bit DRAM device, and the socket 29 and the output waveform terminal 22 are
Is for a DRAM device having a 4-bit configuration. Resistors 26 and 27 for impedance adjustment are connected to the output waveform terminals 21 and 22, respectively.

The write data setting section 30 includes an input switch 1
5 and a buffer line drive circuit 16.
The input switch 15 is used for inputting data when the DRAM device 1 has a 1-bit configuration (FIG. 3) and for inputting data when the DRAM device 1 has a 4-bit configuration. Input signal of "L" level (0V) or "H" level (voltage = power supply voltage 5V plus or minus 0.5V) for each bit, which is composed of the input switches 15-2 to 15-5 (Fig. 3) used. You can enter manually. The buffer line drive circuit 16 uses a write enable signal (hereinafter,
/ WE signal. ) Becomes "L" level, the input signal from the input switch 15 is taken in and DRA
While inputting to the data input terminal (not shown) of the M device 1, when the / WE signal is at "H" level, the input signal of the DRAM device 1 is not taken in and the input terminal of the DRAM device 1 is in a high impedance state (even at "L" level, It is designed to be held at a state that is not H level). Even if the input terminal of the DRAM device 1 is in a high impedance state, this does not affect the output signal (read data.
“/” Represents a low active signal.

The control signal generator 40 includes a crystal oscillator 9 that oscillates at a frequency of several MHz by applying an electric signal, an oscillator circuit 10 that shapes the oscillation waveform of the crystal oscillator 9 into a rectangular clock signal, and an oscillator circuit. The clock signal from 10 is divided into a predetermined frequency to generate a row address strobe signal (hereinafter referred to as a / RAS signal), and a dividing circuit 11 that outputs the generated signal is output from the dividing circuit 11. The RAS signal is delayed by about 20 to 35 ns for the column
Address strobe (hereinafter referred to as / CAS signal)
Of the write enable signal / WE signal by adjusting the pulse width and the delay amount of the / RAS signal output from the frequency dividing circuit 11 by the variable resistor 24 and the variable resistor 25. A multivibrator circuit 13 for generating and outputting and an OE input switch 14 capable of inputting an output enable signal (hereinafter, referred to as / OE signal) of "L" level or "H" level by a manual operation are provided. . And the / RAS signal,
The / CAS signal, / WE signal and / OE signal are input to each control terminal (not shown) of the DRAM device 1 which is the semiconductor memory to be tested.

The address setting section 50 is capable of manually inputting an address value in hexadecimal notation, a binary switch 18 for converting the input address value into a binary address signal, and a converted binary address. The signal is divided into a row address and a column address in a time division manner, and DRA is performed.
A multiplexer circuit 17 for inputting to the address terminal of the M device 1 is provided. As shown in FIG. 3, the binary switch 18 includes a row address input switch section 18-1.
And a column address input switch section 18-2. Row address input switch section 18-1
Is one of three switches 18-for inputting three digits representing a row address among hexadecimal address values.
The column address input switch unit 18-2 includes three switches 18-21 to 18-2, each of which inputs three digits representing a column address.
Consists of three. Then, the address signal from the multiplexer 17 is input to an address input terminal (not shown) of the DRAM device 1 according to the states of the / RAS signal and the / CAS signal. That is, when the / RAS signal is at "H" level, the row address signal is not captured, and when it is at "L" level, the row address signal is captured and input to the DRAM device 1. At this time, / CAS
Since the signal is at "H" level, the column address signal is not fetched, and after that, after a delay of 20 to 35 ns, / C
When the AS signal changes from the “H” level to the “L” level, the column address signal is fetched and the DRAM device 1
Is input to

Socket 2 of semiconductor memory operation confirmation device 2
In the DRAM device 1 mounted on the 8 or 29, the above-mentioned / RAS signal, / CAS signal, / WE signal and / O signal
Input data is written to a memory cell at a specified address according to the E signal, and the data read from the memory cell is output as an output signal and input to the oscilloscope 4.

The writing and reading of data to and from the DRAM device 1 are performed as follows. That is, when the / RAS signal is at "H" level, the DRAM device 1 does not operate, and the row address signal is fetched from the address setting section 50 at the timing when this signal falls from "H" level to "L" level. Then / CA
The column address signal is fetched at the timing when the S signal falls from the “H” level to the “L” level. Here, as described above, when the / WE signal is at the "H" level, the input signal is not captured, but the input signal is captured at the timing when it becomes the "L" level. As a result, the input data is written in the memory cell at the designated address. At this time,
The / OE signal is in the "H" level state. This / O
When the E signal is at "H" level, the output waveform is in a high impedance state, and the output signal is output from the output waveform confirmation terminal 21 or 22 only when the / OE signal is set at "L" level. This output signal is input to the oscilloscope 4, and its output waveform can be observed. At this time, if the input signal is also input to the oscilloscope 4, the output waveform and the input waveform can be observed simultaneously. And if there is a difference between the two,
It can be determined that the memory cell at that address has a malfunctioning portion. When there is a defective portion in the DRAM device 1, light (photons) emitted from the defective portion enters the emission microscope 5, and the state is visually displayed on the image monitor 7. This allows, for example, CMOS
It is possible to analyze the cause of defects such as leak current in the device section. At this time, the display magnification and the like of the emission microscope 5 are controlled by the controller 8. Further, the controller 8 controls the stage driving unit 60 to move the stage 3 (FIG. 1) in a desired direction.

A method of using the semiconductor memory operation confirmation device having the above-described structure will be described. Note that here, the / WE signal is input to the oscilloscope 4 in advance.

First, a DRAM device 1 in which the mold package portion is decapped with fuming nitric acid is prepared, and this is used as a socket 28 or 2 of the semiconductor memory operation confirming device 2.
9 Next, while observing the / WE signal with the oscilloscope 4, the pulse width and the delay amount from the / RAS signal are adjusted.

Next, a specific address considered to be a defective portion is manually set by the binary switch 18 of the address setting section 50, and an input signal is manually input by the input switch 15 of the write data setting section 30. Here, when the input signal is "1", it is input as "H" level, and when it is "0", it is input as "L" level.

Next, when the / OE signal is set to the "H" level by the OE input switch 14, the input signal is written in the DRAM device 1 according to the / WE signal output from the multivibrator circuit 13. Be done. Next, O
When the / OE signal is set to the "L" level by the E input switch 14, data is read from the DRAM device 1 and input to the oscilloscope 4 as an output signal. Then, the output waveform appearing on the oscilloscope 4 is compared with the input waveform, and it is determined whether or not the designated address is a malfunctioning portion.

When it is determined that the defective portion is present, the semiconductor memory operation confirmation device 2 with the DRAM device 1 still mounted is set on the stage 3 of the dark box 9 (FIG. 1), and the emission microscope 5 analyzes the failure of the defective portion. I do.
Specifically, the controller 8 performs magnification adjustment, focusing operation, and the like to focus on the surface inside the chip of the DRAM device 1. Then, the light quantity of the emission microscope 5 is adjusted so that the inside of the chip is displayed on the image monitor 7.

Next, the DRAM device 1 is brought into a malfunctioning state, the emission time and the like are set, and the emission is started. If there is a defective portion such as a leak current in the CMOS device portion inside the chip, hot electrons are generated, so that minute photons are emitted by recombination thereof,
This is captured by the emission microscope 5 and displayed on the image monitor 7. This image is recorded in an image recording device (not shown).

Then, if necessary, the defective portion inside the chip of the DRAM device 1 is etched back to remove the upper layer portion of the element structure, and the cause analysis is performed while observing the external appearance using a SEM (scanning electron microscope). To do.

As described above, in this embodiment, since the target address can be set by the manual binary switch, the operation of the DRAM device 1 can be performed by an extremely simple operation without using the pulse generator which has been conventionally used. Confirmation can be done. Further, the circuits for generating all the signals necessary for operating the DRAM device 1 are arranged on a single substrate of a relatively small size, and the DRAM device 1 to be tested is mounted on this substrate. Since this is done, the DRAM device can be put into operation by simply setting this substrate (semiconductor memory operation confirming device 2) in the dark box 9, and as in the conventional case, a large number of signal wirings can be provided in the dark box 9.
The setting work of pulling in from the outside to the inside and connecting is unnecessary. Moreover, since the subject (DRAM device 1) is mounted on the central portion of the substrate, observation by the emission microscope 5 becomes easy.

In this embodiment, the operation can be confirmed by mounting the 1-bit DRAM device and the 4-bit DRAM device, but a DRAM device having a larger number of bits (for example, 16 bits) is also installed. It is also possible to configure so that it can.

Although the DRAM device has been described as an example in the present embodiment, the present invention is not limited to this, and other semiconductor memory operation confirming device, for example, SRA.
It goes without saying that the present invention can also be applied to an M device, a ROM device, an EEPROM, a flash memory and the like.

[0029]

As described above, according to the semiconductor memory operation confirming apparatus of the present invention, all the means for generating the write data and the control signal necessary for operating the semiconductor memory to be tested are provided. Since it is formed on one substrate, when analyzing a defective part using an emission microscope, the semiconductor memory operation confirmation device equipped with the semiconductor memory to be tested is set in the dark box to Can be activated. Therefore, unlike the conventional case, the complicated setting work of pulling in a large number of signal wirings from the outside of the dark box to the inside and connecting them is not necessary, and the labor and time in the defect location analysis can be reduced. Further, since an arbitrary address value can be set by a manual operation, the operation is extremely simple as compared with the conventional case where a pulse generator is used.

In particular, according to the semiconductor memory operation confirmation apparatus of the second aspect, since the semiconductor memory to be tested is arranged in the central portion of the substrate, the observation with the emission microscope is easy.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a semiconductor memory analysis system using a semiconductor memory operation confirmation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a semiconductor memory operation confirmation device and its peripheral device according to an embodiment of the present invention.

FIG. 3 is an external view showing a circuit arrangement of the semiconductor memory operation checking device.

[Explanation of symbols]

 1 DRAM device 2 Semiconductor memory operation confirmation device 3 Stage 4 Oscilloscope 5 Emission microscope 7 Image monitor 8 Controller 9 Dark box 30 Data input section 40 Control signal generation section 50 Address setting section 17 Multiplexer 18 Binary switch 18-1 Row address input switch Section 18-2 Column address input switch section

Claims (2)

[Claims] 1. An arbitrary address of a semiconductor memory,
An apparatus comprising a single substrate for writing and reading data and confirming memory operation, comprising: a memory mounting part for mounting a semiconductor memory to be tested, and writing to the semiconductor memory to be tested. Write data setting means for setting target data; control signal generating means for generating a control signal for controlling the operation of the semiconductor memory under test; and a write address or a read address of the semiconductor memory under test. An address setting unit for setting and an output unit for outputting the data read from the semiconductor memory under test are provided, and the address setting unit receives an arbitrary address value input by a manual operation and outputs it. An address value conversion unit for converting to a binary number and a binary address signal converted by this address value conversion unit Semiconductor memory operation check device characterized by comprising a multiplexer for inputting the split to the subject semiconductor memory. 2. The semiconductor memory operation checking device according to claim 1, wherein the memory mounting portion is arranged in a central portion of the substrate.