JPH09101888A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase response speed for a branch instruction and exception processing. SOLUTION: A data bus 6-9 and bidirectional switches 5-7, 5-8 for setting up an immediate value in a program counter 2-3 directly from a decoder 1 without passing a data bus 6-6 to an operation part 2-1 are added to a microprocessor for executing exception processing by the use of a branch instruction and an internal vector. The microprocessor is also provided with a data bus 6-10 and a switch 5-9 for setting up a register value in the counter 2-3 directly from a register file 2-2 without passing the data bus 6-6 of the operation part 2-1. Consequently the branched address of an immediate branch instruction is set up in the counter 2-3 directly from the decoder 1 through the data bus 6-9 and that of a register direct branch instruction is set up in the counter 2-3 directly from the register file 2-2 through the data bus 6-10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for speeding up the response speed of exception handling executed by a branch instruction and an internal vector in a microprocessor.

[0002]

2. Description of the Related Art Conventionally, instruction address arithmetic in a microprocessor includes constant value arithmetic with an instruction address in a normal instruction and indefinite value arithmetic such as a branch instruction. Generally, a normal instruction is calculated at the IF (instruction read) stage, and a branch instruction or the like is calculated at the EX (operation) stage. Among branch instructions, there are addressing modes such as program counter relative branch, immediate branch, and register direct branch. The program counter relative branch calculates the program counter and the relative value in the EX stage. On the other hand, in the immediate branch and the register direct branch, since the branch address is an absolute value, processing is performed to set the absolute value in the program counter at the EX stage (“H8 / 327, SH7032 programming manual, RISC system: Kaibundou”). ).

As an example of such a conventional technique, a microprocessor adopting 5-stage pipeline processing will be described. The five stages are IF (instruction read),
It is divided into ID (instruction decoding), EX (operation), MA (memory access), and WB (write back), and the normal pipeline stage flow is as shown in FIG.

As shown in FIG. 6, the conventional microprocessor has a decoder 1 and a data path 2. The data path 2 includes an arithmetic unit 2-1 that performs logical operation, arithmetic operation, shift operation, etc., a register file 2-2 that stores the operation result, a program counter 2-3 that counts the address of the current program, Calculation unit 2-1
Alternatively, an address unit 2-4 for switching the output from the program counter 2-3 to the address bus 4 is provided. The arithmetic units 2-1 to address units 2-4 are controlled by the control buses 7-1 to 7-4 from the decoder 1, respectively.

Then, the microprocessor specifies an address in a memory (not shown) by outputting data via the address bus 4, and the instruction stored at the address is stored in the memory via the data bus 3. The decoder 1 decodes this instruction to control the data path 2.

Further, an immediate bus 6-1 is provided from the decoder 1 to the arithmetic unit 2-1, and read buses 6-2 and 6-4 for reading data from the register file 2-2.
An input bus 6-3, 6-5 to the arithmetic unit 2-1; an output bus 6-7 for the arithmetic result of the arithmetic unit 2-1; a read bus 6-7 from the program counter 2-3; An input bus 6-8 to the address unit 2-4 is provided, and as shown in the figure,
In the bidirectional switches 5-1 to 5-6, the above-mentioned bus 6-1 and
6-2, 6-4, 6-5, 6-6, 6-7 are configured to be switched.

Each stage of IF to WB and data path 2
Correspondence with the operation timings of the respective units 2-1 to 2-4 is as follows. That is, the program counter unit 2-3 at the IF stage, the control unit (decoder 1) and the register file 2-2 at the ID stage, the arithmetic unit 2-1 at the EX stage, and the address unit 2 at the MA stage. -4, and the register file 2-2 operates during the WB stage.

Immediate branching in this conventional microprocessor has a pipeline stage flow as shown in FIG. That is, the branch destination address decoded by the decoder 1 enters the arithmetic unit 2-1 from the immediate bus 6-1 in the subsequent EX stage 301, and passes through the output bus 6-6 to the program counter 2-.
Set to 3.

Similarly, in the register direct branch in the conventional microprocessor, the branch destination address is read from the register file 2-2 and is input to the arithmetic unit 2-1 through the buses 6-4 and 6-5. 2-1 to Bus 6-
6 is set in the program counter 2-3 via 6.

[0010]

As described above, in the conventional microprocessor, the response to the branch instruction or the exception processing must always set the address in the program counter 2-3 via the operation unit 2-1. Since it is configured, there is a problem in that the processing speed must be slowed when viewed from the processing stage without fail.

Therefore, an object of the present invention is to speed up the response speed of branch instructions and exception handling.

[0012]

In order to achieve the above object, the present invention provides a bus for directly setting an immediate value from a decoder to a program counter without passing through an output bus of an arithmetic unit, and the bus and the above-mentioned bus. A switch for switching between the output bus and the output bus, or a bus for setting a register value directly from the register file to the program counter without passing through the output bus of the arithmetic unit, and a switch for switching the bus and the output bus. And is provided.

According to the former configuration, when the immediate branch is performed, the output bus is closed and the bus added for direct setting from the decoder is opened, so that the decoder can directly output the signal without passing through the arithmetic unit. The branch destination address can be set in the program counter.

Further, according to the latter configuration, when the register direct branch is performed, the output bus is closed and the bus added for direct setting from the register is opened so that the register is not passed through the arithmetic unit. Directly from
The branch destination address can be set in the program counter.

In this way, according to the present invention, since the branch destination address can be set in the stage before the EX stage, the response speed to the branch instruction and the exception processing can be increased. Further, even when the program is reset, the initial value can be set in the ID stage without passing through the EX stage, and there is an effect that the state in which the initial value is indefinite becomes short.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described. [First Embodiment] FIG. 1 is a block diagram of a microprocessor showing an example of an embodiment of the present invention. This microprocessor is for realizing speeding up for immediate branching.

As can be seen from comparison with the conventional example shown in FIG. 6, this microprocessor has an immediate bus 6-9 having both switches 5-7 for directly setting the immediate value from the decoder 1 to the program counter 2-3.
And the addition of a new bidirectional switch 5-8 in the output bus 6-6.

The flow of the pipeline at the time of immediate branch in this microprocessor is as shown in FIG. That is, the immediate branch instruction is the IF stage 5
When fetched at 00, this instruction returns ID stage 5
At the same time, the program counter 2-3 is decoded by the decoder 1 at 01, and at the same time via the immediate bus 6-9.
Is set directly to. Therefore, since it is not necessary to execute the next EX stage, the instruction from the branch destination address can be immediately fetched and the processing can be started in the (n + 2) th processing cycle. At this time, the switch 5-7 is opened and the switch 5-8 is closed to switch the data input bus to the program counter 2-3.

Thus, according to the first embodiment, the speed of immediate branching can be increased. [Second Embodiment] FIG. 3 is a block diagram of a microprocessor showing another example of the embodiment of the present invention. This microprocessor is for realizing a high speed for the direct branch of the register.

As can be seen by comparing this microprocessor with the conventional example of FIG. 6, first, as in the first embodiment, the bidirectional switch 5-8 is provided in the output bus 6-6 from the arithmetic unit 2-1. The difference is that is added. In addition, the bidirectional switch 5-4 in the input bus 6-5 and the arithmetic unit 2-1.
Bidirectional switch 5-6 in the output bus 6-6.
8 and a bus 6-9 for direct setting is newly added so as to connect the point between the counter 8 and the program counter 2-3. A bidirectional switch 5-9 is provided on the newly added bus 6-10.

When register direct branch processing is performed, the bidirectional switches 5-3 and 5-9 are opened and the bidirectional switch 5-8 is closed. As a result, the data in the register file is directly set to the program counter 2-3 via the newly added bus 6-10 for direct setting. Therefore, also in this case, as in the case of the first embodiment, since the calculation unit 2-1 is not used, EX
The branch address can be set immediately after the setting of the branch destination address is completed in the stage before the stage.

Thus, according to the second embodiment, it is possible to accelerate the address direct branching. [Third Embodiment] As shown in FIG. 4, by combining the first and second embodiments, it is possible to obtain a high-speed microprocessor for both immediate branch and register direct branch. In this case, both of the effects of the first and second embodiments described above can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a microprocessor according to a first embodiment of the invention.

FIG. 2 is a schematic diagram showing an operation of pipeline processing in the case of immediate branching according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing an overall configuration of a microprocessor according to a second embodiment of the invention.

FIG. 4 is a block diagram showing an overall configuration of a microprocessor according to a third embodiment of the invention.

FIG. 5 is a schematic diagram showing an operation of pipeline processing in a conventional example.

FIG. 6 is a block diagram showing an overall configuration of a conventional microprocessor.

FIG. 7 is a schematic diagram showing an operation of pipeline processing in a conventional example.

[Explanation of symbols]

1 ... Decoder, 2 ... Data path, 2-1 ...
Calculation unit, 2-2 ... Register file, 2-3 ...
Program counter, 2-4 ... Address unit,
3 ... Data bus, 4 ... Address bus, 5-1 to 5-1
5-9 ... Bidirectional switch, 6-1 to 6-10 ...
Bus, 7-1 to 7-4 ... Control bus.

Claims (2)

[Claims] 1. A microprocessor for performing exception processing by a branch instruction and an internal vector, a bus for directly setting an immediate value from a decoder to a program counter without passing through an output bus of an arithmetic unit, the bus and the output. A microprocessor having a switch for switching between a bus and the bus. 2. A microprocessor for performing exception processing by a branch instruction and an internal vector, a bus for directly setting a register value from a register file to a program counter without passing through an output bus of an arithmetic unit, the bus and the bus. A microprocessor comprising a switch for switching between an output bus and the output bus.