JPH0878400A - Pattern formation method of silicon-based material layer - Google Patents

Abstract

(57) [Summary] [Object] To provide a method for forming a pattern of a silicon-based material layer capable of forming a fine pattern finer than the resolution limit of a lithography technique with high productivity. [Structure] In the first step, a silicon substrate 10 as a substrate
A gate oxide film 11 that is an insulating film, a polycrystalline silicon layer 12 that is a silicon-based material layer, and a resist film 13 are sequentially formed on the surface of. After that, the resist film 13 is patterned. In the second step, the patterned resist film 13 is isotropically etched, and at the same time, the polycrystalline silicon layer 12 is anisotropically etched by almost the thickness thereof. In this step, an etching gas containing at least one of sulfur difluoride, sulfur difluoride, sulfur tetrafluoride, and sulfur difluoride is used. Then, in the third step, an etching gas containing at least one kind of halogen other than fluorine is used to etch the polycrystalline silicon layer 12
The remaining portion 12a of is etched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method for a silicon-based material layer such as a polycrystalline silicon layer or a tungsten polycide layer.

[0002]

2. Description of the Related Art In recent years, design rules of semiconductor devices have been highly miniaturized as seen in VLSI and ULSI. Along with this, for example, in the fine processing of a transistor gate electrode made of a silicon-based material layer such as a polycrystalline silicon layer or a tungsten polycide layer, an accurate resist mask exposure / development technique that matches a desired gate length is particularly required. Has become. Therefore, a method for forming a fine resist pattern has been studied and implemented.

For example, there is an electron beam direct writing technique. This method is a method of forming a fine pattern that is two or more generations ahead of the conventional lithographic technology that can be mass-produced. In addition, the resist ashing method is also widely used. In the resist ashing method, a resist finely processed to a critical dimension by a lithography technique is further ashed by oxygen plasma or oxygen radicals to form a resist pattern finer than the limit of the lithography technique.

After forming a fine resist pattern by the above method, the gate electrode is obtained by dry etching which proceeds in the process shown in FIG. Figure 2
In the case where the gate oxide film 21, the polycrystalline silicon layer 22 and the fine resist pattern 23 are sequentially formed on the surface of the silicon substrate 20 as shown in (a), the polycrystalline silicon layer 22 is formed by using, for example, a halogen-based gas. Dry etching.

Then, as shown in FIG. 2B, the polycrystalline silicon layer 22 is anisotropically etched, and reaction products generated by the etching adhere to the resist pattern 23 and the sidewalls of the polycrystalline silicon layer 22. As a result, the sidewall protection film 24 is formed. Therefore, as shown in FIG.
A gate electrode made of the polycrystalline silicon layer 22 that is faithfully etched to the line width α of the resist pattern 23 is obtained.

[0006]

However, the electron beam direct writing method and the resist ashing method described above have the following problems. In the case of the electron beam direct writing method, since the pattern is directly written on the entire surface of the resist, it takes a long time to process the entire surface of the substrate. Further, in order to use this resist as a resist pattern that can withstand the subsequent dry etching step, it is necessary to adopt a multilayer resist method. Therefore, the productivity is low and the cost is high.

Further, in the resist ashing method, the resist is thinned by the ashing before the dry etching step, and the uniformity of the resist line width cannot be obtained. Furthermore, since an ashing process is inserted between the resist pattern forming process by the lithography technique and the dry etching process, the number of processes is increased from the viewpoint of process flow. Therefore, even in the resist ashing method, productivity is a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a pattern forming method of a silicon-based material layer capable of forming a fine pattern finer than the resolution limit of a lithography technique with high productivity. I am trying.

[0009]

In the method of forming a pattern of a silicon-based material layer of the present invention, first, in a first step, an insulating film, a silicon-based material layer and a resist film are sequentially formed on the surface of a substrate. Then, the resist film is patterned. Next, in a second step, the patterned resist film is isotropically etched, and at the same time, substantially the thickness of the recon-type material layer is anisotropically etched. In this step, an etching gas containing at least one of sulfur difluoride, sulfur difluoride, sulfur tetrafluoride, and sulfur difluoride is used. Next, in the third step,
The remaining portion of the silicon-based material layer is etched using an etching gas containing at least one kind of halogen other than fluorine.

The etching gas used in the second step may contain a nitrogen compound. In addition, the etching gas used in the third step may contain an oxygen-based compound. Further, when performing the second step, it is preferable to maintain the substrate at a predetermined temperature within the range of 0 ° C to 70 ° C.

[0011]

In the present invention, at the same time as anisotropic etching of the silicon-based material layer in the second step, isotropic etching of the patterned resist film proceeds. for that reason,
The resist film is processed finer than the size formed in the first step. The silicon-based material layer is finely processed to have substantially the same dimensions as the resist film by anisotropic etching that proceeds at the same time. Further, the etching gas used in the third step is a gas having a high selection ratio of the silicon-based material layer to the insulating film, unlike the fluorine-based gas. Therefore, the insulating film is not damaged in the third step.

When the substrate is kept at a predetermined temperature in the range of 0 ° C. to 70 ° C. in the second step, it is 0 ° C. or higher,
Adsorption of sulfur fluoride contained in the etching gas onto the side wall of the resist by sulfur is suppressed. As a result, isotropic etching of the resist film is performed. Further, since the temperature is 70 ° C. or lower, the etching resistance of the resist film does not deteriorate.

[0013]

EXAMPLE An example of a method of forming a pattern of a silicon-based material layer according to the present invention will be described below with reference to the process chart shown in FIG. In this embodiment, the pattern formation of the transistor gate electrode will be described as an example. In the first step shown in FIG. 1A, first, an insulating film made of silicon oxide, that is, a gate oxide film 11 is formed on the surface of a silicon substrate 10 as a base by a diffusion furnace. At this time, the gate oxide film 11 is formed to have a film thickness of, for example, about 8 nm.

Next, a reduced pressure chemical vapor deposition method (hereinafter, referred to as
A polycrystalline silicon layer 12 as a silicon-based material layer is formed on the gate oxide film 11 by the CVD method). At the time of film formation, the polycrystalline silicon layer 12 is doped with impurities. Then, in order to diffuse and activate the impurities in the polycrystalline silicon layer 12 with good uniformity, for example, about 8
Annealing is performed at 50 ° C. for about 10 minutes.

Then, a photoresist film (hereinafter abbreviated as resist film) 13 is formed on the polycrystalline silicon layer 12 by spin coating. Then, the resist film 13 is patterned by an excimer laser stepper. In this patterning, exposure and development are performed so that the line width β of the patterned resist film 13 is, for example, about 0.30 μm, which is close to the critical processing dimension of the excimer laser stepper.

Next, the second step shown in FIG. 1B is performed.
In the second step, the patterned resist film 13 is isotropically etched and, at the same time, substantially the thickness of the polycrystalline silicon layer 12 is anisotropically etched. The etching gas for this just etching is sulfur difluoride (S
₂ F ₂ ), sulfur difluoride (S ₂ F), sulfur tetrafluoride (SF ₄ ) and at least one sulfur difluoride (S ₂ F ₁₀ ) gas containing sulfur fluoride is used.
Further, the etching gas may contain a nitrogen compound.

Further, in the just etching,
The silicon substrate 10 is maintained at a predetermined temperature within the range of 0 ° C to 70 ° C.

For example, the etching gas is S ₂ F ₂ and E
An example of just etching conditions when using a CR (Electron Cyclotron Resonance) type etching apparatus is shown below. Microwave supply power = 850W (2.45W
GHz), magnetic field strength = 87.5 mT (875 G), chamber pressure = 1.3 Pa, radio frequency (RF) bias power = 100 W, silicon substrate temperature = 30 ° C., S ₂ F ₂
Gas flow rate = 100 ml / min.

An example of conditions for just etching with a magnetron RIE (Reactive Ion Etching) type etching apparatus using the same etching gas as described above is shown below. Magnetic field strength = 20 mT (200 G),
Chamber pressure = 2.5 Pa, radio frequency (RF) bias power = 250 W, silicon substrate temperature = 30 ° C., S ₂
F ₂ gas flow rate = 100 ml / min.

In such just etching, as shown in FIG.
As shown in (b), the remaining portion 1 is left on the polycrystalline silicon layer 12.
2a remains. Therefore, after the second step, overetching of the third step shown in FIG. 1C is performed. That is, in the third step, the remaining portion 12a of the polycrystalline silicon layer 12 is etched using the etching gas containing at least one kind of halogen other than fluorine as described above. The etching gas used for overetching may contain an oxygen-based compound.

Specific examples of the etching gas include a mixed gas of hydrogen bromide (HBr) and chlorine (Cl ₂ ), a mixed gas of HBr and O ₂ , a mixed gas of Cl ₂ and O ₂ , and H 2.
A mixed gas of Br, Cl _2, and O ₂ can be used.

An example of overetching conditions when an ECR type etching apparatus is used with a mixed gas of HBr and Cl ₂ as an etching gas is shown below. Microwave supply power = 850 W (2.45 GHz), magnetic field strength = 87.5 mT (875 G), chamber pressure = 1.3 Pa, radio frequency (RF) bias power = 60 W,
Silicon substrate temperature = 30 ° C., HBr / Cl ₂ gas flow rate = 120/10 ml / min.

An example of conditions for over-etching with a magnetron RIE type etching apparatus using the same etching gas as above is shown below. Magnetic field strength = 2
0mT (200G), chamber pressure = 2.5
Pa, radio frequency (RF) bias power = 120 W, silicon substrate temperature = 30 ° C., HBr / Cl ₂ gas flow rate = 200
/ 30 ml / min.

By this over-etching, the polycrystalline silicon layer 12 having a line width γ of about 0.18 μm, which is about 3/5 finer than the size close to the resolution limit of the excimer laser stepper.
Pattern is formed. That is, a pattern of the gate electrode having a very fine gate length γ of about 0.18 μm can be obtained.

In the just etching of the second step of the above embodiment, the resist film 13 reacts with the fluorine of sulfur fluoride contained in the etching gas. Then, a fluorine-based compound (CF _x ) is generated, and the product is exhausted without adhering to the sidewall of the anisotropically etched polycrystalline silicon layer 12. Therefore, the isotropic etching of the resist film 13 patterned as described above and the anisotropic etching of approximately the thickness of the polycrystalline silicon layer 12 simultaneously proceed.

As a result, the line width γ of the resist film 13 is processed to be thinner than the finished line width dimension β of the exposure and development in the first step. Moreover, the polycrystal silicon layer 12 is formed into the resist film 13 by the anisotropic etching which proceeds at the same time.
Finely processed to have a line width dimension substantially equal to the line width γ of. Further, unlike the ashing, the resist film 13 is finely processed by etching with good controllability, so that the uniformity of the line width γ of the resist film 13 can be secured.

Under the discharge dissociation condition, at least one sulfur fluoride contained in the etching gas is dissociated to generate sulfur (S). Since the generated sulfur is adsorbed on the side wall of the anisotropically etched polycrystalline silicon layer 12, the undercut of the polycrystalline silicon layer 12 is prevented. Therefore, the side wall of the polycrystalline silicon layer 12 is processed perpendicularly to the surface of the silicon substrate 10.

Further, when the etching gas contains a nitrogen compound, for example, a sulfur nitride compound made of SN polymer is adsorbed on the side wall of the anisotropically etched polycrystalline silicon layer 12. Therefore, even when such an etching gas is used, undercut of the polycrystalline silicon layer 12 is prevented.

It is generally known that with a sulfur-based gas, anisotropic etching easily proceeds at a temperature lower than 0 ° C. However, in the second step, the silicon substrate 10 is maintained at a predetermined temperature within the range of 0 ° C to 70 ° C. Therefore, the adsorption of sulfur fluoride contained in the etching gas onto the side wall of the resist film 13 by sulfur is suppressed, and the resist film 13 is isotropically etched. The upper limit of the holding temperature of the silicon substrate 10 is set to 70 ° C. because the etching resistance of the resist film 13 may deteriorate and the function as a mask may not be achieved.

By setting the temperature of the silicon substrate 10 as described above, the adsorption of the sulfur-based compound on the side wall of the polycrystalline silicon layer 12 is suppressed, but the polycrystalline silicon is controlled by controlling the RF bias power. The sidewalls of layer 12 can be processed perpendicular to the surface of silicon substrate 10.

On the other hand, the etching gas containing at least one kind of halogen other than fluorine used in the third step is a gas having a high selection ratio of the polycrystalline silicon layer 12 to the gate oxide film 11 unlike a fluorine-based gas. Therefore, the remaining portion 12a of the polycrystalline silicon layer 12 can be etched without damaging the gate oxide film 11.

Further, during etching, a silicon-based reaction product (for example, SiCl _x or SiBr _x ) is produced. Since the generated silicon-based reaction product is deposited on the sidewalls of the resist film 13 and the polycrystalline silicon layer 12, undercut of the polycrystalline silicon layer 12 is prevented.

When the etching gas contains an oxygen-based compound, a silicon oxide-based compound (eg, SiO, SiO ₂ , SiOBr, etc.) is adsorbed on the sidewalls of the resist film 13 and the polycrystalline silicon layer 12, so that overetching occurs. In this case, the side wall is further protected.

Therefore, in the above embodiment, it is possible to form a gate electrode pattern having a line width γ which is finer and more uniform than the resolution limit of the lithography technique without damaging the gate oxide film 11. Moreover, since the isotropic etching of the resist film 13 and the anisotropic etching of the polycrystalline silicon layer 12 are performed in one step, the number of steps is reduced as compared with the conventional resist ashing method. Further, the resist film 13 can be processed finer than the resolution limit of the lithography technique in a short time as compared with the electron beam direct writing method. Therefore, it is possible to improve productivity and reduce costs associated therewith.

[0035]

As described above, according to the present invention, the resist film patterned in the second step is isotropically etched, and at the same time, the silicon-based material layer is anisotropically etched. Therefore, in one step, the resist film can be processed finer than the size formed in the first step, and the silicon-based material layer can be processed finely to the size of the resist film. Also the third
Unlike the fluorine-based gas, the etching gas used in the process has a high selection ratio of the silicon-based material layer to the insulating film, so the remaining part of the silicon-based material layer should be etched without damaging the insulating film. You can

Therefore, according to the present invention, a pattern of a silicon-based material layer finer than the resolution limit of the lithography technique can be formed with high productivity and at low cost as compared with the conventional method.

When the substrate is kept at a predetermined temperature within the range of 0 ° C. to 70 ° C. in the second step, the isotropic etching of the resist film progresses due to the sulfur fluoride contained in the etching gas. Therefore, the resist film can be surely finely processed.

[Brief description of drawings]

FIG. 1 is a process drawing showing an example of the present invention.

FIG. 2 is a process chart showing an example of a conventional method.

[Explanation of symbols]

 10 Silicon Substrate (Base) 11 Gate Oxide Film (Insulating Film) 12 Polycrystalline Silicon Layer (Silicon Material Layer) 13 Resist Film 13a Remaining Part

Claims (4)

[Claims] 1. A first step of patterning the resist film after sequentially forming an insulating film, a silicon-based material layer, and a resist film on the surface of the substrate, and sulfur difluoride, sulfur difluoride, and tetrafluoride. The patterned resist film is isotropically etched using an etching gas containing at least one kind of sulfur fluoride and sulfur difluoride, and at the same time, a substantially layer thickness of the silicon-based material layer is reduced. A silicon-based material comprising a second step of anisotropic etching and a third step of etching the remaining portion of the silicon-based material layer using an etching gas containing at least one kind of halogen other than fluorine. Layer patterning method. 2. The pattern formation method for a silicon-based material layer according to claim 1, wherein the etching gas used in the second step contains a nitrogen-based compound. Method. 3. The silicon-based material layer pattern forming method according to claim 1 or 2, wherein the etching gas used in the third step contains an oxygen-based compound. Layer patterning method. 4. The method for forming a pattern of a silicon-based material layer according to claim 1, claim 2, or claim 3, wherein when performing the second step, the substrate is set to a predetermined temperature within a range of 0 ° C to 70 ° C. A method for forming a pattern of a silicon-based material layer, which is characterized by holding at a temperature.