JPH0785670A - Sense amplifier drive circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To shorten the access time of the semiconductor memory device by shortening the amplification time of the bit line by the sense amplifier row separated from the power supply and ground pins. [Configuration] Memory cell data is bit lines BL1 to BL
The drive signals φp and φn are input to the drive signal generating means 3 in a state where they appear at 3 and a minute potential difference is generated. The driving signal generating means 3 has the same number of 3 as the sense amplifier driving means 1a to 1c.
Drive signals φpa, φna having a pair of different delay amounts
.phi.pc and .phi.nc are generated and input to the corresponding sense amplifier driving means 1a-1c. Therefore, the sense amplifier driving means 1a farthest from the power source 7 and the ground pin 8 can be driven first, so that the sense amplifier driving means 1 can be driven.
The voltage drop with respect to a can be suppressed low, the supply current can be increased, the drive end time of the corresponding sense amplifier row 2a can be shortened, and the time required for amplification of all the bit lines BL1 to BL3 can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a sense amplifier drive circuit in a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a sense amplifier drive circuit in a conventional semiconductor memory device. In the figure, reference numeral 5 is a sense amplifier, 2a, 2b and 2c are sense amplifier rows each composed of a plurality of sense amplifiers 5 ...
Reference numerals 1b and 1c denote sense amplifier driving circuits for driving the sense amplifier rows 2a to 2c, respectively, and φp and φn are a pair of driving signals, and the sense amplifier driving circuits 1a to 1c are provided.
Input to c. 6a, 6b and 6c are memory cell arrays. ROW is a row address signal, 4 is a row decoder, and drives any one of the plurality of word lines WL by the row address signal ROW. BL1, BL2,
BL3 is a bit line, respectively. Power is supplied to the sense amplifier drive circuits 1a to 1c in either direction from the power supply 7 and the ground pin 8 through the wiring 9.
In the case of the connection as shown in the above, the distance from the power supply 7 and the ground pin 8 to the sense amplifier drive circuits 1a to 1c is
The sense amplifier drive circuit 1c is the shortest, the sense amplifier drive circuit 1b is next, and the sense amplifier drive circuit 1a is the farthest.

Next, the driving operation of the sense amplifier having the above configuration will be described. Row address ROW
Is input and the word line WL is driven by the row decoder, the data in the selected memory cell is transferred to the bit line BL.
1 and BL2 and BL3, which causes a minute potential difference. The pair of drive signals φp and φn are simultaneously input to the sense amplifier drive circuits 1a to 1c, and the sense amplifier drive circuit 1a
a generates a pair of sense amplifier drive signals SAPa and SANa to drive the corresponding sense amplifier 2a, and similarly the sense amplifier drive circuit 1b causes the sense amplifier drive signal SAP to be generated.
b, SANb to drive the sense amplifier 2b, and the sense amplifier drive circuit 1c causes the sense amplifier drive signal SAP
c and SANc are generated to drive the sense amplifier 2c.

Driven sense amplifier rows 2a, 2b, 2c
Amplifies the minute potential difference on the corresponding bit lines BL1 to BL3. FIG. 4 is a timing chart of the sense amplifier driving operation, in which the vertical axis represents voltage and the horizontal axis represents time. In the same figure, the data of the memory cell is output onto the bit lines BL1 to BL3 at the rising T of the word line WL, and at each subsequent time T1, the sense amplifier drive signals SAPa and SANa.
~ Each bit line BL1 by inputting SAPc, SANc
It is shown that it takes Tb before BL3 is amplified and all bit lines BL1 to BL3 are amplified.

[0005]

However, in the above conventional configuration, the drive signals φp and φn are simultaneously input to the plurality of sense amplifier drive circuits 1a to 1c, and the plurality of sense amplifier drive circuits operate simultaneously. To get started
The distance between these sense amplifier drive circuits and the power supply and ground pins poses a problem.

That is, a plurality of sense amplifier drive circuits 1
Since the wiring resistance Ri exists in the wiring 9 for power supply between a to 1c and the power supply 7 and the ground pin 8,
Letting Ia, Ib, and Ic be the currents flowing from these to the power supply 7 and the ground pin 8 by the simultaneous start of the plurality of sense amplifier drive circuits 1a to 1c, the potential at the point C in the figure is Vc = Ri.Ic, The potential at point B in the figure is Vb = Ri · I
c + 2Ri · Ib, and the potential at point A in the figure is Va = Ri
・ Ic + 2RiIb + 3RiIa, resulting in a difference in potentials at points A, B, and C due to the voltage drop, and the effect of the voltage drop becomes greater as the sense amplifier drive circuit is farther from the power supply 7 and the ground pin 8. As a result, the supply current value decreases as the sense amplifier drive circuit 1a is farther away from the power supply 7 or the like, and the ability of the sense amplifier drive circuit to activate the sense amplifier (hereinafter referred to as the sense amplifier drive circuit ability) decreases. There is a problem in that the amplification capability of the sense amplifier decreases as the distance from the power supply 7 increases, and it takes time to amplify all the bit lines, which causes a delay in the operation of the semiconductor memory device.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to shorten the drive end time of the sense amplifier by increasing the capability of the sense amplifier drive circuit at a position distant from the power supply and ground pins. Then, the amplification time of the bit line is shortened and the operation time of the semiconductor memory device is shortened.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a power supply for a power supply to a sense amplifier driving circuit which is separated from a power supply and a ground pin by limiting the voltage drop to a small value. The operation start time of each sense amplifier drive circuit is made different so that the operation can be independently started before the operation of the sense amplifier drive circuit close to the same.

Specifically, the configuration of the present invention is a sense amplifier drive circuit for driving a plurality of sense amplifier rows for amplifying a minute potential difference of a bit line, which is provided for each of the sense amplifier rows and is common. A plurality of sense amplifier driving means that receives power from a power source and a common ground pin to drive the corresponding sense amplifier row, and a drive signal that generates a plurality of drive signals with different delay amounts with respect to the input drive signal. Generating means is provided, and each of the plurality of drive signals of different delay amounts generated by the drive signal generating means is input to each of the sense amplifier driving means to drive the plurality of sense amplifier rows.

[0010]

With this configuration, in the present invention, the timings of the drive signals input to the plurality of sense amplifier drive means are changed for each sense amplifier drive circuit, and input to the sense amplifier drive means having a short distance from the power supply and ground pins. The delay amount given to the drive signal is set to be large, and the delay amount given to the drive signal to be input to the sense amplifier driving means at a long distance is set to be small. As a result, the operation timing of the sense amplifier driving means having a short distance from the power supply and ground pins is delayed, and the distance from the power supply and the ground pin is shortest until the sense amplifier driving means having a short distance starts to operate. Since the remote sense amplifier driving means starts to operate,
In the sense amplifier driving means separated by this distance, the current value is held relatively large without being affected by the voltage drop due to the operation of the other sense amplifier driving means, and the driving end time of the sense amplifier is shortened. Therefore, it is possible to shorten the operation end time of the sense amplifier farthest from the power supply and ground pins, which has been a cause of hindering the shortening of access time in the past, and shorten the bit line amplification time. The time can be shortened.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a sense amplifier drive circuit according to the present invention. In the figure, 3 is a drive signal generating means, which is a pair of input drive signals φp, φ.
A plurality of pairs (3 pairs in FIG. 1) of driving signals (φpa, φna), (φpb, φnb) and (φ) with different delay amounts with respect to n.
pc, φnc) and drive signal φp
a and φna have the smallest delay amount, and then the drive signal φp
b, φnb have a small delay amount, and drive signals φpc, φnc
Has the largest amount of delay.

Further, 6a, 6b and 6c are memory cell arrays, ROW is a row address signal, 4 is a row decoder, and a plurality of word lines W are provided by the row address signal ROW.
Any one of L is driven. A sense amplifier 5 has a function of amplifying the data on the bit lines BL1, BL2, BL3.

Further, 2a, 2b, 2c are sense amplifier rows 1a, 1b, each consisting of a plurality of sense amplifiers 5.
Reference numeral 1c denotes a sense amplifier driving means for driving the plurality of sense amplifier rows 2a to 2c, respectively. The sense amplifier driving means 1a to 1c are supplied with power from a common power source 7 and a common ground pin 8 through a wiring 9. Although supplied in either direction, in FIG. 1, the sense amplifier driving means 1c has the shortest distance from the power supply 7 and the ground pin 8 to each of the sense amplifier driving means 1a to 1c. The sense amplifier driving means 1a are arranged in this order, and the sense amplifier driving means 1a is farthest away. The sense amplifier driving means 1a farthest from the power source 7 or the like receives the driving signals φpa and φna with the smallest delay amount from the driving signal generating means 3, and the sense amplifier driving means 1b farthest away from the power source 7 or the like is Drive signals φpb and φn from the drive signal generating means 3 have the second smallest delay amount.
In response to b, the sense amplifier driving means 1c having the shortest distance from the power supply 7 receives the driving signals φpc and φnc having the largest delay amount from the driving signal generating means 3.

Next, the operation of the above configuration will be described. When the row address ROW is input and the word line WL is driven by the row decoder, the data of the selected memory cell appears on the bit lines BL1, BL2 and BL3, causing a minute potential difference. Further, the drive signals φp and φn are input to the drive signal generating means 3.
The input drive signals φp and φn are divided into three pairs of drive signals in the drive signal generating means 3 in the same number as the sense amplifier drive means 1a to 1c, and the respective drive signals are delayed by different delay amounts. 3 pairs of drive signals φpa, φ
na to φpc and φnc are generated. The drive signals φpa and φna with the smallest delay amount are input to the sense amplifier driving means 1a farthest from the power supply 7 and the like, and the drive signals φpb and φnb with the smallest delay amount are next sense amplifier driving means 1b. Drive signals φpc and φnc having the largest delay amount are input to the sense amplifier driving means 1c having the shortest distance from the power supply 7 or the like.

As a result, the drive signals φpa and φna are first generated.
Is input to the sense amplifier driving means 1a, the sense amplifier 2a is activated and the sense amplifier driving signal SAPa,
SANA is generated and drives the sense amplifier 2a. Next, the drive signals φpb and φna are delayed with respect to the drive signals φpa and φna.
φnb is input to the sense amplifier driving means 1b to generate sense amplifier driving signals SAPb and SANb, and drives the sense amplifier 2b. Then, drive signals φpc and φnc
Is input to the sense amplifier driving means 1c, the sense amplifier driving means 1c is activated, and the sense amplifier driving signal SAP
c and SANc are generated to drive the sense amplifier 2c.

As a result, first, the sense amplifier driving means 1a, which is distant from the power source 7 etc., operates independently of the other sense amplifier driving means 1b, 1c, so that the other sense amplifier driving means 1b, It is not affected by the voltage drop due to the operation of 1c. Therefore, the capability of the sense amplifier driving means 1a far from the power source 7 etc. can be enhanced to generate the sense amplifier driving signals SAPa and SANa, so that the driving end time of the sense amplifier 2a can be shortened and the bit can be reduced. The amplification time of the line BL1 can be shortened.

FIG. 3 shows the above situation. This figure is a timing diagram of a plurality of sense amplifier driving means 1a to 1c, and sense amplifier driving signals SAPa and SANa to SA generated by the respective sense amplifier driving means 1a to 1c.
Pc, SANc, and potentials of the bit lines BL1 to BL3 are shown with time, and the vertical axis shows voltage and the horizontal axis shows time. As can be seen from the figure, the bit line for the sense amplifier driving means 1a farthest from the power supply 7 or the like, that is, the bit line BL1 requiring the longest time to be amplified is the period from the time T1 to the time Ta for being amplified. However, this period is from the time T1 to the time T2 during the period.
Between the other two sense amplifier driving means 1b, 1
c does not operate, the sense amplifier driving means 1c does not operate from time T2 to time T3, and the voltage drop is small accordingly, and the supply current to the farthest sense amplifier driving means 1a increases. A period (Ta) shorter than the time Tb required for amplifying all bit lines as shown in FIG.
Since <Tb), the time required for amplifying all bit lines can be shortened as compared with the conventional example.

With the above configuration, the influence of the voltage drop caused by the difference in the wiring resistance Ri of the wiring 9 between the power supply 7 and the ground pin 8 and the plurality of sense amplifier driving means 1a to 1c is suppressed to a low level, and the power supply is reduced. Since it is possible to shorten the drive end time of the sense amplifier row 2a which is the most distant from the 7 and the ground pin 8 and which has been a cause of hindering the shortening of the access time, until all the bit lines BL1 to BL3 are amplified. The time required for the semiconductor memory device can be shortened, and the operation time of the semiconductor memory device can be shortened.

In the above description, the drive signal generating means 3 which gives different amounts of delay to the input drive signal has a separate circuit configuration, but the present invention is not limited to this, and other input is possible. The sense amplifier driving means 1a is modified by changing the length of each wiring for supplying the drive signals .phi.p and .phi.n to the respective sense amplifier driving means 1a to 1c, and adding a plurality of different delay amounts according to the difference in the wiring lengths. The operation timings of 1c may be controlled at different timings.

[0021]

As described above, according to the sense amplifier drive circuit of the present invention, by delaying the input timing of the drive signal input to the sense amplifier drive means having a short distance from the power supply and ground pins, the power supply and Since the effect of the voltage drop due to the wiring resistance on the sense amplifier drive circuit farthest from the ground pin was reduced and the supply current was increased to increase the capability of the sense amplifier drive circuit more than ever before, The drive end time of the farthest sense amplifier can be shortened, and the amplification time of the bit line which requires the longest time for amplification, which has been a cause of impediment to shortening the access time, can be shortened. It is possible to increase the speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a sense amplifier drive circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional sense amplifier drive circuit.

FIG. 3 is a signal timing diagram according to an embodiment of the present invention.

FIG. 4 is a timing chart of signals in a conventional example.

[Explanation of symbols]

 1a, 1b, 1c Sense amplifier driving means 2a, 2b, 2c Sense amplifier row 3 Drive signal generating means 4 Row decoder 5 Sense amplifier 6a, 6b, 6c Memory cell array 7 Power supply 8 Ground pin 9 Wiring BL1 to BL3 Bit line

Claims (2)

[Claims] 1. A sense amplifier driving circuit for driving a plurality of sense amplifier rows for amplifying a minute potential difference of a bit line, wherein the sense amplifier driving circuit is provided for each of the sense amplifier rows, and a power source is provided through a common power source and a common ground pin. Receiving supply,
A plurality of sense amplifier driving means for driving the corresponding sense amplifier row, and a drive signal generating means for generating a plurality of drive signals having different delay amounts with respect to the input drive signal are provided, and are generated by the drive signal generating means. A sense amplifier drive circuit, wherein each of the plurality of drive signals having different delay amounts is input to each of the sense amplifier drive means to drive a plurality of sense amplifier rows. 2. The drive signal generating means sets the delay amount of the drive signal to the sense amplifier driving means that is the farthest from the common power source and the common ground pin to a minimum amount,
2. The sense amplifier drive circuit according to claim 1, wherein the delay amount of the drive signal for the sense amplifier drive means closest to the common power source and the common ground pin is set to the maximum.