JPH0737903A - Field-effect transistor and formation therefor - Google Patents

Abstract

PURPOSE:To prevent positional deviations of a gate electrode and an interelement isolation layer to an ohmic electrode due to positional deviation, etc., of a mask alignment by forming the layer and the gate electrode in a self-alignment manner. CONSTITUTION:A structure 66 on the way of forming an ohmic electrode provided on a base 48 having an active layer on a surface is used as a mask, the base 48 is ion implanted to form an interelement isolation layer 68. Two ohmic electrodes 70 having a shape of a section perpendicular to a surface of the base 48 has an inverted tapered shape are formed from the structure 66 on the way of forming the ohmic electrodes along a gate length direction through a gate electrode forming region. Then, with the electrodes 70 as masks a gate electrode having a gate length of an interval between the electrodes 70 is formed on the base 48 of a region interposed to be held between the electrodes 70.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) and its forming method.

[0002]

Prior to the description of the present invention, in order to facilitate understanding of the present invention, first, a conventional method of forming a field effect transistor using an epitaxial technique will be described with reference to the drawings. (A) to (C) of FIG.
FIG. 10 is a process diagram for explaining a conventional FET formation method.
FIGS. 9A to 9C are process diagrams following FIG. 8C. 10A to 10C are process diagrams following FIG. 9C.

First, an n-type active layer (n layer) 12 and a high-concentration n-type active layer (n ⁺ layer) 14 are sequentially laminated on a GaAs substrate 10 using an epitaxial technique to form a semiconductor body 36. ((A) of FIG. 8).

Next, a resist pattern 16 for element isolation is formed on the semiconductor body 36 using conventional photolithography and etching techniques. Then, using the element isolation resist pattern 16 as a mask, ions are implanted into the semiconductor body 36 to form the element isolation layer 18 (FIG. 8B).

Next, a resist pattern 16 for element isolation is formed.
Is removed using an organic solvent, and then an insulating film 20 is formed on the entire surface of the n ⁺ active layer 12 by the CVD method ((C) of FIG. 8).

Next, the electrode resist pattern 2 having an opening in the ohmic electrode formation planned region on the insulating film 20.
Form 2. And this electrode resist pattern 2
Using 2 as an etching mask, the insulating film 20 exposed in the opening is removed ((A) of FIG. 9).

Next, a conductive film 24 is vacuum-deposited on the semiconductor body 36 and the resist pattern 22 exposed in the opening ((B) of FIG. 9).

Next, the conductive film 24 portion on the resist pattern 22 is removed by a lift-off method, and the semiconductor body 3 is removed.
The remaining conductive film on 6 is used as the ohmic electrode 24a. Next, on the ohmic electrode 24a and the insulating film 20, there is a gate opening 26 in a region where the gate electrode is to be formed between the ohmic electrodes 24a, and the side wall of the gate opening 26 has an inversely tapered cross section. A resist pattern 28 for gates is formed. Then, the gate insulating film opening 30 is formed in the insulating film by using the gate resist pattern 28 as an etching mask ((C) of FIG. 9).

Next, using the insulating film 20 having the gate insulating film opening 30 formed therein as an etching mask, the semiconductor body 36 exposed in the gate insulating film opening 30 is wet-etched to the n layer 12 of the semiconductor substrate. Recess etching reaching the depth is performed to form the recess etching portion 32 ((A) of FIG. 10).

Next, using the gate resist pattern 28 as a mask, a gate electrode 34 is formed in the recess etching portion by a vacuum deposition method. At this time, the gate electrode material metal 34a is also vacuum-deposited on the gate resist pattern 28 ((B) of FIG. 10).

Next, the gate resist pattern 28 and the gate electrode material metal 34a on the gate resist pattern 28 are removed to form an FET (FIG. 10C).

[0012]

However, in the conventional method for forming an FET, in forming the element isolation region and the gate electrode, a resist pattern is formed individually by using the photolithography technique, and this resist pattern is formed. By using as a mask, the positions of the element isolation layer and the gate electrode were determined. Therefore, due to mask misalignment and development unevenness (insufficient development) during resist pattern formation,
The reproducibility of the positions of the element isolation region and the gate electrode is different for each FET element formed on the wafer and for each wafer. As a result, there has been a problem that the characteristics of the FET elements are varied and the yield in FET formation is reduced.

Further, when the gate length becomes short, the gate resistance becomes large, so that there is a problem that the device characteristics such as high speed operability are deteriorated.

Further, when the ohmic electrode is reduced in order to reduce the size of the element, there is a problem that the ohmic resistance increases and the element characteristics deteriorate.

Therefore, a first object of the present invention is to provide a method for forming a field effect transistor capable of performing alignment of an ohmic electrode with an element isolation layer and a gate electrode in a self-aligned manner.

A second object of the present invention is to provide a method for forming a field effect transistor having a short gate length and a small gate resistance.

A third object of the present invention is to provide a field effect transistor having a reduced ohmic resistance.

[0018]

In order to achieve the above-mentioned first object, according to the method for forming a field effect transistor of the first invention, (a) an underlayer having an active layer on its surface is formed. Using the provided structure during formation of the ohmic electrode as a mask, a step of performing ion implantation into the base to form an element isolation layer, and (b) the structure during formation of the ohmic electrode to the gate. Two ohmic electrodes having a reverse taper shape in a cross section (hereinafter, also simply referred to as a cross section) along a direction that is a long direction and perpendicular to the surface of the base are formed with a gate electrode formation planned region interposed therebetween. And (c) using the two ohmic electrodes as a mask, form a gate electrode having a gate length that is the distance between the ohmic electrodes on the ground below the region sandwiched between the ohmic electrodes. Characterized in that it comprises a step of.

In order to achieve the first purpose, the second
According to the method for forming a field effect transistor of the field effect transistor of the invention of (1), the cross section along the direction that becomes the gate length direction is an inverse taper shape on the underlayer having the active layer on the main surface. Forming two ohmic electrodes with a gate electrode formation-scheduled region in between, and (b)
A step of implanting ions into the semiconductor substrate to form an element isolation layer using the two ohmic electrodes as a mask; and (c) sandwiching the ohmic electrodes with each other using the two ohmic electrodes as a mask. And a step of forming a gate electrode having a gate length which is the interval between the ohmic electrodes on the semiconductor substrate in the different region.

Further, in implementing the field effect transistor of the first invention, in order to achieve the above-mentioned second object, preferably, before the step (a), it is preferably formed on a substrate.
In the step of forming an insulating film and the step (c), the insulating film provided on the semiconductor in the region between the ohmic electrodes is etched using the ohmic electrode as an etching mask to open the gate opening. A step of forming, a step of performing an etchback process on the ohmic electrode to form a residual ohmic electrode, and a step of forming the residual ohmic electrode, and then forming a gate on the gate opening and an insulating film around the gate opening. And a step of forming an electrode.

In implementing the field effect transistor of the second invention, further, in order to achieve the above-mentioned second object, preferably, before the step (a), an insulating film is formed on the semiconductor substrate. The step of forming and the step (c) include a step of forming a gate opening by performing an etching process on the insulating film portion in the region between the ohmic electrodes by using the ohmic electrode as an etching mask. And a step of forming a residual ohmic electrode by etching back, and a step of forming a gate electrode on the gate opening and the insulating film around the gate opening after forming the residual ohmic electrode. Is desirable.

However, the remaining ohmic electrode functions as an ohmic electrode in the formed FET.

In implementing the field effect transistor of the first invention, preferably, in the step (a), an active layer is formed on the main surface of the semiconductor substrate and the active layer is formed on the semiconductor substrate and the active layer. To form an underlayer, an insulating film is formed on the underlayer surface, an ohmic resist pattern having an opening in the ohmic electrode formation region is formed on the insulating film, and the ohmic resist pattern is etched. Using the mask as a mask, etching the insulating film exposed in the opening to form an insulating film pattern,
Forming a current film for plating on the underlying layer exposed in the opening and the ohmic resist pattern; and having a resist opening in the ohmic electrode formation planned region on the current film for plating and in the gate length direction. Forming a resist pattern for plating having a forward tapered shape in a cross section that is perpendicular to the semiconductor substrate surface and the resist opening and the resist pattern sandwiched between the resist openings. On the part,
The step of forming the plating layer, the step of removing the resist pattern portion exposed around the plating layer, and the etching back of the plating layer until the resist pattern portion for plating sandwiched between the resist openings is exposed. To form the residual plating layer and remove the current film portion for plating exposed around the residual plating layer, and the ohmic resist pattern and the resist openings exposed around the residual plating layer. The step of removing the sandwiched resist pattern portion for plating and molding a structure consisting of the remaining plating layer and the current film portion for plating during formation of the ohmic electrode, and using the structure during formation of the ohmic electrode as a mask, Ion-implanting to form an element isolation layer, (b)
The step of includes a step of forming an inter-element isolation layer, then removing the ohmic resist to form two ohmic electrodes separated from each other, and exposing the gate insulating film,
In the step (c), the ohmic electrode is used as a mask to etch the gate insulating film to form a gate opening, and a protective film resist having an opening at least on the gate opening is formed. A step of forming on the ohmic electrode and the element isolation layer, a step of etching the active layer exposed in the gate opening using the insulating film as an etching mask to form a recess etching portion, and an ohmic contact It is desirable to include a step of forming a gate electrode in the recess etching part by using the electrode, the protective film resist and the insulating film as a mask.

In carrying out the first or second invention, it is preferable to form an underlayer having an active layer on a semiconductor substrate by sequentially epitaxially growing the first and second active layers.

In carrying out the first or second invention, preferably, a step of performing ion implantation of a base having an active layer into a semiconductor substrate to form a first active layer, and a first active layer. On the layer, a step of forming an ohmic resist pattern having an opening in the ohmic electrode formation planned region, and ion implantation is performed on the first active layer exposed in the opening using the ohmic resist pattern as a mask , A second active layer is formed, and an active layer including the first and second active layers is formed.

Further, according to the structure of the field effect transistor of the present invention, in order to achieve the above-mentioned third object,
In a field effect transistor in which an ohmic electrode is provided on the lower ground with a gate electrode sandwiched between the ohmic electrodes, the cross-section of the ohmic electrode perpendicular to the surface of the base has a reverse taper shape. And

However, here, the inverse taper shape means that the edge on the gate electrode side of the upper surface of the ohmic electrode is on the gate electrode side with respect to the position of the edge on the gate electrode side of the junction surface between the ohmic electrode and the semiconductor substrate. It refers to the overhanging shape. Therefore, the cross section of the side wall of the ohmic electrode may be bent.

[0028]

According to the method for forming a field effect transistor of the present invention, an ohmic electrode having a cross-sectional shape in the direction of the gate length direction is an inverse taper shape, or the ohmic electrode and the ohmic electrode during the formation of the ohmic electrode. Using the structure as a mask, the element isolation layer and the gate electrode are formed in a self-aligned manner.

Therefore, the gate electrode and the element isolation layer are separated from the position of the ohmic electrode due to the displacement of the mask when the FET is formed and the uneven development of the photoresist pattern (especially insufficient development). Positional deviation can be prevented. As a result, the FET can be formed with good reproducibility. In addition, since the element isolation layer and the gate electrode are formed in a self-aligned manner, it is not necessary to perform strict mask alignment, so that process processing time can be shortened.

Further, by providing a bulging part which is continuous with the lower part of the gate electrode on the upper part of the gate electrode so that the cross-sectional shape of the gate electrode is a so-called mushroom shape (also called T-shape), the gate electrode is shortened. In addition, the gate resistance can be reduced.

If the cross-sectional shape of the ohmic electrode is an inverse taper type, the ohmic resistance can be reduced.

[0032]

Embodiments of the method of forming an FET according to the present invention will be described below with reference to the drawings. It should be noted that the drawings referred to below only schematically show the sizes, shapes, and positional relationships of the constituent components of the respective drawings to the extent that the present invention can be understood. In addition, in each drawing, hatching and the like showing the cross section are partially omitted. Therefore, the present invention is not limited to the illustrated examples.

First Embodiment Hereinafter, the structure of the FET of the present invention and the method for manufacturing the FET will be described together as a first embodiment. 1 (A)-
(C) is a process drawing for explaining the first embodiment. 2A to 2C are process diagrams following FIG. 1C. FIGS. 3A to 3C are process drawings following FIG. 2C. 4A to 4C are process diagrams following FIG. 3C. Each drawing shows a cross section along a direction that is the gate length direction of the FET.

In the first embodiment, first, an n layer 42 as a first active layer and an n ⁺ layer 4 as a second active layer 4 are formed on the main surface of a semi-insulating GaAs substrate 40 as a semiconductor substrate.
4 are sequentially epitaxially grown. Hereinafter, the semiconductor substrate 40, the n layer 42, and the n ⁺ layer 44 are collectively referred to as a base 48, and the n layer 42 and the n ⁺ layer 44 are collectively referred to as the active layer 4.
6. Next, the insulating film 50 is formed on the surface of the base 48 by the CVD method ((A) of FIG. 1).

Next, a cross section having an ohmic opening 52 in the ohmic electrode forming region on the insulating film 50, and along the direction of the gate length direction and perpendicular to the underlying surface (hereinafter, simply referred to as a cross section). An ohmic resist pattern 54 having a forward tapered shape is formed.
The formation of the ohmic resist pattern 54 does not require pattern alignment.

Next, the ohmic resist pattern 54 is formed.
Is used as an etching mask to form the ohmic opening 5
The insulating film 50 exposed at 2 is dry-etched (see FIG. 1).
(B)).

Next, a current film for plating (hereinafter, referred to as a film for plating) is formed on the base 48 and the ohmic resist pattern 54 exposed in the ohmic opening 52 by using a vacuum deposition method.
A plating CF) 56 is formed (FIG. 1C).

Next, on the CF 56 for plating, the resist opening 58 is provided on the ohmic opening 52, and the cross-sectional shape along the direction of the gate length direction and perpendicular to the surface of the base 48 is in order. A plating resist pattern 60 having a tapered shape is formed. Here, the resist opening 5
The portion of the plating resist pattern 60 sandwiched between 8 is particularly referred to as a gate resist pattern 60a ((A) of FIG. 2).

Next, on the resist opening 58 and the gate resist pattern 60a, using a normal plating technique,
The plated layer 62 is formed. This plating layer 62 has a thickness larger than that of the plating resist pattern 60,
The resist opening 58 is formed in a buried state. Also,
The plating layers 62 in which the two resist openings 58 are embedded are connected to each other by the overplating portion 62a on the gate resist pattern 60a ((B) of FIG. 2).

Next, using the usual photolithography technique, the entire surface is exposed and developed to remove the plating resist pattern 60 exposed around the plating layer 62 (FIG. 2C).

Next, the plating layer 62 is etched back until the gate resist pattern 60a is exposed to form the remaining plating layer 64 separated from each other. Hereinafter, the residual plating layer 64 and the plating CF 56 are collectively referred to as a structure 66 in the process of forming an ohmic electrode ((A) of FIG. 3).

Next, using the usual photolithography technique, the entire surface is exposed and developed to remove the ohmic resist pattern 54 and the gate resist pattern 60a exposed around the residual plating layer 64.

Next, the structure 6 during formation of the ohmic electrode
Using 6 as a mask, ion implantation is performed on the base 48 around the structure 66 to form an element isolation layer 68. At this time, the CF for plating the gate electrode formation region
The remaining portion of the ohmic resist pattern 54 under 56 serves as a gate ion blocking resist that prevents ions from being implanted into the base 48 in the gate electrode formation region (FIG. 3B).

Next, after the inter-element isolation layer 68 is formed, the portion of the CF 56 for plating exposed between the remaining plating layers 64 and the remaining portion of the ohmic resist pattern 54 thereunder are removed and left. Two ohmic electrodes 70 having a reverse tapered cross-section, which are separated from each other, are formed of the CF 56 for plating and the remaining plating layer 64 ((C) of FIG. 3).

Next, a protective film resist 76 having an opening 74 in a region including at least the upper surface of the ohmic electrode 70 (hereinafter, referred to as a gate opening) 72 is formed on the ohmic contact using an ordinary photolithography technique. It is formed on the electrode 70 and the element separation layer 68. The cross section of the side wall of the opening 74 of the protective film resist 76 has an inverse taper shape. Then, using the protective film resist 76 and the ohmic electrode 70 as a mask, the insulating film 50 exposed between the ohmic electrodes 70 is dry-etched to form an insulating film gate opening 78. The width of the insulating film gate opening 78 in the direction of the gate length is equal to the distance between the ohmic electrodes 70 (FIG. 4).
(A)).

Next, using the protective film resist 76 and the ohmic electrode 70 as a mask, the active layer 46 exposed in the insulating film gate opening 78 is wet-etched to form a recess etching portion 80. . The recess etching portion 80 reaches the n layer 42 ((B) of FIG. 4).

Next, using the protective film resist 76 and the ohmic electrode 70 as a mask, the gate metal 82a is vapor-deposited by the vacuum vapor deposition method to form the gate electrode 82 in the recess etching portion 80 in a self-aligned manner. Therefore, the gate length becomes equal to the interval between the ohmic electrodes 70 and the width of the insulating film gate opening 78. FIG. 4C shows a state in which the protective film resist 76 has been removed.

In this way, the element isolation layer 68 and the ohmic electrode 82 are arranged with respect to the position of the ohmic electrode 70.
Can be manufactured in a self-aligned manner. The ohmic electrode 82 of the FET manufactured in the first embodiment has a reverse taper shape in a cross section along the gate length direction and perpendicular to the underlying surface. Therefore,
The ohmic resistance of the ohmic electrode 82 is smaller than the resistance value of the conventional ohmic electrode. As a result, the operating characteristics of the FET such as high-speed operability can be improved.

Second Embodiment Hereinafter, a second embodiment of the method for manufacturing the FET of the present invention will be described. In the second embodiment, a gate electrode having a bulge is formed in a self-aligned manner. FIG. 5A-
FIG. 7C is a process drawing for explaining the second embodiment. FIGS. 6A to 6C are process diagrams following FIG. 5C. Each drawing shows a cross section along a direction that is the gate length direction.

In the second embodiment, as shown in FIG. 3C of the first embodiment, the steps until the ohmic electrode 70 is formed are the same as the steps of the first embodiment described above.

After forming the ohmic electrode 70, in the second embodiment, the insulating film 50 provided on the semiconductor in the region between the ohmic electrodes 70 is etched using the ohmic electrode 70 as an etching mask. An insulating film gate opening 78 is formed. Specifically, after removing the protective film resist 76 formed in the same process as the first embodiment using an organic solvent, the etch back resist 84 is removed.
Is applied to the entire surface of the base 48 including the ohmic electrode 70. The thickness of the etch-back resist 84 is made thicker than that of the ohmic electrode 70 ((A) of FIG. 5).

Next, the etch-back resist 84 is etched into a thin film, and the residual etch-back resist 84 is formed.
a is formed. This residual etch back resist 84a
Is thinner than the thickness of the ohmic electrode 70 ((B) of FIG. 5).

Next, by dry etching, the ohmic electrode 70 is subjected to an etch back process to thin the ohmic electrode 70 to the thickness of the residual etch back resist 84a to form the residual ohmic electrode 70a. By thinning the inversely tapered ohmic electrode 70, the gap (gate opening) between the remaining ohmic electrodes 70a becomes wider than the insulating film gate opening 78 (FIG. 5C). Next, the residual etch back resist 84a is removed using an organic solvent. Next, a gate resist 86 is formed on the remaining ohmic electrode 70a and the element isolation layer 68. The gate resist 86 covers the upper surface and the side wall of the remaining ohmic electrode 70a. Further, the gate resist 86 has an insulating film gate opening 78 and a gate resist opening 88 on the insulating film 50 around the insulating film gate opening 78. When forming the gate resist 86, it is sufficient that the gate resist 86 is not formed on the insulating film gate opening portion 78, and therefore the mask alignment does not require precision.

Next, the gate resist 86 and the insulating film 50.
Is used as a mask to perform wet etching on the active layer 46 exposed in the insulating film gate opening 78 to form a recess etching portion 80. The recess etching portion 80 reaches the n layer 42 ((A) of FIG. 6).

Next, using the gate resist 86 as a mask, a gate metal 90 is laminated by a vacuum vapor deposition method to form a gate on the insulating film gate opening 78 and the insulating film 50 around the insulating film gate opening 78. An electrode is formed ((B) of FIG. 6).

Next, the gate resist 86 and the gate metal 90 laminated thereon are removed by the lift-off method. In this way, a so-called mushroom-shaped (T-shaped) gate electrode 92 having a bulge portion can be formed in the gate resist opening 88. The width in the gate length direction of the bulging portion above the gate electrode 92 is
It corresponds to the width of the gate resist opening 88. Also,
The gate length (width of the Schottky junction portion) below the gate electrode 92 corresponds to the width of the insulating film gate opening 78. The width of the insulating film gate opening 78 corresponds to the initial distance between the ohmic electrodes 70. Therefore, also in the second embodiment, the position and the gate length of the gate electrode 92 can be formed in a self-aligned manner by using the ohmic electrode 70 ((C) of FIG. 6).

Further, for example, the gate electrode 92 can be formed by using the remaining ohmic electrode 70a as a mask without using the gate resist 86. In this case, in order to separate the residual ohmic electrode 70a and the gate electrode 92 from each other, the height of the uppermost portion of the gate electrode 92a needs to be lower than that of the residual ohmic electrode 70a.

The residual ohmic electrode 70a formed in the second embodiment functions as an ohmic electrode in the FET.

Modified Example Next, a modified example of forming the active layer by ion implantation will be described. 7A to 7C are process diagrams for explaining this modification, showing a cross section taken along the direction that is the gate length direction of the FET.

In forming a base having an active layer,
In this modification, first, the semiconductor substrate 40 is ion-implanted to form a first active layer (n layer) 94 (FIG. 7).
(A)).

Next, on the first active layer 94, an ohmic resist pattern 98 having an ohmic opening 96 in the ohmic electrode formation planned region is formed.

Next, ohmic resist pattern 98
Using as a mask, ions are implanted into the first active layer 94 exposed in the ohmic opening 96 to form the second active layer (n ⁺ layer) 100, and the first and second active layers 94 are formed.
And 100 are formed (FIG. 7B).

Thereafter, through the same steps as those in the first embodiment described above, the element isolation layer 68 and the gate electrode 9 are self-aligned.
2 is formed to manufacture the FET. However, in the modified example, since the second active layer 100 is formed only under the ohmic electrode 70, it is not necessary to provide the recess etching portion as shown in FIG. 7C. Therefore, it is not necessary to provide an insulating film on the base.

In each of the above-described embodiments, the present invention has been described with reference to an example in which a specific material is used and under special conditions, but the present invention is subject to many changes and many modifications. You can For example, in each of the above-described embodiments, the element isolation layer is formed by using the structure in the process of forming the ohmic electrode as a mask, but in the present invention, for example, the gate opening is covered with a resist pattern and the ohmic electrode is used as a mask. The element isolation layer may be formed in a consistent manner.

As the material of the ohmic electrode, for example, Zn, Al, Ni or a combination of these materials may be used. Further, as the material of the semiconductor substrate,
Si, InP, Ge or (AlGaAs / GaAs)
A heterojunction substrate may be used.

[0066]

According to the method of forming a field effect transistor of the present invention, an ohmic electrode having an inversely tapered cross-section in the direction of the gate length direction, or this ohmic electrode and this ohmic electrode formation. By using the intermediate structure as a mask, the element isolation layer and the gate electrode can be formed in a self-aligned manner.

Therefore, the gate electrode and the element isolation layer are separated from the position of the ohmic electrode due to the displacement of the mask when the FET is formed and the uneven development of the photoresist pattern (especially insufficient development). Positional deviation can be prevented. As a result, the FET can be formed with good reproducibility. In addition, since the element isolation layer and the gate electrode are formed in a self-aligned manner, it is not necessary to perform strict mask alignment, so that process processing time can be shortened.

Further, if the cross section of the gate electrode has a so-called mushroom shape (also referred to as a T-shape) by providing a bulging portion which is continuous with the lower portion of the gate electrode, the gate electrode is shortened. In addition, the gate resistance can be reduced. As a result, an FET having excellent device characteristics such as high-speed operability and amplification factor can be obtained.

If the cross-sectional shape of the ohmic electrode is an inverse taper type, the ohmic resistance can be reduced. As a result, an FET having excellent device characteristics can be obtained.

[Brief description of drawings]

FIG. 1A to FIG. 1C are process drawings for explaining the first embodiment.

2A to 2C are process drawings following FIG. 1C.

3A to 3C are process diagrams following FIG. 2C.

4A to 4C are process diagrams following FIG. 3C.

5A to 5C are process diagrams for explaining the second embodiment.

6A to 6C are process diagrams following FIG. 5C.

FIG. 7A to FIG. 7C are process drawings for explaining a modified example.

8A to 8C are process drawings for explaining a conventional FET formation method.

9A to 9C are process diagrams following FIG. 8C.

10A to 10C are process diagrams following FIG. 9C.

[Explanation of symbols]

10: semiconductor substrate 12: n-type active layer (n layer) 14: high-concentration n-type active layer (n ⁺ layer) 16: element isolation resist pattern 18: element isolation layer 20: insulating film 22: electrode Resist pattern 24: Conductive film 24a: Ohmic electrode 26: Gate opening 28: Gate resist pattern 30: Gate insulating film opening 32: Recess etching part 34: Gate electrode 34a: Gate electrode material metal 36: Semiconductor body 40: Semiconductor Substrate (semi-insulating GaAs substrate) 42: First active layer (n layer) 44: Second active layer (n ⁺ layer) 46: Active layer 48: Underlayer 50: Insulating film 52: Ohmic opening 54: Ohmic resist Pattern 56: Current film for plating (CF for plating) 58: Resist opening 60: Resist pattern for plating 60a: Register for gate Stroke pattern 62: Plating layer 62a: Overplating portion 64: Residual plating layer 66: Structure during formation of ohmic electrode 68: Element isolation layer 70: Ohmic electrode 70a: Residual ohmic electrode 72: Gate opening 74: Opening 76 : Protective film resist 78: insulating film gate opening 80: recess etching part 82: gate electrode 82a: gate metal 84: etch back resist 84a: residual etch back resist 86: gate resist 88: gate resist opening 90: Gate metal 92: Gate electrode 94: First active layer (n layer) 96: Ohmic opening 98: Ohmic resist pattern 100: Second active layer (n ⁺ layer) 102: Active layer

Claims (8)

[Claims] 1. In forming a field effect transistor, (a) ion implantation is performed on the base using a structure in the process of forming an ohmic electrode provided on the base having an active layer on the surface as a mask. And (b) forming a reverse isolation taper in a cross section along the direction of the gate length direction and perpendicular to the surface of the base from the structure in the process of forming the ohmic electrode. A step of forming two ohmic electrodes each having a shape with a gate electrode formation-scheduled region interposed therebetween, and (c) using the two ohmic electrodes as a mask,
And a step of forming a gate electrode having a gate length which is the distance between the ohmic electrodes on the ground below the region sandwiched between the ohmic electrodes. 2. In forming a field effect transistor, (a) two ohmic electrodes each having a reverse taper shape in cross section along the direction of the gate length are formed on a base having an active layer on the main surface. And (b) using the two ohmic electrodes as a mask,
Ion-implanting the semiconductor substrate to form an element isolation layer, and (c) using the two ohmic electrodes as a mask,
And a step of forming a gate electrode having a gate length which is a distance between the ohmic electrodes on a semiconductor substrate in a region sandwiched between the ohmic electrodes. 3. The method for forming a field effect transistor according to claim 1, wherein, before the step (a), a step of forming an insulating film on the base, and the step (c) include the ohmic contact. Using the electrode as an etching mask,
Etching the insulating film provided on the semiconductor in the region between the ohmic electrodes to form a gate opening; and etching back the ohmic electrodes to remove residual ohmic electrodes. A method of forming a field effect transistor, comprising: forming a residual ohmic electrode; and forming a gate electrode on the gate opening and an insulating film around the gate opening after forming the remaining ohmic electrode. 4. The method for forming a field effect transistor according to claim 2, wherein, before the step (a), a step of forming a transfer film on the semiconductor substrate and the step (c) are performed. Using the ohmic electrode as an etching mask,
A step of etching the insulating film portion in the inter-ohmic electrode region to form a gate opening; a step of etching back the ohmic electrode to form a residual ohmic electrode; A step of forming a gate electrode on the gate opening and an insulating film around the gate opening after forming the electrode. 5. The method for forming a field effect transistor according to claim 1, wherein in the step (a), an active layer is formed on a main surface of the semiconductor substrate, and the semiconductor substrate and the active layer are provided. To form an underlayer, a step of forming an insulating film on the surface of the underlayer, a step of forming an ohmic resist pattern having an opening in an ohmic electrode formation region on the insulating film, and the ohmic resist Using the pattern as an etching mask, etching the insulating film exposed in the opening to form an insulating film pattern, and plating on the base and the ohmic resist pattern exposed in the opening Forming a current film, and forming a resist opening in the ohmic electrode formation planned region on the plating current film. And a step of forming a plating resist pattern having a forward tapered shape in a cross section perpendicular to the gate length direction and perpendicular to the surface of the semiconductor substrate, the resist opening, and the resist Forming a plating layer on the resist pattern portion sandwiched between the openings; removing the resist pattern portion exposed around the plating layer; and forming the plating layer on the resist opening. A step of etching back to form a residual plating layer until the plating resist pattern portion sandwiched between the parts is exposed, and removing the plating current film portion exposed around the residual plating layer; The ohmic resist pattern exposed around the residual plating layer and the resist pattern sandwiched between the resist openings. A step of removing the resist pattern portion for forming a structure in the process of forming an ohmic electrode consisting of the remaining plating layer and the current film part for plating; and using the structure in the process of forming the ohmic electrode as a mask, A step of implanting ions to form an inter-element isolation layer, wherein the step (b) includes removing the ohmic resist after forming the inter-element isolation layer, and separating the two elements from each other. Forming the ohmic electrode and exposing the gate insulating film, the step (c) uses the ohmic electrode as a mask to etch the gate insulating film to form a gate opening. Forming a protective film resist having an opening at least on the gate opening, the ohmic electrode and the element isolation layer. Above, the step of forming, the active layer exposed in the gate opening is etched using the insulating film as an etching mask,
A field effect transistor comprising: a step of forming a recess etching portion; and a step of forming a gate electrode in the recess etching portion using the ohmic electrode, the protective film resist and the insulating film as a mask. Forming method. 6. The method for forming a field effect transistor according to claim 1, wherein the first and second active layers are sequentially epitaxially grown on a semiconductor substrate when forming the base having the active layer. A method of forming a field effect transistor, which is characterized in that 7. The method of forming a field effect transistor according to claim 1, wherein in forming the base having the active layer, a semiconductor substrate is ion-implanted to form a first active layer. And a step of forming an ohmic resist pattern having an opening in an ohmic electrode formation-scheduled region on the first active layer, and using the ohmic resist pattern as a mask to expose the opening. Ion implantation is performed on the first active layer to form a second active layer, and an active layer composed of the first and second active layers is formed. Method. 8. A field effect transistor in which an ohmic electrode is provided on the lower ground with a gate electrode sandwiched between the ohmic electrode and a cross section of the ohmic electrode which is perpendicular to the surface of the base and has a reverse taper shape. A field effect transistor characterized by: