JPH0730373A - Digital filter - Google Patents

Abstract

PURPOSE:To enable accurate control follow-up operation by compensating digit absence of the digital filter. CONSTITUTION:A figure shows a low-pass filter(LPF) as a primary delay digital filter. For primary delay, a current input value is added to the quantity obtained by properly multiplying the difference between a last output value and the current input value by a constant to obtain a current output. Here, digit absence is caused at the time of the constant multiplication, so a decimal part generated each time a multiplying means 2 performs arithmetic is integrated and accumulated by an integrating means 3 and when the integration result is >=+ or -1, an overflow detecting means 4 sends an output signal of + or -1 to an adding means 5. The adding means 5 adds output correction of + or -1 in addition to normal arithmetic for a digitized integer part, thereby compensating the digit absence due to digitization. This compensation is performed each time deviation exceeds 1 and the correction is performed at each time, so control reaches a command at all times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used for automatic computer control or the like, and more particularly to a digital nth-order filter having a delay characteristic of one order or more.

[0002]

2. Description of the Related Art Conventionally, a block diagram shown in FIG. 7A has been provided as a digital filter. This has a difference relationship as shown by, for example, Equation 1.

## EQU1 ## y _n = y _n-1 + Kx _n That is, in this filter, the fraction part is digitized by the digit of Kx _n , and the result remains in y _n-1 .
Affects the next operation. In other words, there is a problem that the error is integrated due to the influence of past digit cancellation.

Further, in the configuration as shown in FIG.
2-166913 gazette), this is a means for preventing digit loss for low-pass compensation (high-pass) filters,

## EQU2 ## a _n = a _n-1 + x _n

[Mathematical formula-see original document] y _n = K · a _n is expressed by the equations 2 and 3, but even in this case, digit cancellation is caused by the term of the equation 3. However, this case has the advantage that it is not affected by the past.

However, a first-order lag low-pass filter is applied in the above case. First, a low-pass filter with a first-order lag is expressed by an equation 4

## EQU4 ## Y (s) = 1 / (1 + TS) .X (S)

## EQU5 ## y = (1-K) / (1-KZ- ¹ ) .x is obtained. Where K is

## EQU6 ## K = exp (-Δt / T) (where Δt is a sampling period). Therefore, FIG.
It becomes a block diagram like (c). Equation 5 is

[Equation 7] y _n = K · y _n-1 + ( ₁ −K) · x _n = x _n + K (y _n-1 −x _n ) and even if the equivalent conversion is performed, Since the shape of 7 (b) is not obtained, it can be seen that it cannot be applied to the low-pass filter. That is, this proposal cannot be used for first-order lag filtering.

Further, in the proposal of Japanese Patent Laid-Open No. 4-316208,
This is a proposal for compensating for the digit cancellation error of the digital first-order lag filter. However, if the filter constant is a small value, for example, 0.1, the control can handle small changes, but the unit 1 of the output error is forcibly switched. The controlled object undergoes a stepwise change with a maximum change of 10 digits (shown as a schematic diagram in FIG. 8 h), and a large fluctuation is given to the controlled object, resulting in a fluctuation as shown in i of FIG. Is given to the controlled object.

[0006]

As described above, the proposed method cannot be completely applied to a general filter, and particularly in a first-order lag digital filter, the error is maintained while maintaining controllability. The problem is that no means could be expected to resolve this problem. Therefore, it is an object of the present invention to provide a correction for eliminating an error due to a digit loss in a general digital filter that causes a digit loss without deteriorating the calculation load and the memory efficiency and the controllability. .

[0007]

The structure of the present invention for solving the above problems is, in a digital filter having a multiplication element, a multiplication means for multiplying a filter constant of the multiplication element and a multiplication result of the multiplication means. Of these, the value of the lower byte corresponding to the fractional part is integrated for each multiplication, and the overflow of the value is detected by detecting the value overflow of ± 1 or more in the calculation result of the integrating means. Overflow detection means for outputting ± 1 only at the time of outputting and 0 at other times, and addition means for adding the output of the overflow detection means to the value of the upper byte corresponding to the integer part of the multiplication result. To have.

[0008]

When the digit is dropped and the quantity below the decimal point, which was conventionally ignored, is added up for each sample, and the quantity exceeds ± 1, the cumulative error exceeds the control minimum unit quantity. Correct the amount by ± 1. That is, since the numerical value below the decimal point due to digitization is cut off by the multiplication element, the calculation is not ignored and the values are stored and integrated, and the error accumulation is corrected so as not to exceed 1.

[0009]

INDUSTRIAL APPLICABILITY The present invention is a correction that can be applied to any digital filter that includes a multiplication element and causes cancellation, and in particular can take a value that always follows a steady control instruction value. No digitizing error left. This calculation can be easily realized without requiring complicated changes and memory. Further, the correction does not cause a control abnormality.

[0010]

EXAMPLES The present invention will be described below based on specific examples. FIG. 1 shows a block diagram when the present invention is applied to a first-order lag digital filter. This filter is a low-pass filter and is used, for example, for automatic control of the throttle of an automobile as shown in FIG. An example of a flowchart of this low-pass filter is shown in FIG. 4 (described later). The first-order lag is shown in a block diagram as shown in FIG. 7 (c), and is expressed by a recurrence formula such as Formula 7. The meaning of this formula is that the current input value is added to the amount obtained by appropriately multiplying the difference between the previous output value and the current input value by a constant, and the current output is obtained.

Here, as a characteristic of the digital filter, a digit loss occurs at a constant multiple. This results from ignoring the fractional part, although the integer part and the fractional part are obtained in the result of the multiplication operation by the microcomputer. Therefore, in the present invention, as shown in FIG. 1, the integral part 3 accumulates and accumulates the fractional part generated each time it is calculated by the multiplying part 2, and the absolute value of the integrated result is 1.
When it exceeds, the overflow detection means 4 sends an output signal of ± 1 to the addition means 5. The adding means 5 compensates for digit cancellation due to digitization by adding the output correction of ± 1 in addition to the usual calculation of the digitized integer part. This correction occurs every time the deviation exceeds 1, and is corrected each time, so that the control can always reach the target value.

The occurrence of this overflow differs depending on the gain value setting, that is, the system. This is explained as follows. That is, +1 digit is 1
The filter constant (gain) is 0.
If it is 1, 0.1 × 1 = 0.1 is integrated, so that overflow occurs after sampling 10 times. If the filter constant is 0.25, overflow will occur in sampling 4 times for +1 digit. In this way, the finer the gain, the more the number of times of sampling increases, and the control target is followed just like an asymptote.

A case where the first-order lag digital filter is applied to ISC (idle speed control) in the vehicle throttle shown in FIG. 3 will be described. Figure 3
A throttle actuator 24 is provided in the throttle 23 in the engine 22 of the vehicle 21, and the throttle valve 23 is controlled by a signal from an ECU (electronic control circuit) 26 to keep the engine rotation at a predetermined value. The accelerator position sensor 25 is used for the accelerator that instructs the engine rotation.
Is provided, and the signal corresponding to the operator's accelerator position is E
It is connected to the input I / F 28 of the CU 26 and the engine speed is input as an electric signal. ROM in the ECU 26
According to the program stored in 29, the CPU 30
The drive circuit 2 calculates the opening of the throttle valve to be controlled based on a signal from a throttle sensor (not shown).
7 sends a drive signal to the actuator 24 for control.

At the time of this calculation, the output is an analog value of the angle of the throttle valve, but the calculation is performed digitally by the microcomputer, so digit digit cancellation is unavoidable. Further, as a characteristic of the throttle control, a relatively large change in engine speed is caused by a slight control amount, so that the engine rotation becomes unstable in a control that overshoots an instruction amount. For this reason, more accurate controllability is required, and a first-order lag filter is used here to allow a certain degree of gentle follow-up to a sudden change to realize smooth start-up and acceleration of the vehicle. At this time, if the cancellation of digits is accumulated in this first-order lag digital filter, accurate control cannot be expected, so the present invention is applied.

A flow chart of the basic operation of this ISC is shown in FIG. In step 202,
First, the position of the accelerator is detected, and an engine rotation instruction determined by the operator is fetched in the form of an electric signal Ap. In step 204, the target throttle opening T _TA is determined by a map in ROM in the ECU or by a mathematical expression, and in step 2
At 06, the target controlled variable X is set. And step 208
Set an appropriate filter constant with and set LP in step 210.
Calculate with F (low pass filter) routine, step 2
At 12, the actual control amount is output.

The LPF routine is shown by way of example in the flow chart of FIG. First, in step 102, the input value X
(For the application example of FIG. 3, dX is calculated based on the target throttle opening T _TA , u _{n in} the block diagram of FIG. 1), that is, (y _n-1 −x _n ) in the latter half of the equation (7). Ask for. Then, in step 104, the filter constant KLPF is multiplied, and in step 10
In step 6, the upper 2 bytes of the integer part and the lower 2 bytes of the decimal part are treated separately, and the integral of the decimal part is calculated in step 108. It is checked in step 1 whether this value IdY overflows.
Judge at 10. Overflow, that is, the error is the controlled variable 1
When it exceeds the unit, 1 is added and corrected to the control amount in step 114 (if -1, -1 is added, that is, 1 is subtracted). In the example of this flow chart, when the IdY register exceeds 1, the value obtained by subtracting 1 from the exceeded value is automatically set as the remaining register. Therefore, the step of resetting the IdY register is not shown. Then, the output value is set in the buffer and stored as the previous value, and the LP
The calculation of F ends. In the application example of FIG. 3, step 120 for multiplying the gain correction KG of the LPF output is provided.

Although the present embodiment is applied to a first-order lag digital filter, it can be applied to a portion of a general digital filter which causes cancellation. Further, as shown in FIG. 2, even when n first-order lag LPFs are connected in series and each digit cancellation is compensated, the digit cancellation error does not accumulate as a whole. In this case, in the flowchart of FIG. 4, steps 102 to 116 are a single-stage LPF, and the process up to 118 is repeated n times to form an nth-order filter. When the gain correction is further applied to this in step 120 of FIG.
As described above, it is sufficient to consider only the final digit cancellation by performing it at the end of the nth-order filter. If the gain correction is included in the first stage or the middle stage, the digit cancellation generated in the gain correction unit enters the latter stage, which is not desirable.

As described above, the present invention compensates for the digit cancellation of the digital filter and realizes accurate control tracking. All that is required for this operation is a memory that accumulates the fractional part when multiplied by a constant, and only a few steps are added to the program, which is a great advantage that no burden is imposed. Therefore, the constants can be appropriately set to realize control with excellent followability.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital filter of the present invention.

FIG. 2 is a block diagram of an example of an nth-order digital filter.

FIG. 3 is a block diagram of vehicle idle throttle control (ISC).

FIG. 4 is a flowchart of a digital low pass filter routine.

5 is a flow chart of the ISC of FIG.

FIG. 6 is a block diagram when a gain correction is applied to an nth-order digital filter.

FIG. 7 is a block diagram of a conventional digital filter.

FIG. 8 is an operation chart diagram when compensating for a digit cancellation error of a digital first-order lag low-pass filter according to a conventional proposal.

[Explanation of symbols]

1 subtraction means 2 multiplication means 3 integration means 4 overflow detection means 5 addition means 6 buffer means step 210 digital primary delay low-pass filter
Routine step 108 integrating means steps 110, 112, 114 overflow detecting means step 120 gain correction

Claims (1)

[Claims] 1. A digital filter having a multiplication element, wherein a multiplication unit that multiplies a filter constant of the multiplication element, and a value of a lower byte corresponding to a fractional part of a multiplication result of the multiplication unit is calculated for each multiplication. And an overflow detecting means for detecting that a value overflows ± 1 or more in the calculation result of the integrating means and outputting ± 1 only when the overflow occurs and outputting 0 otherwise. A digital filter comprising: a means and an addition means for adding the output of the overflow detection means to the value of the upper byte corresponding to the integer part of the multiplication result.