JPH07154469A - Storage device for sound data - Google Patents

Abstract

PURPOSE:To provide a storage device for sound data capable of performing additional storage as securing sound quality by which sound can be recognized when the additional storage of data is requested after a memory circuit for sound storage is saturated as the storage device for sound data. CONSTITUTION:When the storage saturation of the sound data on memory circuit 105 is detected in the storage device for sound data, a data operation circuit 102 reduces the data length of the sound data from a sound encoder circuit 101 by specific number of bits, and a write address generation circuit 103 varies the generation of an address for data arrangement for the memory circuit 105 corresponding to the status of a data operation in the data operation circuit 102. A data correction circuit 106 reads out the sound data from the memory circuit 105, and corrects the bits reduced by the data operation circuit 102 by adding the specific number of bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voice data storage device applied to an answering machine or the like.

[0002]

2. Description of the Related Art In recent years, a voice data storage device for an answering machine or the like is generally using a semiconductor memory or the like in addition to a conventional micro cassette tape. The use of semiconductor memory for storage devices, compared to those using conventional microcassette tape, such as improved reliability and operability by random access,
It is possible to easily realize enhancement of functions as an answering machine. On the other hand, however, since the recordable recording time is short, it is easy to cause a situation such as loss of voice data during storage or storage failure, and it is desired to realize more efficient storage processing.

To achieve this, a technique for reducing the data amount by processing audio data by a highly efficient compression method (see, for example, Japanese Patent Laid-Open No. 2-79549), or an empty area of a semiconductor memory (A region in which voice data generated between one voice data and another voice data is not stored) is excluded as much as possible, and a technique is issued to alert the operator by issuing an alarm immediately before the saturation of the storage (for example, , JP
No. 4-343553) is proposed.

[0004]

However, when voice data is stored using the above technique, although more data can be stored by compressing the data or eliminating the free space, the free space is completely removed. After being eliminated, the memory is completely stopped, and even a small amount of additional memory becomes impossible.

The present invention has been made in view of such a point, and when the semiconductor memory is saturated and there is a request for additional storage of data, a voice quality that can recognize a voice is ensured. An object of the present invention is to provide a voice data storage device capable of additional storage.

[0006]

SUMMARY OF THE INVENTION The present invention is a memory comprising a coding circuit for coding a voice signal into digital voice data, and a semiconductor memory for storing and storing the voice data encoded by the coding circuit. In a voice data storage device comprising a circuit and a decoding circuit for reading voice data from the memory circuit and decoding the voice data into a voice signal, memory saturation detection means for monitoring storage saturation of voice data in the memory circuit. A data operation means for reducing the data length of the audio data from the encoding circuit by a specific bit when the memory saturation detection means detects the saturation of the memory circuit; and a situation of data operation by the data operation means. In response to the address generating means for changing the generation of the data arrangement address for the memory circuit, and reading the audio data from the memory circuit. The reduced data in data manipulation means is intended and a data correction means for correcting by the addition of a specific bit.

[0007]

When the memory saturation detecting means detects the storage saturation of the voice data in the memory circuit, the data manipulating means reduces the data length of the voice data from the encoding circuit by a specific bit, and the address generating means uses the data. The generation of the data arranging address for the memory circuit is changed according to the status of the data operation by the operating means. Then, the data correction unit reads the audio data from the memory circuit and corrects the bit reduced by the data operation unit by adding a specific bit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention, a voice data storage device, will be described with reference to FIGS. Figure 1
FIG. 1 is a schematic configuration diagram according to an embodiment of the present invention, a voice data storage device. The voice data storage device digitizes an analog voice signal and performs a coding process to convert the voice signal into voice data having a specific bit length.
And a data operation circuit 102 as data operation means for performing bit replacement operation on digital audio data output from the audio encoding circuit 101 according to a specific procedure based on an instruction from a control circuit 104 described later, and an instruction from the control circuit 104. Write address generation circuit 1 as address generation means for generating a storage destination address in the memory circuit 105
03, a memory circuit 105 for storing and holding voice data output from the data correction circuit 102 at an address output from the address generation circuit 103, and a read address of the voice data stored in the memory circuit 105 according to an instruction from the control circuit 103. Read address generating circuit 107 for generating
And a data correction circuit 106 as data correction means for correcting the audio data read from the memory circuit 105 according to a specific procedure in accordance with an instruction from the control circuit 104, and decoding the digital audio data output from the data correction circuit 106. In addition, it is composed of a voice decoding circuit 108 for converting into an analog voice signal and a control circuit 104 as a memory saturation detecting means for monitoring the storage condition in the memory circuit 105 and controlling the whole.

In the audio data storage device having such a configuration, the PCM system for outputting digital audio data of 8-bit width is used as the audio encoding system, and the memory circuit 105 has 1 bit per address. The operation of storing and reproducing audio data when a semiconductor memory having a memory capacity of 256 bits for storing data is used will be described. FIG. 2 is a flowchart showing a procedure of a voice data storage operation according to an embodiment of the voice data storage device of the present invention.

FIG. 3 is a flow chart showing a procedure of an audio data read operation according to an embodiment of the audio data storage device of the present invention. FIG. 4 is a diagram showing a storage arrangement of audio data on the memory circuit 105 and an address generating operation in the write address generating circuit 103 according to an embodiment of the present invention. First, the operation of inputting and storing voice data will be described.

When the apparatus is activated, the control circuit 104 sets the bit length (bit length of the voice data stored in the memory circuit 105) of the voice data output from the voice encoding circuit 101 as an initial setting ( (Assuming 8 bits)
Also, the generation of the storage start address in the memory circuit 105 is set in the write address generation circuit 103 and the read address generation circuit 107, respectively (step 20).
2).

When the control circuit 104 detects the start of storage of voice data by an instruction from a communication partner terminal via an operation panel (not shown) or a communication line, or by directly inputting a voice signal, the input voice signal is input. Signal (Step 20)
3) is converted into digital 8-bit audio data by an instruction to the audio encoding circuit 101 (step 204). Here, although the input voice is assumed to be an analog voice signal in this embodiment, an already digitized signal such as a voice signal (for example, G.711 data) received via a digital line is input. If so, the voice encoding circuit 101 is unnecessary.

The voice data encoded by the voice encoding circuit 101 is continuously input to the data operation circuit 102,
Data operation is performed according to an instruction from the control circuit 104. At the start of storage, the data operation circuit 102 operates data because the memory circuit 105 is not storing voice data (memory capacity is not saturated: step 205). 104 is
The data operation circuit 102 is instructed not to perform an operation (8-bit input is not operated and 8-bit output is performed), and at the same time, the write address generation circuit 103 is generated with a data write address for each 8-bit (step 208: 40
Instruct 1). In this way, the 8-bit audio data output from the data operation circuit 102 is the address generation circuit 1
Continuous storage is repeated according to the write address in 8-bit units generated in step 03 (steps 209, 21).
0).

With repeated storage (step 203-)
210), and the control circuit 104 uses the memory circuit 1
The state of storage and storage in 05 is monitored (step 20).
5). Then, when the memory saturation of the memory circuit 105 is detected, the control circuit 104 sets 1 as a specific value from the initially set data length (set to 8 bits) (arbitrary and temporarily set to 1 bit for explanation). ) Is subtracted to newly set 7 bits (step 206), and the data operation circuit 102 is instructed to change the setting. Data operation circuit 102
Changes the data length, converts the input data of 8 bits into 7-bit data and outputs it (the least significant 1 bit that has the least influence on the voice quality is deleted and
Create bit data).

At the same time, the control circuit 104 also causes the write address generation circuit 103 to change the existing 8-bit address generation to 7-bit address generation (step 207: 402). Specifically, for all 8-bit data that has been stored so far, the least significant bit is stored in the memory area (8
It is allocated to each future address as a free area. As a result, about ⅛ of the total capacity of the memory circuit 105 can be secured as a new storage area (in the present embodiment, the data length was reset by 1 bit subtraction, but this was subtracted by 2 bit or 4 bit. Subtraction or the like is also possible, and if this is done, a larger free area can be secured), and a specific amount of additional storage is possible even after the memory circuit is saturated.

Repeating the voice data storage operation including the resetting of the above data length (steps 203 to 210) continues until the voice storage is stopped or the data length becomes the data length at which the recognition quality of the voice data cannot be secured. It is continuously performed (step 210). Now, the control circuit 104 is
When the end of storage of voice data is detected by an instruction from a communication partner terminal via an operation panel or a communication line (not shown), or a direct stop of a voice signal,
The final data length is stored in its own circuit or in the memory circuit 10.
The storage operation is completed by storing and storing in the specific position 5 (step 211).

Next, the reading and reproducing operation will be described. First, when the control circuit 104 detects the start of reading and reproduction of audio data by an instruction from a communication partner terminal via an operation panel or a communication line (not shown), the control circuit 104 moves to its own circuit or to a specific position of the memory circuit 105. The final data length of the voice data stored and held is read (step 302).

First, the read address generation circuit 1
07 is instructed to generate a read address in 8-bit units (step 303), and the data for each final data length is input to the read data correction circuit 106 from the start address. The data correction circuit 106 adds a specific bit (for example, all 0s) to the least significant bit side of the read data of the final data length so that it has a size of 8 bits, and performs voice decoding. Circuit 108
(Step 305).

The corrected audio data output from the audio decoding circuit 108 is returned to an analog audio signal by the audio decoding circuit 108 (step 306) and reproduced by a speaker (not shown) or the like (step 307). By the way, the read address is generated in the read address generation circuit 107. This is because the output of every 8 bits is generated immediately after the read reproduction is started, and when it reaches the final address of the memory circuit 105, The address is returned to the initial address and switched to the address generation for every 7 bits. The specific details of the address generation here are the same as the address generation operation of the write address generation circuit 103 at the time of writing (steps 303: 401, 40).
2).

In the above embodiments, the PCM for outputting 8-bit width digital audio data is used as the audio encoding system.
Although the case where the method is used has been described, the present invention can also be applied to a voice encoding method that realizes more efficient data compression by performing a specific process. For example, in the 7 kHz audio encoding method (G.722), which is one of the encoding methods, a digitized 14-bit digital audio signal is band-divided into a high band and a low band by an orthogonal mirror filter, The high-frequency signal is encoded by the high-frequency encoder into 2-bit high-frequency data, the low-frequency signal is encoded by the low-frequency encoder into 6-bit low-frequency data, and both signals are multiplexed to obtain 8-bit encoding. Although this is a coding method for outputting a signal, when this coding method is used in the present invention, the least significant bit of the audio data is selected as the data having the least influence on the reproduction quality of the audio in the PCM method. Similarly, high-frequency data can be selected as the data that is least affected by the reduction.

Further, in the above embodiments, the memory circuit 10
When 5 is saturated and the data is reduced in the data operation circuit 102, all the data already stored in the memory circuit 105 is treated as data of a new data length, but this is not particularly necessary. In the case where the voice storage ends immediately after the reduction is performed, that is, only the area near the start address of the memory circuit 105 is overwritten with the new data length, and the data before the reduction remains in the area near the end address. By storing and holding the final data length and the final write address together in the control circuit 104 and the like, it is possible to correct the data only for the reduced data.

[0022]

As is apparent from the above description, the present invention successively monitors the state of data storage in the memory circuit, and detects storage saturation in the memory circuit before detecting the voice storage end instruction. From the data already stored in the memory circuit, the data that has the least influence on the reproduction quality of the voice is selected and new voice data is recorded at that address. Therefore, even if the memory circuit is saturated, if there is a request for additional storage of data, it is possible to provide a voice data storage device capable of performing additional storage while ensuring voice quality that allows voice recognition.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a voice data storage device according to an embodiment of the present invention.

FIG. 2 is a flow chart diagram showing a procedure of a voice data storage operation according to an embodiment of a voice data storage device of the present invention.

FIG. 3 is a flowchart showing a procedure of an audio data read operation according to an embodiment of an audio data storage device of the present invention.

FIG. 4 is a memory data storage arrangement and a write address generation circuit 1 on a memory circuit 105 according to an embodiment of the present invention.
It is a figure which shows the operation | movement of the address generation in 03.

[Explanation of symbols]

 101 voice coding circuit 102 data operation circuit 103 write address generation circuit 104 control circuit 105 memory circuit 106 data correction circuit 107 read address generation circuit 108 voice decoding circuit

Claims (3)

[Claims] 1. An encoding circuit for encoding an audio signal into digital audio data, a memory circuit including a semiconductor memory or the like for storing and accumulating audio data encoded by the encoding circuit, and an audio from the memory circuit. In a voice data storage device comprising a decoding circuit for reading data and decoding it into a voice signal, a memory saturation detection means for monitoring storage saturation of voice data in the memory circuit, and the memory saturation detection means Data operation means for reducing the data length of the audio data from the encoding circuit by a specific bit when saturation of the memory circuit is detected, and data arrangement for the memory circuit according to the situation of data operation in the data operation means Address generating means for changing the generation of the use address and audio data read from the memory circuit and the data reduced by the data operating means. And a data correction unit that corrects the data by adding a specific bit. 2. The least significant data, wherein the data operating means performs data reduction in order from the least significant bit of audio data output from the encoding circuit each time the memory saturation detecting means detects saturation of the memory circuit. The audio data storage device according to claim 1, further comprising an operating unit. 3. The high-frequency data operating means for reducing the data sequentially from the high-frequency component of the audio data output from the encoding circuit each time the memory operation detecting means detects the saturation of the memory circuit. The audio data storage device according to claim 1, further comprising: