JPH07121195A - Sound processing digital signal processor - Google Patents

Abstract

PURPOSE:To reduce power consumption by stopping or decelerating the operation of a sound processing digital signal processor when a soundless state is detected. CONSTITUTION:A high speed master clock operating a digital signal processor part 3 by detecting the soundless state of the input sound data is frequency divided to a low period clock, or is stopped. The detection of the soundless state of the input audio data is performed based on a bit clock supplied together with the input data. In such a case, when no bit clock is supplied, the soundless state is judged. Thus, power consumption in the period of the soundless state of the input audio data is reduced, and the power of the digital signal processor itself is saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor for voice processing which handles digitized voice.

[0002]

2. Description of the Related Art Conventionally, a digital signal processor (DSP) has been used for voice processing, image processing, etc., which requires extremely high-speed arithmetic processing. FIG. 2 is a block diagram showing the configuration of a conventional digital signal processor for voice processing. In this figure, 1 is an input terminal to which audio data is supplied, 2 is a serial / parallel converter, 3
Is a digital signal processor unit, and 4 is an output terminal for taking out the output of the digital signal processor unit 3 to the outside. The serial / parallel converter 2 operates in synchronization with a bit clock supplied from the outside together with the input audio data. The digital signal processor unit 3 uses a high-speed master clock supplied externally (or supplied by self-excited oscillation) asynchronously or in synchronization with the bit clock, or a clock obtained by dividing the high-speed master clock. Operate.

[0003]

By the way, in the above-mentioned conventional digital signal processor, the power consumption, especially the entire LSI, is improved by improving the performance by accelerating the operation of the circuit and increasing the circuit scale. The power consumption of the digital signal processor unit 3 which occupies most of the power consumption becomes large, which requires the enhancement of heat generation processing of the LSI package and impedes the power saving of the applied device. is there.

Therefore, an object of the present invention is to provide a digital signal processor for voice processing which can save power.

[0005]

To achieve the above object, a voice digital signal processor according to the present invention comprises a silent state detecting means for detecting a silent state of input voice data,
And a frequency dividing means for dividing or stopping a high-speed master clock for operating the digital signal processor unit into a low-cycle clock when a silence state of the input voice data is detected. Further, as a preferred mode, the silent state detecting means detects the silent state based on a bit clock supplied together with the input voice data.

[0006]

According to the present invention, when the silence state of the input voice data is detected, the high-speed master clock for operating the digital signal processor is divided into low-frequency clocks, or
Or stop it. The silent state of the input voice data is detected, for example, by detecting it based on a bit clock supplied together with the input data. That is, it is determined that there is no sound depending on the low level state and the direct current state of the input audio data synchronized with the bit clock. Therefore, the power consumption of the input voice data during the silent period is reduced, so that the power consumption of the digital signal processor itself can be reduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a voice digital signal processor of the present invention. In this figure, the same parts as those in FIG. 2 described above are designated by the same reference numerals. In FIG. 1, reference numeral 5 denotes a silence state detection unit that detects a silence state of input voice data, and outputs a silence detection signal when a silence state of the input voice data is detected. The silent state of the input voice data is detected, for example, by detecting it based on a bit clock supplied together with the input data. That is, it is determined that there is no sound depending on the low level state and the direct current state of the input audio data synchronized with the bit clock. The silent state detecting section 5 is inserted between the input terminal 1 and the serial / parallel converting section 2 as shown in the figure. It should be noted that it may be inserted between the serial / parallel conversion unit 2 and the digital signal processor unit 3. Reference numeral 6 denotes a frequency divider, which divides a high-speed master clock supplied from the outside to operate the digital signal processor unit 3 into 1 / N and outputs it. The frequency division unit 6 divides the high-speed master clock into 1 / N from the time when the silence detection signal is output from the silence state detection unit 5.

The frequency division ratio in the frequency division unit 6 is such that the operation data of the digital signal processor unit 3 is stopped or the operation data after the operation is restored can maintain the normal operation. In this case, even if the digital signal processor unit 3 stops operating or operates at such a low speed that the operation state can be maintained, the serial / parallel conversion unit 2 and the silent state detection unit 5 are supplied from the outside together with the audio data. Since the digital signal processor 3 operates normally by the bit clock, even if the digital signal processor unit 3 returns to the normal operation when a sound occurs and no problem occurs, the digital signal processor itself operates normally.

As described above, when the silence state of the voice data supplied through the input terminal 1 is detected by the silence state detecting section 5, the silence detecting signal is output and supplied to the frequency dividing section 6. When the silence detection signal is supplied to the frequency dividing unit 6, the high speed master clock is frequency-divided to 1 / N and supplied to the digital signal processor unit 3. As a result, the digital signal processor unit 3 operates at such a low speed that the operation can be stopped or the operation state can be maintained. Here, 70-80% of the digital signal processor itself is saved when the operation of the digital signal processor unit 3 is stopped, and about 50% of the digital signal processor itself is saved when the high-speed master clock is divided in half. Electricity can be saved.

Among digital signal processors, some of the oversampling filters and D / A converters have a function of digitally detecting a silent state and forcibly attenuating an analog output signal. Is to improve the characteristic (S / N) at the time of a small signal. In addition, the detection of silence is
It is determined that there is no sound by combining the low level state of the upper bits of the input voice data and the DC state of the lower bits. For reference, FIG. 3 shows a block diagram of a digital signal processor having this function. In this digital signal processor, when the silence state of the voice data is detected by the silence state detecting unit 7, the silence detecting signal is output and the attenuating unit 8 is output.
Is supplied to. As a result, the analog output signal output from the digital signal processor unit 3 is attenuated.

In the above embodiment, the silence state of the input voice data is detected by the silence state detecting section 5, and the high speed master clock is divided by the dividing section 6. The function of may be performed by a microcomputer. In this case, by using the microcomputer built in the device to which the digital signal processor of the present invention is applied, it is possible to suppress the price increase of the device. Further, in the above embodiment, when the silence state of the input voice data is detected, the operation of the digital signal processor unit 3 is stopped or slowed down. However, in addition to the above, when the application does not use the digital signal processor itself, The operation of the digital signal processor unit 3 may be stopped or slowed down by detecting the time such as recording or turning off the sound field processing.

[0012]

According to the present invention, the operation of the digital signal processor unit is stopped or slowed down when the silence state of the input voice data is detected. Therefore, the power consumption in the silence state period of the input voice data is improved. Less consumption,
Power saving of the digital signal processor itself can be achieved. Further, since the power saving can be achieved, the heat generation process of the LSI package can be simplified and the power saving of the applied device can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a voice digital signal processor according to the present invention.

FIG. 2 is a block diagram of a conventional audio digital signal processor.

FIG. 3 is a block diagram of another example of a conventional digital signal processor.

[Explanation of symbols]

 5 Silence state detection section (silence state detection means) 6 Frequency division section (frequency division means)

Claims (2)

[Claims] 1. A silence state detecting means for detecting a silence state of input voice data, and a high-speed master clock for operating a digital signal processor section when the silence state of the input voice data is detected is divided into a low cycle clock. Or a frequency dividing means for stopping the digital signal processor for audio processing. 2. The digital signal processor for voice processing according to claim 1, wherein said silence state detecting means detects the silence state based on a bit clock supplied together with the input voice data.