JPH07120703B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

2. Description of the Related Art Conventionally, the LOCOS method has been generally used as an element isolation technology for semiconductor MOS transistors, and the BOX method (IEDM83-27 Toshiba in 1983) has begun to be applied to recent submicron transistors.

Problems to be Solved by the Invention The LOCOS method is shown in FIG. As shown in the figure, when a part of the substrate 1 is oxidized by using the pad SiO ₂ , Si ₃ N ₄ 8 on the silicon substrate 1 as a mask to form an oxide film 90, an oxide film biting portion called bird's beak 9 is formed. , 3 _A by narrowing the effective channel width of the transistor formed in the 1 _A part.
As shown by the curve 100 in the figure, a phenomenon called narrow channel effect occurs. For this reason, it is difficult to apply it to element separation of 2 μm or less. Figure 3 shows the narrow channel effect, curve 20
0 indicates the method of the present invention described later, and 300 indicates the inverse channel effect of the conventional BOX method.

On the other hand, an example of the BOX method is shown in FIG. Oxide film 2 and PolySi3 are formed on the substrate 1, and the P
The substrate 1 is dry-etched using olySi3 and the oxide film 2 as a mask. Next, CVD SiO ₂ 6 is deposited and a resist 7 is spin-coated. After that, dry etching is performed under the etching conditions such that the resist 7 and the CVD SiO ₂ 6 have the same etching rate to planarize. Finally, PolySi 3 and SiO ₂ 2 in the device area are selectively removed. The BOX process, because there is no biting of the SiO ₂ of element regions, such as LOCOS method, is suitable for miniaturization of the element. However, the BOX method also has drawbacks.

Electric field concentration occurs at the corner portion (edge portion) 400, the threshold voltage at the corner portion decreases, an excessive current flows at the corner portion, and the hump current shown in the transistor characteristic 500 of FIG. 5 flows. In addition, 600 is a normal characteristic.
Therefore, an inverse narrow channel effect, which is the reverse of the LOCOS method, occurs.

Therefore, at the stage of FIG. 4 (a), as shown in FIG.
A method of suppressing the hump current by increasing the threshold voltage at the corner by performing tanning ion implantation and heat treatment is adopted. Reference numeral 50 is an implantation region, and 51 is a diffusion region. However, in this method, most to easily flow corner of hump currents, PolySi3 and SiO ₂ 2 can not sufficiently injected for the surface. Further, since the injection is performed from the side surface, the injection efficiency itself from the side surface is poor due to the influence of reflection. Therefore, it is necessary to increase the implantation concentration in order to obtain a sufficiently high threshold voltage at the corners. Then, the implanted ions are exuded to the channel portion, which affects the characteristics. Therefore, it is difficult to control the injection amount.

Therefore, the inclined box shown in Fig. 7 was proposed. By inclining such a corner portion, electric field injection at the corner portion is reduced. As a result, the amount of ion implantation for lowering the threshold value at the corner can be reduced. Therefore, the exudation of implanted ions into the channel portion can be reduced. However, in this case, for example, areas 1 _A , 1 _B
Although transistors are formed in each of the above, there is a drawback that the isolation breakdown voltage between adjacent transistors is reduced.

Means for Solving the Problems In order to solve the above problems, in the BOX separation method, a layer in contact with a semiconductor in a multilayer film on an element region used as a mask for etching a semiconductor in a field region, or By side-etching the layer on the insulating film in contact with the semiconductor and forming the insulating film to be embedded in the field region also on the side-etched part, an insulating film thicker than the gate oxide film is formed at the corner of the element region. It suppresses the electric field concentration at the corner, and hump at the corner.
It suppresses the electric current.

Function The present invention can form an insulating film thicker than the gate oxide film on the semiconductor corner portion of the element region by the above method. Moreover, the portion where the thick insulating film is formed is the portion where the side etching is performed. Since this side etching can be performed at the time of selective etching of the multilayer film, any side etching can be performed. Therefore, a thick insulating film can be formed in an arbitrary width of the corner portion.

As a result, the electric field concentration at the corners can be reduced, and the decrease in the threshold voltage at the corners can be suppressed. That is, hu
The mp current can be suppressed.

Practical Example FIG. 1 shows an embodiment of the present invention.

In (a), 20 nm SiO ₂ (thermal oxide film) of 2,140 n is formed on the Si substrate 1.
After forming mPolySi3, 500 nm PSG4, PSG4 in the field region is dry-etched, and then PolySi3 is further etched. At this time, PolySi3 is etched under the condition of 50 nm side etching. Since there is SiO ₂ 2 below, PolyS
Since i3 can be selectively etched, arbitrary side etching is possible.

In FIG. 5B, the SiO ₂ 2 and the portion to be the field region of the Si substrate 1 are etched by 500 nm by anisotropic dry etching using PSG4 as a mask. Since anisotropic dry etching is used, the edges of PSG 4, SiO ₂ 2 and Si substrate 1 are aligned, and only the edge of PolySi 3 is recessed by 50 nm.

(C) After removing PSG 4 in the figure, CVD SiO ₂ 5 is deposited. In this step, the thick insulating film 15 can be formed at the corner. Further, a resist 6 is applied to flatten the surface.

In FIG. 3D, under the drive etching conditions in which the CVD SiO ₂ 5 and the resist are etched at a constant rate, etching is performed until the surface of PolySi 3 is exposed to form SiO ₂ for separation in the field region.

(E) in FIG, removing PolySi3 and SiO ₂ 2 on the element region.
As a result, an element isolation structure separated by SiO ₂ 5 is formed.

After that, a part of the device forming region 10 of the substrate 1 is formed by a usual method.
A gate oxide film, a gate electrode, a source, a drain, etc. are formed on the substrate to form a transistor (not shown).

By this method, an insulating film thicker than the gate oxide film can be formed at the corner of the element region. In addition, the width of this thick insulating film corresponds to the side etching amount, and since this side etching can be performed during the selective etching of the multilayer film, any side etching can be performed. Therefore, a thick insulating film can be formed in an arbitrary width of the corner portion. Sectional shape of the present invention is similar to the LOCOS isolation, in that uncontrolled bite of SiO ₂ in the LOCOS isolation, significantly different from the present invention.

As a result, the electric field concentration at the corners can be reduced, and the decrease in the threshold voltage at the corners can be suppressed. That is, hu
The mp current can be suppressed.

EFFECTS OF THE INVENTION Since the insulating film that is thicker than the gate oxide film is formed at the corner of the element region, it is possible to suppress electric field concentration at the corner. Therefore, it is possible to suppress the decrease in the threshold voltage of the corner portion and suppress the hump current.

Further, the thick insulating film region at the corner portion can be controlled by the side etching amount. Since this side etching can be performed at the time of selective etching of the multilayer film, any side etching can be performed. Therefore, a thick insulating film can be formed in an arbitrary width of the corner portion. As described above, the present invention is capable of forming a semiconductor element with a fine performance without deterioration of the density at a high density, and greatly contributes to the manufacture of a large-scale LSI.

[Brief description of drawings]

FIG. 1 is a process sectional view of an embodiment of the present invention, and FIG. 2 is
Process sectional view of LOCOS method, Fig. 3 shows channel width effect of each separation method, Fig. 4 is process sectional view of conventional BOX method, Fig. 5 is transistor characteristic diagram of conventional BOX method, and Fig. 6 is Sectional view showing the state of licking ion implantation, Figure 7 is inclined
It is sectional drawing which shows the BOX method. 1 …… Si substrate, 2 …… SiO ₂ , 3 …… PolySi, 4 …… PS
G, 5, 15 ... CVD SiO ₂ , 6 ... Resist, 10 ... Element formation region.

Claims (1)

[Claims] 1. A step of forming a multilayer film on an element formation region on a semiconductor substrate and etching a field region of the semiconductor substrate using the multilayer film as a mask, and the multilayer film left on the element formation region. A step of side-etching a layer in contact with the semiconductor substrate or a layer on the first insulating film in contact with the semiconductor substrate, and a step of forming a second insulating film in the side-etched portion and the field region. Etching the second insulating film until the surface of the side-etched layer is exposed without etching the semiconductor substrate in the element forming region, and a corner of the semiconductor substrate in the element forming region A method of manufacturing a semiconductor device, comprising: the step of leaving the second insulating film on the upper surface of the substrate; and the step of forming a semiconductor element on the element forming region.