JPH0676565A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a VRAM accelerating operation speed without increasing a manufacturing cost. CONSTITUTION:This device is provided with a write/read control circuit 31 including a level identification circuit 311 controlled by a logical operation enabling signal IORE and for identifying the level of an input signal DI. Based on the result of identifying the logical level of the input signal DI either the writing of the input signal DI or the refreshing of selective memory cell information is carried out for a selective memory cell and thus, a logical operation is effectively carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a dynamic random access memory (DRAM) for image processing having a high-speed image processing function.

[0002]

2. Description of the Related Art A DRAM of this type, which is arranged between a CPU and a data display device in a small computer such as an EWS or a personal computer and which writes / reads data for display under the control of the CPU, It is also called a video RAM (VRAM) or graphics memory and has been widely used. In addition, the speed and flexibility of image processing required for this type of VRAM are increasing more and more. In response to these demands, a write per bit function for random writing described in U.S. Pat. No. 4,633,441 and one clock pulse cycle for a cell of a specified block unit composed of a plurality of bits (32 or 64) The VRAM is now provided with a block write function for writing data in, and a flash write function for writing data in a specified number of cells (8 or 16 rows) in one cycle.

However, when a control circuit for a laser printer or the like is constructed with this type of VRAM, when the figure is formed or changed, the pixel data stored in the VRAM is once read and new pixel data and display conditions are set. Then, the changed pixel data is formed and rewritten to the original address. That is, a VRAM that spans multiple clock pulse cycles to create and modify graphics.
Access operation and CPU arithmetic operation are required. Of the above logical operations in the control circuit of the laser printer, the most frequently performed operation is the OR operation.
The R operation result is rewritten in the VRAM. This requires a read / logical operation / rewrite operation time of at least three clock pulse cycles including access to the CPU and VRAM.

In order to shorten this operation time, the invention described in US Pat. No. 4,951,251 sets a level of a predetermined control signal supplied to a semiconductor chip forming a VRAM prior to a chip selection signal. The semiconductor chip is provided with an internal circuit for making a judgment, fetching a signal supplied from the address terminal in synchronization with the chip selection signal as a function signal, and performing various operations including the above logical operation function in response to the function signal. Proposed VRAM. That is, this internal circuit includes a logical operation circuit for generating a signal for rewriting by subjecting the read output from the RAM to the logical operation with the write signal from the external terminal in response to the function signal. When the logical operation in response to the function signal is an OR operation that produces a logical sum (OR), the read output from the RAM is read-modify-write (read-modify-wr).
The “ite” operation performs an OR operation with the input image data, the OR output is rewritten as new pixel data at the original address of the read output, and these operations are completed in one clock pulse cycle.

Referring to FIG. 4 which shows a block diagram of a conventional VRAM (for convenience of explanation, a multi-bit output type memory in which data is written / read in 4-bit units) is referred to, a 4-bit code is used in the conventional VRAM. Can access word or × 4 bit pattern simultaneously ×
4 based on 4-bit dynamic RAM
A memory section (RAM) 11 including a pair of memory arrays, a sense amplifier (not shown), and row and column address decoders (neither shown), and a refresh address counter (not shown) for forming a refresh address signal. A row for forming an internal complementary address signal that takes in an external address signal in synchronization with a timing signal formed by a control circuit (REFC) 12 and a row address strobe signal inverted (hereinafter I) RAS and transmits the row address decoder to the row address decoder. Address buffer (R-ADB) 1
3 and a column address buffer (C- which forms an internal complementary address signal for receiving the external address signal in synchronization with the timing signal formed by the column address strobe signal ICAS and transmitting it to the column address decoder.
ADB) 14, the operation mode signal fn for decoding the function setting signal FF and setting the operation mode of the logical operation circuit 17, the mask signal msk for selectively invalidating the operation of the data input circuit 20, and the gate circuit 18. Function setting circuit (F
N) 15, the signals IRAS / ICAS and the write enable signal IWE are supplied and the operation mode instructed by the combination of these signals is identified to identify the timing signals φr, φ.
A timing signal generating circuit (TC) 16 for generating various timing signals for other internal circuits such as fn, and four sets of circuits corresponding to the four sets of memory arrays of the memory section 11 are provided at one input. It receives the signal held in the latch circuit 19 and the write signal, and performs a logical product (AND), a negative logical product (NAND), and a logical sum (O) between these signals.
R), a negative logical sum (NOR), an inversion (NOT), an exclusive logical sum (EX-OR), and the like. A logical operation circuit (LU) 17 that generates logical operation outputs in response to the operation mode signal fn.
And a gate circuit (G) 18 for passing the input codeword through the circuit 17 and supplying it to the memory unit 11 without applying the logical operation to the I / O of the memory unit 11
A latch circuit (F) 19 for latching an output codeword from O, a data input circuit (IB) 20, and a data output circuit (OB) 21 are provided. Further, a data output terminal group Do and a data input terminal group Di (each shown as one terminal for convenience of illustration) each including four parallel terminals are provided.

The timing signal generation circuit 16 is configured to identify the operation mode as follows. That is, the timing signal generation circuit 16 operates when the signal IRAS, which is a substantial chip selection signal, is set from the high level (inactive level) to the low level (active level).
When the column address strobe signal ICAS and the write enable signal IWE are set to low level (enable level), these signals IRAS / ICAS are set.
It is recognized as a preset operation mode from the combination of / IWE. This preset operation mode continues until the signal IRAS is set to the high level again. During this preset operation mode period, the timing signal generation circuit 16 generates the timing signal φfn. If the signal IWE is set to the high level (inactive level) when the signal IRAS changes from the high level to the low level, these signals I
It is recognized as an access operation state from the combination of RAS / IWE.

In addition to FIG. 4, FIG. 5 (A) and FIG. 5 (B)
Referring to, the refresh operation is first performed as follows. Before the signal IRAS changes from the high level to the low level, the signal ICAS and the signal IWE are set to the low level. As a result, the internal circuit is activated in synchronization with the transition point of the signal IRAS from the high level to the low level, and the timing signal generation circuit 16 generates the refresh signal φrf and the refresh control circuit 2
2, and various timing signals such as a refresh address signal are generated to start a refresh cycle. (CAS before RAS refresh). During this refresh operation, the input terminal of the row address buffer 13 is coupled to the refresh control circuit 22 and separated from the external address terminal.

The timing signal generating circuit 16 is a signal IC
When it is detected that both AS and signal IWE are at low level, in response to the change of signal IRAS to low level, timing signal φc for activating column address buffer 14 and activation of function setting circuit 15 are set. The timing signal φfn is generated. Since the data line selection timing signal .phi.y is not generated in the refresh operation, the column address decoder in the memory section 11 is practically placed in the inactive state. Therefore, the function signal FF supplied from the address terminals AT0 to ATi and passing through the column address buffer 14 is set to the operation setting circuit 15 at this time.
Be taken into. The function setting circuit 15 holds the fetched function signal FF and decodes it to generate various mode signals corresponding to the next operation.
In this way, the refresh operation and the fetch operation of the function signal FF are performed in parallel during the same memory cycle (refresh cycle). These signals IRA
S, ICAS, and IWE are set to the high level to temporarily reset the internal circuit. Even in this reset state, the function setting circuit 15 outputs the function signal F.
Continues to hold F.

Next, in response to the change of the signal IRAS from the high level to the low level, the timing signal generating circuit 1
6 generates a timing signal .phi.r to activate the row address buffer 13 so that the address terminals AT0 to ATi
From the row address signal AX (AX0 to AX0
AXi), and the word line selection operation of the memory section 11 is performed.

Next, in response to the change of the signal ICAS from the high level to the low level, the timing signal generating circuit 1
6 generates a timing signal .phi.c to activate the column address buffer 14 so that the address terminals AT0 to AT
The address signal from i is converted to the column address signal AY (AY
0 to AYi), and the bit line selection operation of the memory section 11 is performed. As a result, the address signals AX and A
The storage information DA of the memory cell designated by Y and Y is read by the latch circuit F.

On the other hand, in the write operation mode in which the signal IWE is at the low level, the input code word DB from the input data terminal Di is taken in via the data input circuit 20. When the function setting circuit 18 uses the function signal FF to instruct the logical operation circuit 17 to perform an OR operation, for example, by the above-mentioned function setting, the logical operation circuit 17 causes the signal DA of the latch circuit 19 to be output.
And a signal DA + representing an OR output between the input signal DB and the input signal DB.
DB (hereinafter referred to as data signal DW) is formed and transmitted to the I / O node of the memory section 11 to rewrite the selected memory cell. The one-cycle write operation by the read-modify-write is performed in this manner, and the storage information of the memory cell is replaced with the data of the designated logical operation result between the storage information and the write data from the outside. In the above description, the signal DA / DB / DW is one signal for convenience of description, but it is actually a complementary signal composed of a pair of positive and negative signals.

Writing to the selected memory cell is performed as follows according to the values of the complementary data signal DW and the inverted signal IDW. That is, the signal DW is logic 1, the inverted signal IDW
Is logic 0, a logic 1 is written in the selected memory cell. On the other hand, when the signal DW is logic 0 and the inverted signal IDW is logic 1, logic 0 is written. When both the signal DW and the inverted signal IDW are logic 1, writing is prohibited and the cell data is refreshed.

When the stored information in the memory cell is simply replaced with the input code word DB, the function setting circuit 15 generates the pass signal ps instead of the function signal fn and supplies it to the gate circuit 18. This allows
A write operation can be performed at high speed as in a normal DRAM.

[0014]

The conventional semiconductor memory device described above executes a logical operation by a read-modify-write operation. This read-modify-write operation involves a read operation as compared with a simple write operation. The disadvantage is that it only takes a long time. This kind of VRA
As an example of the above time in M, the read-modify-write operation cycle time reaches 260 nS, which is a normal write operation cycle time of 190 nS, which is about 37% more than the former case.

Further, the internal circuit is a function setting circuit for generating a function signal for enabling the logical operation and a plurality of other logical operations, an operational circuit for executing the logical operation, and the RAM read output storage. Since a latch circuit or the like is required, there is a drawback that the manufacturing cost of VRAM is increased.

Therefore, an object of the present invention is to provide a VRAM having an increased operation speed without increasing the manufacturing cost.

[0017]

In a semiconductor memory device of the present invention, a plurality of memory cells arranged in an array in both row and column directions, selecting means for these memory cells, and reading means for holding information in these memory cells are provided. And dynamic memory means including means for writing input data to these memory cells, a first input terminal for receiving an input data signal, and holding information of the input data signal selected from the memory cells. A third input terminal for receiving a logical operation enable signal for performing a predetermined logical operation between the second input terminal and a third input terminal for receiving a write enable signal for instructing the writing means to write into the selected memory cell. Input terminal, the write enable signal and the logic arranged between the memory means and the first, second and third input terminals. Either the first level or the second level corresponding to the operation result of the logical operation in which the level value of the input data signal is predetermined in synchronization with the logical operation timing signal supplied in response to activation with the arithmetic operation enable signal. Level determining means for determining whether or not
At the level of, the input data is supplied to the memory writing means, and when the level value is at the second level, the memory writing means is instructed to write-inhibit. It is equipped with.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 4 are designated by common reference numerals, the embodiment of this invention shown in FIG. The semiconductor memory device of the present invention uses an ORE instead of the timing signal generation circuit 16.
Timing signal generation circuit (TC) which further receives the supply of the signal IORE and further generates the logical operation timing signal φL
16A and a write / read control circuit 31 corresponding to the logical operation circuit 17 for determining the logical value of the input data DI in response to the signal IORE and supplying the write data DW to the memory section 11 when this logical value is at a high level. , Signal I
The ORE input circuit (OR which forms the buffer circuit of the ORE
EB) 32.

The write / read control circuit 31 includes the input circuit 3
A level determination circuit 311 which determines the logical value of the signal DB corresponding to the input signal DI supplied via the data input circuit 20 when the signal LO corresponding to the signal IORE via 2 is at a low level (active level). A write control circuit 3 that generates write data DW when the logical value of the output OD of the rule determination circuit 311 is at a high level, and inhibits the generation of the write data DW when at a low level and refreshes the selected memory cell.
12 and. The signal DW is a complementary signal composed of a pair of the positive signal DW and the inverted signal IDW as in the above-mentioned conventional example.

Referring also to FIG. 2 showing a specific example of the level determination circuit 311 and the write control circuit 312, the logical value determination circuit 311 inverts the signal DB to generate a signal IDB, and an inverter I31. This signal I
The write control circuit 312 includes a NAND gate E31 that produces a NAND of the signal DB and the signal LO.
NOR that produces the NOR of B and the timing signal φL
A gate E32, an inverter I32 that inverts an output signal of the gate E32 to generate an inverted signal IDW, and a NAND
A NOR gate E33 which produces a NOR of the output of the gate E31 and the logical operation control signal φL, and this gate E33.
Inverter I33 which inverts the output signal of to produce the signal DW
With.

Timing signal generating circuit 16A of this embodiment
Responds to the supply of the ORE signal IORE when the write enable signal IWE is at the low level (active level), in addition to the discrimination between the preset operation mode and the access operation mode similar to the above-described conventional timing signal generation circuit 16. The logical operation (OR write) mode that further generates the logical operation timing signal φL is identified.

Referring also to FIG. 3, first, the same refresh operation as in the case of the above-described conventional VRAM is performed. Next, when the signal IRAS falls to the low level, the signal IWE is set to the high level and the signal IORE is set to the low level, whereby the OR operation mode is set. Next, in the write operation mode (write cycle) in which the signal IWE is in the low level state, the input code word DI from the input data terminal Di is taken in via the data input circuit 20 and a corresponding signal DB is generated. , And is supplied to one input of the level determination circuit 311. On the other hand, the signal IORE generates a corresponding signal LO via the ORE input circuit 32 and is supplied to the other input of the level determination circuit 311. The level determination circuit 311 uses the input codeword D
If the logical value of the signal DB corresponding to I is logic 1 or logic 0, the write control circuit 312 writes the logic 1 if the determination result is the former, and prohibits the write if the latter is the cell Instructing rewriting of data DC, that is, refreshing.

Still referring to FIG. 2, the signal DB is inverted by the inverter I31 and the NAND gate E31 and NOR.
It is supplied to the gate E32. The NAND gate E31 supplies the inverted signal I (LO · DB), which is the NAND of the inverted signal ILO and the inverted signal IDB, to one input of the NOR gate E33. NOR gate E32 is an inverted signal ID
B produces a NOR output of the timing signal φL and this NO
The R output is inverted by the inverter I32 and the inverted signal IDW
Next, it is supplied to the memory unit 11. NOR gate E33
Generates a NOR output of the inversion signal I (LO · DB) and the timing signal φL, and this NOR output is inverted by the inverter I32 and becomes the signal DW, which is supplied to the memory section 11.
If the signal DB is logic 1, as is apparent from the above description of the operation, the signal DW becomes logic 1, the inverted signal IDW becomes logic 0, and the logic 1 is written in the selected memory cell. On the other hand, if the signal DB is logic 0, the signal DW and the inverted signal ID
Both Ws have a logic 1, and writing to the selected memory cell is prohibited and refreshing is performed.

As described above, in the arithmetic circuit of this embodiment, when the logical sum of the input code word DI and the read output DC of the selected memory cell is DI, the logical sum is always a logic value regardless of the logic value of DC. 1 and, on the other hand, when the input codeword DI is logic 0, it is always matched with the logic value of DC. That is, it is determined whether the logic value of the signal DI is a logic 1 or a logic 0, and when the logic 1 is the logic 1, the logic 1 is written, and when the logic 0, the writing is prohibited and the cell data DC is refreshed. It is based on the fact that the OR operation can be effectively executed by.

The same operation can be performed for the AND operation. In this case, when the input codeword DI is logic 0, this logic 0 is written in the selected memory cell, and when it is logic 1, the data in the selected memory cell is refreshed. A circuit configuration therefor can be inferred by those skilled in the art from the level determination circuit corresponding to the OR logic operation described above, and therefore the description thereof will be omitted.

[0026]

As described above, the semiconductor memory device of the present invention can achieve the above-mentioned logical operation without increasing the cycle time, and is therefore suitable for speeding up the operation of a laser printer or the like. ing. Further, by limiting the logical operations to the essentially indispensable operations, there is an effect that the circuit configuration for realizing the operations is simplified and the manufacturing cost is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram of a write / read circuit which is a part of this embodiment.

FIG. 3 is a timing chart showing the operation of the semiconductor memory device of this embodiment.

FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device.

FIG. 5 is a timing chart showing the operation of the conventional semiconductor memory device.

[Explanation of symbols]

 11 Memory Section 12 Refresh Control Circuit 13 Row Address Buffer 14 Column Address Buffer 15 Function Setting Circuit 16, 16A Timing Signal Generation Circuit 17 Logical Operation Circuit 18 Gate Circuit 19 Latch Circuit 20 Data Input Circuit 21 Data Output Circuit 31 Write Read Control Circuit 311 Level determination circuit 312 Write control circuit I31 to I33 Inverter E31 NAND gate E32, E33 NOR gate

Claims (4)

[Claims] 1. A plurality of memory cells arranged in an array in both row and column directions, selecting means for these memory cells, reading means for holding information of these memory cells, and writing means for writing input data to these memory cells. A dynamic type memory means including: a first input terminal supplied with an input data signal; and a logical operation for applying the input data signal to a predetermined logical operation between holding information of a selected one of the memory cells. A second input terminal supplied with an enable signal and a third input terminal supplied with a write enable signal for instructing the writing means to write into the selected memory cell; the memory means and the first , And is provided between the second and third input terminals and provided in response to activation of the write enable signal and the logical operation enable signal. Logical operation Tamingu signal in synchronization of the logic operation level value of the input data signal is a predetermined operation result corresponding to the first to be
And a second level, and when the level value is the first level, the input data is supplied to the memory writing means so that the level value is the second level. A semiconductor memory device, comprising: a logical operation data write control means including a write control means for instructing the memory write means to write at the time. 2. The semiconductor memory device according to claim 1, wherein the logical operation is an OR operation, and the first and second levels are a logical 1 level and a logical 0 level, respectively. 3. The semiconductor memory device according to claim 1, wherein the logical operation is an AND operation, and the first and second levels are a logical 0 level and a logical 1 level, respectively. 4. The NAND gate and the NAND gate, wherein the logical operation data write control means produces a negative logical product of the inverted value of the input data and the logical operation enable signal.
A first NOR gate that produces a negative logical sum of the output of the gate and the logical operation Taming signal; and a second NOR gate that produces a negative logical sum of the inverted value of the input data and the logical operation Taming signal. The semiconductor memory device according to claim 1, wherein: