JPH0670307A - Moving picture conding decoding device - Google Patents

Abstract

PURPOSE:To avoid overflow/underflow of a reception buffer memory when the processing frequency of a coder differs from that of a decoder. CONSTITUTION:A coder 100 uses an inter-frame prediction coding circuit 110 to implement the variable length coding for a digital picture signal and a multiplexer circuit 15 multiplexes a transmission buffer memory storage quantity BOCS in a transmission buffer memory 17, a control signal (C) based on a control signal C from a coder 200 and a variable length code and the multiplexed signal is sent to a transmission line via a transmission buffer memory 17. A buffer memory 27 of the decoder 200 stores input data in the reception buffer memory 27, a multiplexer/demultiplexer circuit 31 multiplexes/ demultiplexes the data, a subtractor 28 detects a reception buffer memory storage quantity BOCR, an adder 29 calculates a total delay time as BOCR+BOCS, a control circuit 32 outputs control signals a, b based on the quantity of the time to avoid overflow/underflow of the buffer memory 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture coding / decoding apparatus, and more particularly, to an interframe predictive coding for a moving picture signal when the clock for coding the moving picture signal and the clock for decoding the moving picture signal are asynchronous. The present invention relates to a moving picture coding / decoding apparatus capable of highly efficient coding by encoding.

[0002]

2. Description of the Related Art When a moving picture is coded by inter-frame predictive coding, the frequency of occurrence of coded data is not constant when adaptive quantization or entropy coding is used, and the nature of the input image signal varies. Randomly changes with time.

The transmitting side and the receiving side of an encoding apparatus using such an encoding system are provided with buffer memories, respectively, for speed smoothing between the encoding unit and the transmission line, and between the transmission line and the decoding unit. At the same time, the clock is changed.

In this case, it is necessary for the transmission / reception buffer memory to perform the speed conversion without the loss or duplication of the encoded data. If the encoded data is lost or duplicated, a decoding error occurs. Therefore, in the interframe predictive coding, the error continues until the interframe predicted value is refreshed by some method.

Therefore, in the prior art, for example, "Japanese Patent Laid-Open No. 58-58-58"
As described in Japanese Patent Publication No. 59641 ”, in order to prevent loss and duplication of encoded data in the reception buffer memory,
The delay time in the transmission buffer memory was measured, and the reading of the reception buffer memory was controlled so that the total delay time in the transmission and reception buffer memory was constant.

[0006]

The above-mentioned conventional buffer memory control system is established on the premise that the encoding clock and the decoding clock of the input image signal are synchronized with each other. If this premise does not hold, for example, if the decoding clock has a lower clock frequency than the encoding clock, the decoding process will not be in time and the encoded data stored in the receive buffer memory will gradually increase and eventually overflow. However, there is a problem in that a data loss is caused due to the above error and a decoding error occurs.

The object of the present invention is to solve the above-mentioned problems,
Provided is a moving picture coding / decoding device capable of highly efficient coding / decoding of a moving picture signal by inter-frame predictive coding without causing a decoding error even when a clock for coding the moving picture signal and a clock for decoding the moving picture signal are asynchronous. To do.

[0008]

A moving picture coding apparatus according to the present invention efficiently codes moving picture signals by interframe predictive coding and variable length coding, and smoothes coded data generated at random. In addition, in the moving picture coding device having the transmission buffer memory for changing to the clock of the transmission path, the delay time in the transmission buffer memory is detected by using the data storage amount of the transmission buffer memory as an evaluation measure, and every one image frame And the encoding of the signal of one image frame is prohibited each time the control signal provided by the moving picture decoding device based on the total delay time in transmitting and receiving the encoded data is input. .

Further, the moving picture decoding apparatus of the present invention receives the coded data transmitted from the picture coding apparatus via a transmission line, and decodes the coded data into a moving picture signal from a clock of the transmission line. In a moving picture decoding apparatus, which comprises a receiving buffer memory for changing to a clock, and which decodes with a clock asynchronous with the moving picture coding apparatus, a delay time in the receiving buffer memory is set as a data storage amount of the receiving buffer memory. As an evaluation measure, and when the total delay time added to the delay time in the transmission buffer memory of the moving picture coding device exceeds a preset first threshold value, the control signal is set to the moving picture coding. The total delay time supplied to the device is preset to the first
When the second threshold value lower than the threshold value is not reached, the one image frame time decoding process is stopped.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a moving picture coding / decoding apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 10
0 is an encoding device, and reference numeral 200 is a decoding device,
1 illustrates one of a pair of moving picture coding / decoding devices facing each other via a transmission path.

First, the encoding device 100 will be described.

A digital image signal is input to the input terminal 1,
It is supplied to the subtractor 5. In the subtractor 5, the digital image signal is subtracted from the inter-frame prediction value output from the frame memory 10 to generate a prediction error signal.

The prediction error signal is quantized by the quantizer 8 and supplied to the selector 6.

In the selector 6, either the zero ("0") signal or the quantized signal is selected by the control signal (c) of the control circuit 11, and the variable length coding circuit 13 and the adder 12 are selected.
And supplied to.

The adder 12 adds the inter-frame prediction value output from the frame memory 10 to the selected output from the selector 6 to decode the image signal, and writes it in the frame memory 10.

The signal written in the frame memory 10 is supplied to the subtracter 5 and the adder 12 after one frame time delay as the next inter-frame predicted value.

The equal-length code quantized by the quantizer 8 is converted into a variable-length code by the variable-length coding circuit 13 and supplied to the multiplexing circuit 15. In the multiplexing circuit 15, the control signal a supplied from the decoding device 200 and the subtractor 16
Is accumulated in the transmission buffer memory storage amount (BOCS) from (1) to (3), and a flag (F) indicating the head of the frame is added and written to the transmission buffer memory 17.

The multiplexing circuit 15 supplies a write pulse to the write address generation circuit 14, generates a write address to the transmission buffer memory 17 in the write address generation circuit 14, and the encoded data is the transmission buffer memory 17.
Written in.

The transmission line clock is input to the input terminal 3,
The read address generation circuit 18 generates a read address of the transmission buffer memory 17, and the transmission buffer memory 1
The encoded data is read from 7 and is output to the output terminal 4 as transmission encoded data.

The subtracter 16 subtracts the read address from the write address of the transmission buffer memory 17 to obtain the data storage amount (BOC) of the transmission buffer memory 17.
S) is calculated and multiplexed by the multiplexing circuit 15,
It is supplied to the control circuit 7.

The control circuit 7 switches the characteristic of the quantizer 8 according to BOCS to control the amount of generated information, and controls the amount of information accumulated in the transmission buffer memory 17.

The control circuit 11 receives the control signal c from the decoding device 200, gives a control signal (c) for stopping the coding of one image frame time to the selector 6, and the selector 6 outputs a zero signal. Selective output and multiplex circuit 1
5 to stop the multiplexing operation for one image frame time,
Prohibits the generation of transmission coded data.

FIG. 2 shows an operation time chart of the encoding apparatus 100 when the control signal c is received by the control circuit 11.

Next, the decoding device 200 will be described.

Received encoded data is input to the input terminal 22, and based on the transmission path clock from the input terminal 21,
It is written in the reception buffer memory 27 by the write address supplied from the write address generation circuit 26.

The written reception coded data is read by the read address supplied from the read address generation circuit 30 and supplied to the demultiplexing circuit 31.

In the demultiplexing circuit 31, the encoding device 10
Flag F multiplexed with 0, control signal (c), BOC
The multiplexing of S and the encoded data is separated, and the encoded data is supplied to the variable length decoding circuit 33 to be converted / restored into an equal length code and supplied to the adder 34. In the adder 34,
The inter-frame prediction value from the frame memory 36 is added to obtain a decoded signal.

The obtained decoded signal is stored in the frame memory 36.
To the output terminal 23 via the selector 37.
To be output as a decoded image signal. The signal written in the frame memory 36 is delayed by one frame and is added as an inter-frame prediction value for the next frame to the adder 34 and the selector 3.
7 is supplied.

The control signal (c) separated by the demultiplexing circuit 31 is supplied to the control circuit 11 of the encoding device 100 as the control signal c.

The subtractor 28 subtracts the read address from the write address to calculate the storage amount in the reception buffer memory 31, and outputs it as the reception buffer memory storage amount (BOCR) to the adder 29. It is added to the separated transmission buffer memory storage amount (BOCS) and is supplied to the control circuit 32 as the transmission / reception buffer memory total storage amount (BOC) of the data amount stored in the transmission / reception buffer memory.

The control circuit 32 generates the control signal a or b for each decoded frame according to the value of BOC.
In this case, a = 1 is generated when the predetermined BOC value is exceeded, and b = 1 is generated when the BOC value is lower than the predetermined BOC value. When the BOC is within the predetermined range, a = b = 0 is output.

When the control signal b = 1 is generated, the read address generation circuit 30 stops the reading of the reception buffer memory 27, and the selector 37 selectively outputs the output signal of the frame memory 36 to perform the decoding operation. Is delayed by one frame time.

Total amount of transmission / reception buffer memory (BOC)
Corresponds to the total delay time of the transmission / reception buffer memory on a one-to-one basis when the transmission rate is constant. Therefore, by controlling the BOC within a certain range while monitoring the BOC, it is possible to avoid data loss and duplication in the reception buffer memory 27.

As shown in FIG. 3, when the BOC exceeds the total delay time d3 as the first threshold value, the control signal a is generated and the multiplexing circuit 15 of the encoding device 100 is used.
Then, the encoded data of the transmitting unit is thinned out by one frame, and the decoding of the receiving unit of the decoding device 200 is accelerated, and the BOC is used as the second threshold value for the total delay time d2. When the amount becomes less than 1, the control is possible by prohibiting the reading of the reception buffer memory 27 and delaying the decoding in the receiving unit.

3A corresponds to the change in BOC when the frequency of the decoding clock is higher, B corresponds to the change of the frequency when the encoding clock is higher, and d3-d2 corresponds to one frame time. FIG. 3 also shows the maximum value d1 of the delay time of only the transmission unit in the encoding device 100.

Now, the frequency difference between the transmission and reception processing clocks is 100 ppm at maximum, and the maximum delay difference is 1 frame time (33 m
s), at a maximum of about 2.7 minutes, a = 1 or b =
1 occurs, which causes the encoding stop control to be performed in the encoding unit or the read inhibition control of the reception buffer memory in the decoding unit.

In this embodiment, the inter-frame predictive coding circuit 110 and the inter-frame predictive decoding circuit 210 are used.
Although it is a basic circuit, it is obvious that it is also applicable to hybrid coding combined with coding such as orthogonal transform coding and motion compensation interframe predictive coding.

[0039]

As described above, the present invention provides a high-efficiency coding / decoding apparatus based on interframe predictive coding,
While monitoring the total delay amount BOC in the transmission / reception buffer memory, when the BOC exceeds the first threshold value, a control signal is generated, multiplexed by the multiplexing circuit of the encoding unit and transmitted to the transmission unit. Reception is performed by thinning out one frame of coded data from the receiver, speeding up encoding in the receiving unit, and prohibiting reading of the receiving buffer memory and delaying decoding in the receiving unit when the value falls below the second threshold. There is an effect that the overflow and underflow of the buffer memory are avoided, and an error does not occur in the decoded image signal even when the encoding and decoding clocks are asynchronous.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of transmission encoded data in FIG.

FIG. 3 is a diagram showing a transition of a total delay time in the transmission / reception buffer memory of FIG.

[Explanation of symbols]

 1,3,21,22 Input terminal 4,23 Output terminal 5,16,28 Subtractor 6,37 Selector 7,11,32 Control circuit 8 Quantizer 10,36 Frame memory 12,29,34 Adder 13 Variable length coding circuit 14, 26 Write address generation circuit 15 Multiplexing circuit 17 Transmission buffer memory 27 Reception buffer memory 18, 30 Read address generation circuit 31 Multiplexing / separating circuit 33 Variable length decoding circuit 110 Interframe predictive coding circuit 210 Inter-frame predictive decoding circuit 100 Encoding device 200 Decoding device

Claims (2)

[Claims] 1. A transmission buffer memory for high-efficiency coding a moving picture signal by inter-frame predictive coding and variable-length coding, smoothing coded data generated at random, and changing to a clock of a transmission line. In the moving picture coding device having, the delay time in the transmission buffer memory is detected as the data storage amount of the transmission buffer memory as an evaluation scale, and is transmitted for each image frame,
Further, the video encoding device is characterized in that the encoding of the signal of one image frame is prohibited every time the control signal provided based on the total delay time in transmitting and receiving the encoded data from the video decoding device is input. . 2. A reception buffer memory for receiving the encoded data transmitted from the image encoding device via a transmission path and changing the clock of the transmission path to a clock for decoding into a moving image signal. In the moving picture decoding device for decoding with a clock asynchronous with the moving picture coding device, the delay time in the reception buffer memory is detected as a data storage amount of the reception buffer memory as an evaluation measure, and the moving image is detected. When the total delay time added to the delay time in the transmission buffer memory of the image coding apparatus exceeds a preset first threshold value, the control signal is supplied to the moving picture coding apparatus, Is to stop the one-image frame time decoding process when a second threshold value lower than the preset first threshold value has not been reached. Video decoding device.