JPH066194A - Malfunction prevention circuit for electronic device - Google Patents
Malfunction prevention circuit for electronic deviceInfo
- Publication number
- JPH066194A JPH066194A JP4161297A JP16129792A JPH066194A JP H066194 A JPH066194 A JP H066194A JP 4161297 A JP4161297 A JP 4161297A JP 16129792 A JP16129792 A JP 16129792A JP H066194 A JPH066194 A JP H066194A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- diode
- driving
- zener diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 title claims abstract description 16
- 230000002265 prevention Effects 0.000 title claims description 7
- 230000000630 rising effect Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 10
- 238000009499 grossing Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Power Sources (AREA)
- Direct Current Feeding And Distribution (AREA)
- Electronic Switches (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、電源のオン、オフに伴
う電源端子に接続された駆動用(ドライバ用)ICの誤
動作を防止する電子回路の誤動作防止回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction prevention circuit for an electronic circuit which prevents malfunction of a driving (driver) IC connected to a power supply terminal when the power supply is turned on and off.
【0002】[0002]
【従来の技術】一般に電源端子に各種電子回路を接続
し、各種の機能及び動作を備えた回路を構成するが、電
源回路としては、交流電源又は電池等の直流電源を用
い、電源スイッチのオン、オフにより、負荷回路に電源
を供給する。2. Description of the Related Art Generally, various electronic circuits are connected to a power supply terminal to form a circuit having various functions and operations. An AC power supply or a DC power supply such as a battery is used as a power supply circuit and a power switch is turned on. , To supply power to the load circuit.
【0003】この場合、電源スイッチのオン時には、電
源回路に接続した平滑回路等の充放電特性によって、そ
の立上り又は立下り時に方形波状にならず指数関数状の
波形となる。In this case, when the power switch is turned on, due to the charging / discharging characteristics of the smoothing circuit connected to the power circuit, the waveform does not become a square wave but an exponential waveform when rising or falling.
【0004】図5及び図6に示すように駆動用IC(図
中IC)に対して出力側に出力トランジスタ(TR)が
接続されており、これに対して負荷(ZL)に出力電圧
V0を供給するために、上記ICには入力電圧としてVi
が、電源電圧としてV1が加わり、TRには電源電圧と
してV2が加えられている。As shown in FIGS. 5 and 6, an output transistor (TR) is connected to the output side of a driving IC (IC in the drawings), and the output voltage V is applied to a load (Z L ) to this. In order to supply 0 , the above IC has an input voltage of Vi
However, V 1 is added as a power supply voltage, and V 2 is added as a power supply voltage to TR.
【0005】この場合に上記電源電圧V1及びV2は電源
スイッチのオン、オフに伴って図6(イ)(ロ)に示す
ように上昇、下降の曲線となる。ICの入力側には図6
(ハ)に示すパルス電圧が加えられると、電源スイッチ
オン時のt1〜t2期間及び電源スイッチオフ時のt3〜
t4期間にICの出力電圧VA(図6(ニ))に不要な電
圧波形が発生し、これによって図6(ホ)に示す電圧V
0として上記期間にノイズが現われ、正常な入力信号Vi
の期間T1及びT2に相当するパルス以外に余分な電圧が
負荷(ZL)に加わってしまう。In this case, the power supply voltages V 1 and V 2 have curves of rising and falling as shown in FIGS. 6 (a) and 6 (b) as the power switch is turned on and off. Figure 6 on the input side of the IC
When the pulse voltage shown in (c) is applied, the period from t 1 to t 2 when the power switch is turned on and t 3 from when the power switch is turned off
An unnecessary voltage waveform is generated in the output voltage V A of the IC (FIG. 6 (d)) during the period of t 4 , which causes the voltage V V shown in FIG. 6 (e).
Noise appears in the above period as 0 , and the normal input signal Vi
An extra voltage is applied to the load (Z L ) other than the pulses corresponding to the periods T 1 and T 2 of.
【0006】従来例としては、(株)ラジオ技術社発行
の「トランジスタ回路の設計」P.253〜256に示
されている平滑回路があげられ、これらの平滑電圧が図
5に示した電圧V1又はV2として供給される。[0006] As a conventional example, "Transistor circuit design" P.I. The smoothing circuits shown at 253-256 are provided, and these smoothing voltages are supplied as the voltage V 1 or V 2 shown in FIG.
【0007】[0007]
【発明が解決しようとする課題】前述の従来技術では、
電源スイッチのオン及びオフ時に、不要な電圧が負荷に
現われてしまって、負荷が誤動作してしまう欠点があ
り、本発明は上記欠点を除去した新規な電子回路の誤動
作防止回路を提供するものである。In the above-mentioned prior art,
When the power switch is turned on and off, an unnecessary voltage appears in the load and the load malfunctions. The present invention provides a novel electronic circuit malfunction prevention circuit that eliminates the above drawbacks. is there.
【0008】[0008]
【課題を解決するための手段】本発明は、駆動用ICに
接続された第1の直流電源端子、前記駆動用ICの次段
の駆動用トランジスタに接続された第2の直流電源端
子、前記駆動用トランジスタの出力側に接続された出力
トランジスタ、該出力トランジスタの出力側に接続され
た負荷より成り、前記駆動用トランジスタのエミッタと
アース間にツェナーダイオードを接続すると共に前記第
1及び第2の直流電源端子と該ツェナーダイオードとの
間に各々ダイオードを接続し、前記第1及び第2の直流
電源端子に供給される電源のオン、オフ時に上記駆動用
ICの出力端に現われるノイズを除去する構成である。According to the present invention, there is provided a first DC power supply terminal connected to a driving IC, a second DC power supply terminal connected to a driving transistor in the next stage of the driving IC, An output transistor connected to the output side of the driving transistor, and a load connected to the output side of the output transistor. A Zener diode is connected between the emitter of the driving transistor and ground and the first and second A diode is connected between the DC power supply terminal and the Zener diode to eliminate noise appearing at the output end of the driving IC when the power supply to the first and second DC power supply terminals is turned on and off. It is a composition.
【0009】[0009]
【作用】本発明では、電源スイッチのオン、オフ時の電
源電圧の立上り、立下り特性に伴って発生する駆動用I
Cの出力側に現われるノイズによって駆動用トランジス
タ及び出力トランジスタが誤動作するのを電源端子とア
ース間に設けたダイオード及びツェナーダイオードによ
り、駆動用トランジスタのエミッタ電位が所定のツェナ
ー電圧までは駆動用トランジスタがオフを保持するの
で、ノイズ電圧の発生を防止することができる。According to the present invention, the driving I generated due to the rising and falling characteristics of the power supply voltage when the power switch is turned on and off.
The noise appearing on the output side of C causes the driving transistor and the output transistor to malfunction. The diode and Zener diode provided between the power supply terminal and the ground prevent the driving transistor from reaching the predetermined Zener voltage. Since the off state is maintained, the generation of noise voltage can be prevented.
【0010】[0010]
【実施例】図面に従って本発明を説明すると、図1は本
発明の電子機器の誤動作防止回路を示す回路図、図2〜
図4は図1の説明波形図、図5は従来の電子機器の要部
回路図、図6は図5の説明波形図を示す。図面におい
て、(1)は駆動用IC、(2)(3)(4)はバイア
ス抵抗、(5)は駆動用トランジスタ、(6)(7)は
ベース抵抗、(8)(9)は各々第1及び第2の電源端
子、(10)は入力端子、(11)は分圧抵抗(12)
(13)、前記両電源端子に順方向接続したダイオード
(14)(15)、定電圧用のツェナーダイオード(1
6)を有する電圧調整回路、(17)は出力トランジス
タ、(18)は負荷を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a malfunction prevention circuit for electronic equipment of the present invention.
4 is an explanatory waveform diagram of FIG. 1, FIG. 5 is a circuit diagram of a main part of a conventional electronic device, and FIG. 6 is an explanatory waveform diagram of FIG. In the drawing, (1) is a driving IC, (2), (3) and (4) are bias resistors, (5) is a driving transistor, (6) and (7) are base resistors, and (8) and (9) are respectively. First and second power supply terminals, (10) is an input terminal, (11) is a voltage dividing resistor (12)
(13), diodes (14) and (15) connected in the forward direction to both power supply terminals, and a zener diode (1 for constant voltage
6 is a voltage regulator circuit, 17 is an output transistor, and 18 is a load.
【0011】次に本発明回路の動作について説明する
と、駆動用IC(1)の電源端子(8)には図2(イ)
に示す電源電圧V1が加わり、電源スイッチのオン、オ
フによってタイミングt0及びt3で各々電圧は立上り又
は立下がる。このとき前記IC(1)の入力端子(1
0)には図2(ハ)に示す入力信号が加わる。Next, the operation of the circuit of the present invention will be described. The power supply terminal (8) of the driving IC (1) is shown in FIG.
Applied power supply voltages V 1 shown in, on the power switch, each voltage falls rising or falling timing t 0 and t 3 by off. At this time, the input terminal (1
The input signal shown in FIG. 2C is added to 0).
【0012】ここで前記IC(1)は一般にオープンコ
レクタタイプの駆動用のICで、抵抗(2)(3)
(4)は該IC(1)の出力信号を次段の駆動用トラン
ジスタ(5)のベースに伝達するように該駆動用トラン
ジスタ(5)のベース電流(IB)及びベース電圧
(VB)を供給するためのバイアス抵抗であり、駆動用
トランジスタ(5)は出力トランジスタ(17)を駆動
する。駆動用トランジスタ(5)のエミッタはツェナー
ダイオード(16)によって所定電圧(VDZ)に保持さ
れる構成となっている。The IC (1) is generally an open collector type driving IC and has resistors (2) and (3).
(4) The next stage of the driving transistor to the output signal of the IC (1) (5) the base current of the driving transistor so as to transmit to the base (5) of (I B) and the base voltage (V B) Is a bias resistor for supplying the drive transistor (5) to drive the output transistor (17). The emitter of the driving transistor (5) is held at a predetermined voltage (V DZ ) by the Zener diode (16).
【0013】今電子機器本体の電源供給用の電源スイッ
チ(図示せず)がオンになり、図2(イ)及び(ロ)に
示す通り、タイミングt0でV1及びV2が立上ったとす
ると、抵抗(12)及びダイオード(14)、抵抗(1
3)及びダイオード(15)を介してV1又はV2の追随
速度の早い方の電圧によって駆動用トランジスタ(5)
のエミッタ電位は上昇し、ツェナーダイオード(16)
のツェナー電圧(VDZ)に達する。(タイミングt1) このとき駆動用IC(1)の出力は、その最低動作電圧
に達するまで、ハイインピーダンスとなるため、前記電
源端子(8)の立上りと同期して、駆動用ICの入力電
圧Vi(図2(ハ))に対して、その出力電圧VAは図2
(ニ)に示すようにノイズが期間T1に発生する。とこ
ろが、前記電圧VAに対して、駆動用トランジスタ
(5)のベース・エミッタ間電圧(VEB)は VEB=VB0−VZ となり、VB0=VZとなるまで逆バイアスが加わること
になる。(VB0は駆動用トランジスタのベース電圧、V
Zはツェナーダイオード(16)に加わる電圧)そこで
VB0=VZのときに前記電圧VEBはVEB=0となって、
このときまでは駆動用トランジスタ(5)はオンしな
い。Now, a power switch (not shown) for supplying power to the electronic apparatus main body is turned on, and V 1 and V 2 rise at timing t 0 as shown in FIGS. 2A and 2B. Then, the resistance (12) and the diode (14), the resistance (1
3) and the driving transistor (5) via the diode (15) by the voltage having the faster following speed of V 1 or V 2.
Emitter potential rises and Zener diode (16)
Zener voltage (V DZ ) is reached. (Timing t 1 ) At this time, the output of the driving IC (1) becomes high impedance until it reaches the minimum operating voltage. Therefore, the input voltage of the driving IC is synchronized with the rise of the power supply terminal (8). The output voltage V A for Vi (FIG. 2C) is shown in FIG.
As shown in (d), noise is generated in the period T 1 . However, with respect to the voltage V A , the base-emitter voltage (V EB ) of the driving transistor (5) becomes V EB = V B0 -V Z , and a reverse bias is applied until V B0 = V Z. become. (V B0 is the base voltage of the driving transistor, V
Z is the voltage applied to the Zener diode (16). Therefore, when V B0 = V Z , the voltage V EB becomes V EB = 0,
Until this time, the driving transistor (5) is not turned on.
【0014】また駆動用トランジスタ(5)の電圧VB0
はV1より高くなることはないために、期間T1の間はV
EB≦0に保持されているので、駆動用IC(1)の動作
保証電圧値を超えるまで、駆動用トランジスタ(5)は
動作しない。その模様を拡大して図3(イ)〜(ロ)に
示してあり、図3(ロ)に示す通り、駆動用トランジス
タ(5)は期間(TP)の間強制的にオフに保たれる。Further, the voltage V B0 of the driving transistor (5)
Is never higher than V 1 , so V is maintained during the period T 1.
Since EB ≦ 0, the driving transistor (5) does not operate until the operation guarantee voltage value of the driving IC (1) is exceeded. The pattern is enlarged and shown in FIGS. 3A to 3B. As shown in FIG. 3B, the driving transistor (5) is forcibly kept off during the period (T P ). Be done.
【0015】従って出力トランジスタ(17)は、上記
期間(TP)はオフに保持されるので、図2(ニ)に示
される期間T1に生じたノイズによる誤動作は未然に防
止できる。Therefore, since the output transistor (17) is kept off during the period (T P ) described above, malfunction due to noise generated during the period T 1 shown in FIG. 2D can be prevented.
【0016】一方電源スイッチをオフにしたときには、
図2のタイミングt3から、電源端子(8)(9)の電
圧V1及びV2は、図2(イ)(ロ)に示すように徐々に
下がる。On the other hand, when the power switch is turned off,
From timing t 3 of FIG. 2, the voltages V 1 and V 2 of the power supply terminals (8) and (9) gradually decrease as shown in FIGS.
【0017】このとき駆動用IC(1)がハイインピー
ダンスになる期間(T2)より、出力トランジスタ(1
7)のオフの期間が長くなるため、図4に示す特性か
ら、図4(ロ)の期間(T3)、駆動用トランジスタ
(5)は強制的にオフになって、駆動用トランジスタ
(5)のコレクタ電圧(Vc)が正電圧になり、出力ト
ランジスタ(17)はオフになって期間T2に生じるノ
イズによる出力トランジスタ(17)の誤動作は発生し
ない。At this time, from the period (T 2 ) in which the driving IC (1) has a high impedance, the output transistor (1
Since the OFF period of 7) becomes long, the driving transistor (5) is forcibly turned OFF during the period (T 3 ) of FIG. 4B from the characteristics shown in FIG. The collector voltage (V c ) of () becomes a positive voltage, the output transistor (17) is turned off, and the malfunction of the output transistor (17) due to the noise generated in the period T 2 does not occur.
【0018】以上の説明から分るように負荷(18)に
は図2(ホ)に示す出力電圧V0が加わり、従来生じて
いた誤動作は防止できる。As can be seen from the above description, the output voltage V 0 shown in FIG. 2 (E) is applied to the load (18), and the malfunction that has conventionally occurred can be prevented.
【0019】[0019]
【発明の効果】本発明の電子機器の誤動作防止回路によ
れば、従来電源スイッチのオン、オフに伴って電源電圧
が変化し、この際に生じるノイズによって、負荷に対
し、ノイズが加わり、負荷が誤動作していたのを、駆動
用トランジスタ、ツェナーダイオード及びダイオードを
接続した構成で、出力トランジスタを前記ノイズの期間
出力トランジスタを強制的にオフに設定できるので、出
力トランジスタの誤動作は未然に防止し得る。According to the malfunction prevention circuit for an electronic device of the present invention, the power supply voltage changes according to the conventional power switch being turned on and off, and noise generated at this time causes noise to be added to the load. Was malfunctioning because the output transistor can be forcibly set to off during the noise period by connecting the drive transistor, Zener diode, and diode, preventing malfunction of the output transistor. obtain.
【図1】本発明回路を示す回路図である。FIG. 1 is a circuit diagram showing a circuit of the present invention.
【図2】図1の動作を説明するための特性図である。FIG. 2 is a characteristic diagram for explaining the operation of FIG.
【図3】図1における電源スイッチ・オン時の説明のた
めの詳細特性図である。FIG. 3 is a detailed characteristic diagram for explaining when the power switch is turned on in FIG.
【図4】図1における電源スイッチ・オフ時の説明のた
めの詳細特性図である。FIG. 4 is a detailed characteristic diagram for explanation when the power switch is turned off in FIG.
【図5】従来の電子機器の要部回路図である。FIG. 5 is a circuit diagram of a main part of a conventional electronic device.
【図6】図5の説明のための特性図である。FIG. 6 is a characteristic diagram for explaining FIG.
(1) 駆動用IC (5) 駆動用トランジスタ (8) 第1の電源端子 (9) 第2の電源端子 (10) 入力端子 (11) 電圧調整回路 (16) ツェナーダイオード (17) 出力トランジスタ (18) 負荷 (1) Driving IC (5) Driving transistor (8) First power supply terminal (9) Second power supply terminal (10) Input terminal (11) Voltage adjustment circuit (16) Zener diode (17) Output transistor ( 18) Load
Claims (2)
動用ICの出力側にベースが接続された駆動用トランジ
スタ、該駆動用トランジスタの出力側に接続された負荷
回路とより構成され、該駆動用トランジスタのエミッタ
とアース間にツェナーダイオードを接続すると共に該ツ
ェナーダイオードの一端と第1及び第2の電源端子との
間に各々ダイオードを接続し、電源のオン、オフ時に上
記駆動用ICの出力側に発生するノイズを除去すること
を特徴とした電子機器の誤動作防止回路。1. A driving IC to which an input signal is applied, a driving transistor whose base is connected to the output side of the driving IC, and a load circuit connected to the output side of the driving transistor, A Zener diode is connected between the emitter of the driving transistor and the ground, and diodes are respectively connected between one end of the Zener diode and the first and second power supply terminals, so that the driving IC is turned on and off. A malfunction prevention circuit for electronic equipment, which eliminates noise generated on the output side of the.
ナーダイオードの一端との間に各々抵抗及び順方向接続
されたダイオードより成る直列回路を接続したことを特
徴とする請求項1記載の電子機器の誤動作防止回路。2. A series circuit including a resistor and a diode connected in a forward direction is connected between the first and second power supply terminals and one end of the Zener diode, respectively. Malfunction prevention circuit for electronic devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4161297A JPH066194A (en) | 1992-06-19 | 1992-06-19 | Malfunction prevention circuit for electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4161297A JPH066194A (en) | 1992-06-19 | 1992-06-19 | Malfunction prevention circuit for electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH066194A true JPH066194A (en) | 1994-01-14 |
Family
ID=15732436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4161297A Pending JPH066194A (en) | 1992-06-19 | 1992-06-19 | Malfunction prevention circuit for electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH066194A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014017285A1 (en) * | 2012-07-27 | 2014-01-30 | イーグル工業株式会社 | Stern tube sealing device |
-
1992
- 1992-06-19 JP JP4161297A patent/JPH066194A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014017285A1 (en) * | 2012-07-27 | 2014-01-30 | イーグル工業株式会社 | Stern tube sealing device |
| US9868502B2 (en) | 2012-07-27 | 2018-01-16 | Eagle Industry Co., Ltd. | Stern tube sealing device |
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