JPH06326726A - ATM cell processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] An AT that realizes parallel expansion processing of N-byte units of ATM cell data with a simple circuit and performs low-speed signal processing.
An object is to obtain an M cell processing device. [Structure] From N-byte parallel input ATM cell data to H
A format conversion circuit that deletes 1 byte of the EC area and inserts a stuff byte in every N cell cycle to output N bytes in parallel, and a header processing circuit that receives this output and processes the data of the header in N bytes in parallel Or a payload processing unit that receives the output of the format conversion circuit and processes the data of the payload unit in N bytes in parallel. Further, the HEC is deleted from the N-byte parallel input data, the stuff byte is inserted every N cell cycle and the N byte parallel output is performed, and the stuff byte is inserted every N cell cycle by changing the clock. And a second format conversion circuit for inserting HEC and OH bytes in N-byte parallel data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell processing device in an ATM cell processing device.

[0002]

2. Description of the Related Art FIG. 11 shows an ATM to which a conventional ATM cell processing method shown in, for example, the 1991 IEICE Spring National Convention Lecture Paper B-706 "Construction Method of ATM Cell Terminator" is applied. It is a cell processing receiver circuit. In the figure, 102 is a cell synchronization circuit, 104 is an error correction circuit, and 105 is a descramble circuit. 7 is 8 parallel ATM cell reception data which is 8 parallelized in byte units, 8
Is a reception clock synchronized with 8 parallel ATM cell reception data 7. Reference numeral 115 is a speed matching circuit, 119 is a system clock, 124 is 8 parallel data in which cell synchronization is established in the cell synchronization circuit 102, 125 is 8 parallel data in which the header portion of the 8 column data 124 is error-corrected in the error correction circuit 4. , 126 are 8-parallel data obtained by descrambled 8-parallel data 125 in which the information payload part is scrambled in the descramble circuit 105,
127 is 8 parallel data 12 in the speed matching circuit 115.
It is 8 parallel data in which 6 speed matching is performed. Reference numeral 128 is a delay circuit that constitutes the cell synchronization circuit 102, 129 is an HEC arithmetic circuit, and 130 is a synchronization protection circuit.
Reference numeral 31 is an HEC calculation result calculated by the HEC calculation circuit 129, reference numeral 132 is an error correction circuit constituting the error correction circuit 104, and reference numeral 133 is an error calculation circuit.

Next, the operation will be described. The ATM cell reception data 7 of 8 parallels, which are parallelized in units of 8 bytes, are input to the cell synchronization circuit 102 using the synchronized reception clock 8 as a timing signal. The HEC arithmetic circuit 129 is
The CRC of 4 bytes of the header is calculated, the result is compared with the HEC byte of the 5th byte, and the HEC calculation is performed.
The head of the cell is determined from the calculation result, and a coincidence pulse is generated. The synchronization protection circuit 130 receives the coincidence pulse from the HEC calculation circuit 129 and establishes synchronization based on the specified number of protection stages. Further, the delay circuit 128 is composed of 8 parallel ATs.
The M cell reception data 7 is delayed.

The 8-parallel data 124 for which cell synchronization is established in the cell synchronization circuit 102 and the HEC calculation result 131 calculated by the HEC calculation circuit 129 are the error correction circuit 10
4 is input. The error calculation circuit 133 uses the HEC calculation result 131 calculated by the HEC calculation circuit 129 to detect a 1-bit error and a 2-bit or more error in the header part. The error correction circuit 132 performs 1-bit error correction on the header part. Eight parallel data 1 in which the error correction circuit 104 has performed error correction on the header portion of the eight-column data 124.
25 is input to the descramble circuit 105.

The descramble circuit 105 descrambles the 8-parallel data 125 in which the information payload part is scrambled, and the descrambled 8-parallel data 126 is input to the speed matching circuit 115. FI
The speed matching circuit 115 composed of FO or the like performs speed matching such as transfer of the 8 parallel data 125 synchronized with the reception clock 8 to the system clock, insertion / extraction of idle cells, and cell length conversion, and the like. Is output.

FIG. 12 is a block diagram of a conventional ATM cell format conversion system disclosed in Japanese Patent Laid-Open No. 4-291855, a block diagram of the conversion means, and an explanatory diagram of input / output signals. In the figure, 142 is an exchange switch, 14
Reference numeral 3 is an input format conversion means and 144 is an output format conversion means. Further, details of the input format conversion means 143 are shown in FIG. 12 (b), and are composed of the following elements. That is, 145 is a speed matching circuit, specifically, a FIFO buffer memory, 146 is a serial / parallel conversion circuit, and 147 is a gate circuit that creates a write clock for the FIFO buffer. This operation is as follows. 53-byte ATM input by 8-byte parallel signal
When the cell is written to the FIFO buffer 145,
As shown in FIG. 12C, the clock is stopped so that the input fifth byte is not written in the buffer 145, and as a result, the read data becomes 52 bytes. If you want to use 2 bytes in parallel as shown in the figure, this output is
The parallel conversion circuit 146 parallelizes it in units of 2 bytes and outputs it to the exchange switch.

[0007]

Since the ATM cell processing device to which the conventional ATM cell format conversion system is applied is constructed as described above, it is necessary to process the ATM cells by 8 bytes in 1-byte units. It was necessary to perform parallel processing. This means that when the interface speed becomes high, the data signal processing speed also becomes high, and there is a problem that the circuit design becomes disadvantageous or difficult. The same applies to the input format conversion means used in the conventional ATM exchange described above.

The present invention has been made in order to solve the above problems, and an ATM cell for performing format conversion or speed conversion while maintaining the input synchronization and keeping the ATM cell data format of parallel input of a plurality of bytes. The purpose is to obtain a processing device.

[0009]

An ATM cell processing device according to the present invention deletes 1 byte of HEC area from N byte (N is an integer of 2 or more) parallel input ATM cell data, and at every N cell cycle. A format conversion circuit that inserts stuff bytes and outputs N bytes in parallel, a header processing circuit that receives the output of this format conversion circuit and processes the data of the header in parallel in N bytes, or a payload that receives the output of the format conversion circuit And a payload processing unit for processing N bytes of data in parallel. The ATM cell processing device according to the invention of claim 2 deletes 1 byte of the HEC area from N byte parallel input ATM cell data, and inserts the first stuff byte for every N cell period to output N bytes in parallel. A first format conversion circuit, a speed matching circuit that receives the output of this format conversion circuit, performs speed conversion by changing clocks, inserts a second stuff byte every N cell cycles, and outputs N bytes in parallel, and Receives this speed matching circuit output and outputs 1 in N bytes of parallel data.
A second format conversion circuit for inserting an HEC byte and an OH (overhead) byte for each cell is provided.

The ATM cell processing device according to the invention of claim 3 is
The header processing part or the payload processing part for processing the header part data or the payload part data of the N-byte parallel input in parallel with the N-byte parallel ATM cell data is input, and the HEC area 1 byte is added to the necessary part. A format conversion circuit that sequentially inserts and outputs N bytes in parallel and a multiplexing circuit that receives the output of this format conversion circuit and converts it to 1-byte parallel data are provided. Further, the ATM cell processing device according to the invention of claim 4 is arranged such that NEC byte parallel input ATM cell data is converted into HEC area 1 byte, OH1
A first format conversion circuit that deletes bytes, inserts first and second stuff bytes every N cell cycles and outputs N bytes in parallel, and receives the output of this format conversion circuit to change the clock and change the speed. A speed matching circuit that converts and deletes the stuff byte every N cell cycles and outputs N bytes in parallel, and receives the output of this speed matching circuit, and inserts HEC bytes and OH bytes into N bytes parallel data for each cell. And a second format conversion circuit.

[0011]

In the ATM cell processing device according to the present invention, 1 byte of HEC byte is sequentially deleted from N-byte parallel input data, a stuff byte is inserted, and the N-byte parallel data is kept as it is for synchronization. Sent to the processing circuit. In addition to the above, the ATM cell processing device according to claim 2 performs speed conversion with the stuff byte inserted and N-byte parallel data remains unchanged, and the stuff byte is deleted from the converted N-byte parallel data. OH byte and HEC byte are inserted. The ATM cell processing device of claim 3 performs the reverse processing of the device of claim 1. That is, the stuff bytes of N bytes of parallel input data are deleted,
One HEC byte is inserted in order. The AT of claim 4
The M cell processing device performs the reverse processing of the device of claim 2. That is, 1 byte of OH and 1 byte of HEC are deleted, a stuff byte is inserted, speed conversion is performed with the N byte parallel data as it is, the stuff byte is deleted from the converted N byte parallel data, and HEC is added to necessary parts. Bytes are inserted.

[0012]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of the present embodiment, and FIG. 2 is a waveform chart of each part for explaining the operation of the present embodiment. In the figure, 1 is an 8-32 DMUX circuit, 2 is a cell synchronization circuit, 3
Is a format conversion circuit, 4 is an error correction circuit, 5 is a descrambling circuit, and 6 is a 1/4 frequency dividing circuit. Also, 7
Is 8 parallel ATM cell reception data that is parallelized in 8 bytes, 8 is a reception clock that is synchronized with 8 parallel ATM cell reception data 7, and 9 is 8 parallel ATM cell reception data 7 in the 8-32DMUX circuit 1. 32 parallel data demultiplexed by 1 to 4 and 10 are 1/4 divided clocks obtained by dividing the received clock 8 by 1/4 in the 1/4 divider circuit 6. Reference numeral 11 denotes 32 parallel data in which cell synchronization is established in the cell synchronization circuit 2, 12 is 32 parallel data in which format conversion of 32 parallel data 11 is performed in the format conversion circuit 3, and 13 is a header portion of 32 parallel data 12 in the error correction circuit 4. 32 parallel data with error correction, 1
Reference numeral 4 denotes 32 parallel data obtained by descrambled 32 parallel data 12 in which the information payload part is scrambled in the descramble circuit 5.

Next, the operation will be described with reference to FIGS. The ATM cell reception data 7 of 8 parallels, which are parallelized in units of 8 bytes, are input to the 8-32 DMUX circuit 1 by using the synchronized reception clock 8 as a timing signal. 8-
The 32DMUX circuit 1 demultiplexes 8-parallel ATM cell reception data 7 by 1: 4. In the 8-32 DMUX circuit 1, the 32 parallel data 9 demultiplexed by 1: 4 is input to the cell synchronization circuit 2. In addition, the 1/4 frequency divider circuit 6
The reception clock 8 is divided by 1/4 to generate a 1/4 divided clock 10 synchronized with the 32 parallel data 9. The cell synchronization circuit 2 performs a CRC operation on the 4-byte header, compares the result with the HEC byte of the fifth byte, and performs an HEC operation to establish synchronization.

The 32 parallel data 11 for which cell synchronization has been established in the cell synchronization circuit 2 are input to the format conversion circuit 3. As shown in FIG. 2 (c), the format conversion circuit 3 deletes unnecessary HEC bytes after the HEC operation, and the ATM cell data of 53 bytes has a total of 52 bytes including a header of 4 bytes and an information payload of 48 bytes. Convert to. Furthermore, in every 4 cell cycles, 4 bytes of stuff bytes are inserted into 4 bytes of the deleted HEC bytes, and the clock cycle of the 1/4 divided clock 10 and ATM
The format conversion of the 32 parallel data 11 in which the cell synchronization is established is performed so that the boundary between the cell and the ATM cell and the boundary between the header and the information payload match.

The 32 parallel data 11 subjected to format conversion in the format conversion circuit 3 is input to the error correction circuit 4, which is the processing of the header section. The error correction circuit 4 corrects a 1-bit error in the header part and detects an error of 2 bits or more from the HEC operation result. The 32 parallel data 13 obtained by error-correcting the header portion of the 32-column data 12 in the error correction circuit 4 is input to the descramble circuit 5, which is the processing of the payload portion. The descramble circuit 5 descrambles 32 parallel data 13 in which the information payload part is scrambled,
The descrambled 32 parallel data 14 is output. As described above, the 4-byte signal after 8-32DMUX is synchronized and thereafter all 4-byte parallel processing is input to the next processing circuit, so that low-speed processing is possible.

Example 2. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a configuration diagram of the present embodiment, and FIGS. 4 and 5 are waveform diagrams of respective parts for explaining the operation of the present embodiment. In the figure, 1 is an 8-32 DMUX circuit, 3 is a format conversion circuit, and 6 is a 1/4 frequency dividing circuit. Reference numeral 7 is an 8-parallel ATM cell reception data which is parallelized in byte units, 8 is a reception clock synchronized with the 8-parallel ATM cell reception data 7, and 9 is 8-parallel ATM cell reception data 7 in the 8-32DMUX circuit 1. 1 to 4 demultiplexed 32
Parallel data, 10 is a 1/4 frequency-divided clock obtained by dividing the reception clock 8 by 1/4 in the 1/4 frequency dividing circuit 6, and 12 is 32 parallel data obtained by format-converting the 32 parallel data 9 in the format conversion circuit 3. . 15 is a speed matching circuit, 16 is a format conversion circuit, 17 is 32-8
The MUX circuit, 18 is a quarter frequency divider circuit. Reference numeral 19 is a system clock, 20 is a quarter divided clock obtained by dividing the system clock 19 by a quarter in the quarter divider circuit 18, and 21 is 32 parallel data 1 in the speed matching circuit 15.
32 parallel data that has been subjected to speed matching of 2; 22 is 32 parallel data obtained by format conversion of 32 parallel data 21 in the format conversion circuit 16; and 23 is 32-8 MUX.
It is 8 parallel data in which 32 parallel data 22 are multiplexed 4 to 1 by the circuit 17.

Next, the operation will be described with reference to FIGS. The ATM cell reception data 7 of 8 parallels, which are parallelized in units of 8 bytes, are input to the 8-32 DMUX circuit 1 using the synchronized reception clock 8 as a timing signal (FIG. 4B). The 8-32DMUX circuit 1 has eight parallel ATs.
The M cell reception data 7 is demultiplexed by 1: 4. 8-32D
In the MUX circuit 1, the 32 parallel data 9 demultiplexed by 1: 4 is input to the format conversion circuit 3. Further, the 1/4 frequency dividing circuit 6 frequency-divides the reception clock 8 by 1/4 and synchronizes with the 32 parallel data 9 1/4 frequency-dividing clock 1
Generates 0.

The format conversion circuit 3 deletes the HEC byte and converts the ATM cell data of 53 bytes into a total of 52 bytes including 4 bytes of header and 48 bytes of information payload. Furthermore, the HE that has been deleted every four cell cycles
Insert 4 stuff bytes for 4 bytes for C byte, and set the clock cycle of 1/4 divided clock 10 and AT
Format conversion of the 32 parallel data 11 in which cell synchronization is established is performed so that the boundary between the M cell and the ATM cell and the boundary between the header and the information payload match (see FIG. 4).
(C)).

The 32 parallel data 9 whose format is converted by the format conversion circuit 3 is input to the speed matching circuit 15. Further, the 1/4 frequency dividing circuit 18 frequency-divides the system clock 19 by 1/4 to generate a 1/4 frequency-divided clock 20. The speed matching circuit 15 uses the 1/4 frequency-divided clock 10
The 32 column data 12 synchronized with the above is subjected to speed matching such as transfer to the system clock, insertion / extraction of idle cells, cell length conversion, etc., and 32 parallel data 21 is output. Regarding cell length conversion, as shown in FIG.
When adding 1 byte of OH (overhead) to an ATM cell with a byte structure and converting the cell length to an ATM cell with a 54-byte structure, insert 4 bytes of stuff bytes into the added 4 bytes of OH every 4 cell cycles. The format is output from the speed matching circuit 15.

In the format conversion circuit 16, the above 32
For the input of the parallel data 21, the stuff bytes 4 bytes for HEC and the stuff bytes 4 bytes for OH, which were inserted every 4 cell cycles, are deleted, and instead, 1 HEC byte and 1 OH byte each cell cycle are deleted. Insert
The format is converted into ATM cell data of 32 parallel continuous 54 bytes (FIG. 5 (e)). The 32 parallel data 22 subjected to the format conversion in the format conversion circuit 16 is input to the 32-8 MUX circuit 17. 32
The -8 MUX circuit 17 multiplexes 32 parallel data 22 by 4 to 1, and outputs 8 parallel continuous ATM cell data 23 of 54 bytes.

Example 3. Still another embodiment of the present invention will be described. FIG. 6 is a configuration diagram thereof, and FIG. 7 is a waveform chart of each part for explaining its operation. In the figure, 41 is a scramble circuit, 42 is a 1/4 frequency divider circuit, 43 is an HEC generation circuit, 44 is a format conversion circuit which is a main element of the present invention, and 45 is a 32-8 MUX circuit. 51 is the input 3
Two-bit parallel data, 52 is a transmission clock, and 53 is 32 parallel data before the format shown in FIG. 7A in which a stuff byte is inserted every 4 cells, for example. 54
Is 32-bit parallel data after format conversion, and 55 is, for example, transmission data.

This operation is for performing an inverse conversion from the configuration of FIG. 1, and is used for processing the transmission data, for example. That is,
The 32-bit parallel data receives the processing of the header or payload signal section in parallel with 4 bytes and is input to the format conversion section 44. In the format conversion unit 44, as shown in FIG. 7B, the stuff byte is deleted and the HE
The HEC data from the C generation circuit 43 is inserted into the predetermined position of the cell byte by byte. Finally, in the 32-8 multiplexer 45, 8-bit transmission data is obtained as shown in FIG. 7 (c).

Example 4. Still another embodiment of the present invention will be described. FIG. 8 is a configuration diagram thereof, and FIGS. 9 and 10 are waveform diagrams of respective parts for explaining the operation thereof. In the figure, 61 is 8
-32DMUX circuit, 62 frequency division circuit, 63 first format conversion circuit, 64 speed matching circuit, 65
Is a second format conversion circuit, 66 is a 1/4 frequency dividing circuit, and 67 is a 32-8 MUX circuit. 71 is 8-bit parallel input data, 72 is a system clock, 73 is 32-bit parallel data demultiplexed by 4 to 1, 74 is a clock obtained by dividing the system colock by 1/4, and 75 is a signal after the first format conversion, for example, It is a 32-bit parallel data of 54 bytes per cell. Reference numeral 76 is 32-byte parallel data of 53 bytes per cell after speed matching, 77 is 32-bit parallel data after the second format conversion, 78 is a transmission clock, 79 is a transmission clock divided by 1/4, and 80 is 8 It is bit transmission data.

This operation is for performing the inverse conversion from the configuration of FIG. 3, and is used for processing the transmission data, for example. Ie 8
The input data of bit is 3 bytes of 4 bytes shown in FIG. 9 (b).
The 2-bit parallel data is input to the first format conversion circuit 63. This output becomes 32-bit parallel data in which the individual OH and HEC bytes are deleted and 2 stuff bytes are inserted every 4 cell cycles, as shown in FIG. 9C. Further, the number of bytes of one cell is reduced, and the clock is changed to become the 32-bit parallel data of FIG. This data enters the second format conversion circuit 65 and becomes the 32-bit parallel data of FIG. Finally, the 32-8 MUX circuit 67 forms the multiplexed transmission data 80.

[0025]

The ATM cell processing device according to the present invention is
N to process and convert multiple N-byte parallel inputs as a unit
Since the byte processing circuit, the N-byte format conversion circuit, or the N-byte speed matching circuit is provided, it is not necessary to return to the processing circuit in units of 8 bytes, the processing circuit is simple, and the circuit element for low speed can be used. effective.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a cell processing receiving circuit of an ATM cell processing device according to an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the ATM cell processing receiving circuit of FIG.

FIG. 3 is a configuration diagram of a cell processing receiving circuit of an ATM cell processing device according to another embodiment of the present invention.

FIG. 4 is a timing diagram illustrating an operation of the ATM cell processing receiving circuit of FIG.

FIG. 5: A to which a conventional ATM cell processing method is applied
It is a block diagram of a TM cell processing receiver circuit.

FIG. 6 is a configuration diagram of an ATM cell transmission processing circuit according to the embodiment of the present invention.

7 is a timing diagram illustrating an operation of the ATM cell transmission circuit of FIG.

FIG. 8 is a configuration diagram of an ATM cell transmission processing circuit according to another embodiment of the present invention.

9 is a timing diagram illustrating the operation of the ATM cell transmission circuit of FIG.

10 is a timing diagram illustrating an operation of the ATM cell transmission circuit of FIG.

FIG. 11 is a block diagram of a conventional ATM cell processing receiving circuit.

FIG. 12 is a diagram for explaining the configuration and operation of a conventional ATM switch and input format conversion means.

[Explanation of symbols]

 1 8-32 DMUX circuit 2 Cell synchronization circuit 3 Format conversion circuit 4 Error correction circuit 5 Descramble circuit 6 1/4 frequency divider circuit 15 Speed matching circuit 16 Format conversion circuit 17 32-8 MUX circuit 18 1/4 frequency divider circuit 41 Scrambler Circuit 42 1/4 frequency divider circuit 43 HEC generation circuit 44 Format conversion circuit 45 32-8 MUX circuit 61 8-32 DMUX circuit 62 1/4 frequency divider circuit 63 Format conversion circuit 64 Speed matching circuit 65 Format conversion circuit 66 1/4 minute Circular circuit 67 32-8 MUX circuit

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[Procedure amendment]

[Submission date] August 27, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

The present invention solves the above problems.
This was done for the purpose of converting ATM cell data into multiple bytes.
Format data is converted as it is in parallel data, and ATM cells are converted.
Simple parallel expansion processing of multiple bytes for data
ATM circuit that can be realized by a circuit and can reduce the signal processing speed
The purpose is to obtain a processing device.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

[0025]

The ATM cell processing device according to the present invention is
N to process and convert multiple N-byte parallel inputs as a unit
Since a byte processing circuit, N-byte format conversion circuit, or N-byte speed matching circuit is provided ,
8 parallel processing circuit is unnecessary, the processing circuit is simple,
Further, there is an effect that it can be constituted by a circuit element for low speed.

Claims (4)

[Claims] 1. N bytes (N is an integer of 2 or more) 1 byte of HEC area is deleted from ATM cell data of parallel input,
And a format conversion circuit that inserts a stuff byte every N cell cycles and outputs N bytes in parallel, and a header processing circuit that receives at least the output of the format conversion circuit and processes the data of the header in N bytes in parallel, or An ATM cell processing device comprising a payload processing unit which receives the output of the format conversion circuit and processes the data of the payload unit in N bytes in parallel. 2. One byte of HEC area is deleted from ATM cell data of N bytes (N is an integer of 2 or more) parallel input,
And insert the first stuff byte every N cell cycles,
A first format conversion circuit that outputs N bytes in parallel and the output of the above format conversion circuit are received, speed conversion is performed by changing clocks, a second stuff byte is inserted every N cell cycle, and N bytes are output in parallel. An AT including a speed matching circuit and a second format conversion circuit which receives the output of the speed matching circuit and inserts an HEC byte and an OH (overhead) byte into each cell in N-byte parallel data.
M cell processing device. 3. A header processing unit or payload processing unit for processing at least N bytes (N is an integer of 2 or more) parallel input header data or payload data in N bytes in parallel, and said N bytes parallel ATM A format conversion circuit that receives cell data as an input, sequentially inserts 1 byte of HEC area into a necessary portion, and outputs N bytes in parallel, and a multiplexing circuit that receives the output of the format conversion circuit and converts it into 1-byte parallel data ATM cell processing device. 4. N bytes (N is an integer of 2 or more) parallel input ATM cell data to HEC area 1 byte, OH
(Overhead) A first format conversion circuit that deletes one byte and inserts first and second stuff bytes every N cell cycles and outputs N bytes in parallel; To convert the speed, and delete the stuff byte every N cell cycles to output N bytes in parallel and the speed matching circuit output to receive the HEC for each cell in the N bytes parallel data. An ATM cell processing device having a second format conversion circuit for inserting bytes and OH bytes.