JPH06275067A - Serial/random access switching circuit - Google Patents

Abstract

PURPOSE:To suppress a random access end waiting time required before serial access by providing an arbiter circuit and mediating the switch of access. CONSTITUTION:The switches 8, 9 are connected to the contacts B by the arbiter circuit 12 where random access request R-REQ becomes 1, and random address R-AD is supplied to a DRAM controller 10, and a dual port DRAM 11 is random accessed. On the other hand, when serial access request S-REQ becomes 1, the switches 8, 9 are switched to the contacts A sides through the circuit 12 after the random access is ended, and the random access end waiting time is suppressed minimally, and the serial access is performed, and then, the throughput of the random access side is enhanced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a serial / random access switching circuit.

[0002]

2. Description of the Related Art In a conventional serial / random access switching circuit for a dual port DRAM, it is common to switch between serial access and random access by a configuration as shown in FIG. That is, the address signal (S AD) and the address signal (R A
Switch 8 for switching D) and the serial access request signal (S REQ) and random access request signal (R
A switch 9 for switching REQ) is provided, and switching of these switches is performed using the horizontal synchronizing signal (HD) of the video signal.

A signal selected by the switches 8 and 9 is a DRAM controller (hereinafter referred to as DMC) 10
To the next stage dual port DRAM (hereinafter referred to as DD
A signal (MA: multiplex address, RAS: row address strobe, CAS: column address strobe) necessary for controlling the RAM 11 is generated. On the side of the DDRAM 11, a horizontal synchronizing signal (HD) is supplied to a terminal SE that selects which of serial data (SD) and random access data (RD) is to be valid, and which data is to be used is determined. There is.

FIG. 5 shows a horizontal synchronizing signal (HD) and a serial access request signal (S). REQ). A High level period of HD is a random accessible period, and a Low level period of HD is a horizontal blanking period. As shown in the figure, after the horizontal blanking period, the random access end waiting period is waited for, and then the serial access period is started. The random access end waiting period is longer than the longest random access cycle in order not to interrupt the random access cycle (time to randomly access the memory once).

[0005]

In the above-mentioned conventional serial / random access switching circuit, as shown in FIG. 5, the random access end waiting period is required to be several times as long as the random access cycle, and the random access period is random during this period. Since it cannot be accessed, it was a cause of lowering the processing capacity on the random access side.

The serial / random access switching circuit of the present invention has been made in view of such a problem, and it is necessary before serial access by providing means for arbitrating switching between serial access and random access. Another object of the present invention is to provide a serial / random access switching circuit that does not require a random access end waiting time and improves the processing capacity on the random access side.

[0007]

In order to achieve the above object, the serial / random access switching circuit of the present invention is provided with switching means for arbitrating switching between serial access and random access. Eliminates the waiting time for switching requests, random access requests, and refresh.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of this embodiment. same
In the figure, an arbiter circuit (hereinafter referred to as switching means)
(Referred to as ABT) 12 has a serial access request signal.
(S REQ) and a random access request signal (R RE
Q) and the refresh cycle signal of the DDRAM 11
Three signals of (RDY) are input and the serial access
Whether to perform random access or random access.
The signal SEL for selecting is output.

The signal SEL output from the ABT 12 is an address signal (A RD) and the address signal (S A
Switch 8 for switching D) and the random access request signal (R REQ) and serial access request signal (S
It is used to switch the switch 9 for switching REQ).

The signal selected by the switch is D
A signal (MA: multiplex address, R that is input to the MC 10 and is required to control the DDRAM 11
AS: row address strobe, CAS: column address strobe).

FIG. 3 is a diagram showing a detailed structure of the ABT 12. This ABT 12 has flip-flop circuits IC1 to IC1.
IC8, AND circuits AND1 to 4 and OR circuit OR1
, NAND circuit NAND1 and multi-input AND circuit AND5
And a serial access request signal (S REQ) is input to the multi-input AND circuit AND5 and the flip-flop circuit IC4
Output and the random access request signal (R REQ)
, And RDY and the output of the AND circuit AND4 are input. Further, the signal SEL is output from the OR circuit OR1.

FIG. 2 is a time chart showing the operation of this embodiment. In the figure, each signal is valid at High level (state 1). S A period in which REQ is 1 indicates a serial access request. R REQ indicates that a random access request is being made and a random access is being made. RDY indicates that the memory is being refreshed. SEL is a signal for switching the switch 8 and the switch 9 to the A side in the state 1, and indicates that the serial access is being performed.

The operation of the above configuration will be described below. At the time of random access, the switches 8 and 9 are connected to the B side, and the address for random access (R
AD), random access request signal (R REQ) is input and the random access data (RD) is DDR
Read and write to AM11.

At the time of serial access, a serial access request signal (S AD) is input to the ABT 12. A
The BT 12 determines the timing when serial access is possible, and connects the switches 8 and 9 to the A side. As a result, the serial access address (S AD), serial access request signal (S REQ) is supplied to the DMC 10,
The serial access data SD is read from or written to the DDRAM 11 once, and after the serial access is completed, the switches 8 and 9 are returned to the B side. FIG. 2A shows a state in which random access is not performed and refresh is not performed. When SEL is in the state 1, serial access is performed once.

FIG. 2B shows a state when a random access request occurs during serial access. Here, random access is performed once after the serial access (SEL is 1) is completed.

FIG. 2C shows a state when a serial access request is received during random access. here,
Random access (R After REQ is 1), serial access (SEL is 1) is performed once.

FIG. 2 (d) shows the case where the refresh state is entered during the serial access request. At this time, refresh (RDY is 1) is prioritized and serial access is performed once after the refresh is completed. The state shown by the dotted line in the figure shows the case where a serial access request comes during refresh (RDY = 1). Also at this time, the refresh is prioritized.

As described above, in this embodiment, the DDR
Since switching between serial access and random access is arbitrated by the ABT 12 with respect to the AM 11, the waiting time when switching from random access to serial access is minimized, and throughput on the random access side is improved.

[0020]

Since the waiting time required for switching between serial access and random access is minimized by using the switching means, the number of waits generated in the microprocessor for random access is reduced and the processing capability is improved. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a serial / random access circuit according to an embodiment.

FIG. 2 is a timing chart for explaining the operation of the serial / random access circuit according to the present embodiment.

FIG. 3 is a diagram showing a detailed configuration of an arbiter circuit.

FIG. 4 is a diagram showing a configuration of a conventional serial / random access circuit.

FIG. 5 is a diagram for explaining a conventional problem.

[Explanation of symbols]

8, 9 ... Switch, 10 ... DRAM controller (DM
C), 11 ... Dual-port DRAM (DDRAM),
12 ... Arbiter circuit (ABT).

Claims (1)

[Claims] 1. A serial / random access switching circuit for a dual-port DRAM, wherein switching means for arbitrating switching between serial access and random access is provided, and a switching end wait time for serial access request, random access request, and refresh is set. Serial / random access switching circuit characterized in that it is unnecessary.