JPH06242191A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] To generate a type recognition signal capable of electrically determining the types of IC chips having different operations from the outside, and to accurately determine the type of an IC chip in a short time. An internal circuit in which a type of circuit operation is set according to a type of a wiring mask used for determining a wiring pattern for at least one layer at the time of manufacturing, and an external input / output terminal 2
The input circuit 23, 24 and the output circuit 22 connected to the data bus signal line DBUS connected to the data bus 5 via the input clocked inverter circuits 17 to 20, and the input clocked inverter by decoding the control input. Decoder circuits 9-12 for generating control signals gi, l, n for controlling the circuit and the output clocked inverter circuit
And a wiring 26 connecting at least one output clocked inverter circuit input node and one of the two power supply nodes to each other.
1 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (I
The present invention relates to C), and more particularly, to a means used for externally determining the types of ICs having the same chip size but different operations.

[0002]

2. Description of the Related Art Generally, when manufacturing ICs, there are cases where several types of ICs having the same circuit configuration but different operations are manufactured. To achieve this, the data in the ROM (read-only memory) mounted on the chip is changed, or the wiring mask for determining the pattern of the wiring (for example, metal wiring) for at least one layer is changed at the time of manufacturing. ing.

Conventionally, in order that the type of the IC manufactured as described above can be discriminated from the outside, a recognition pattern which allows the operator to recognize the pattern by looking through the IC chip with a microscope or the like is created in advance in the wiring layer. Or I
When the C chip is packaged and shipped, the recognition character is displayed on the package surface.

FIG. 5 shows an example of a metal wiring mask pattern used to create a recognition pattern on an IC chip when several types of ICs are manufactured by changing ROM data. The recognition pattern 51 is the code number of the ROM (corresponding to the contents of the ROM data)
Is shown.

However, as described above, when the type of the IC chip is discriminated, it takes a long time for the operator to look through the individual IC chips with a microscope or the like, which may cause a discrimination error due to fatigue or the like. The countermeasure is desired.

[0006]

As described above, in the conventional IC, the operator needs to look through the individual IC chips with a microscope or the like when determining the chip type, which requires a long time, fatigue, etc. There was a problem that there is a possibility that a discrimination error may occur due to.

The present invention has been made to solve the above problems, and it is possible to electrically determine the types of several types of IC chips having different operations from the outside, and to accurately determine the types of IC chips in a short time. It is an object of the present invention to provide a semiconductor integrated circuit that enables the above.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to an integrated circuit chip in which the type of circuit operation is set according to the type of wiring mask used to determine the wiring pattern for at least one layer during manufacturing. A circuit, at least one data bus signal line connected to an external input / output terminal of an integrated circuit chip, and at least one data bus signal line connected to the data bus signal line via an input clocked inverter circuit. An input circuit, at least one output circuit connected to the data bus signal line via an output clocked inverter circuit, and a control input to decode the input clocked inverter circuit and the output clocked inverter circuit. At least one of a decoder circuit for generating a control signal for controlling the inverter circuit and the output clocked inverter circuit Characterized by comprising a type recognition signal generating circuit consisting of one and connecting the wiring of the input nodes and two power supply nodes.

[0009]

Since the type recognition signal generating circuit for generating the type recognition signal capable of electrically determining the type of the IC chip outside the chip is included, the type of the IC chip can be accurately determined in a short time. Become.

Moreover, it is possible to make the type recognition signal generation circuit based on the same mask as the wiring mask used for determining the type of IC, and it is dedicated to form the type recognition signal generation circuit. You don't need a mask.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a part of an IC according to an embodiment of the present invention.

The IC shown in FIG. 1 is formed on an IC chip according to the type of a wiring mask used for determining a pattern for at least one layer of a master slice type metal wiring at the time of manufacturing, and the type of circuit operation is It has a set internal circuit (not shown).

In the IC of FIG. 1, 1 is a first external input terminal, 2 is a second external input terminal, 21 and 22 are plural output circuits (two in this example), and 23 and 24 are plural. (Two in this example) input circuits, 25 is an external input / output terminal of the IC chip, and DBUS is at least one or more data bus signal lines connected to the external input / output terminal 25.
The first external input terminal 1 and the second external input terminal 2 are
Correspondingly, via the pull-up resistors 3 and 4, the power supply potential V
It is connected to the DD node.

Reference numerals 5 and 6 are two-stage inverter circuits connected to the first external input terminal 1, and reference numerals 7 and 8 are two-stage inverter circuits connected to the second external input terminal 2. .

The four NOR circuits 9 to 12 form a decoder circuit which decodes the control signal input from each of the inverter circuits 5, 6, 7 and 8 to generate control signals g, i, l and n. ing.

Reference numerals 13 and 14 denote the data bus signal lines DB.
This is a two-stage input clocked inverter circuit that is inserted and connected to the US, and the output of the preceding stage of the two-stage inverter circuits 5 and 6 is supplied as these control inputs.

Reference numerals 15 and 16 denote two-stage output clocked inverter circuits which are inserted and connected to the data bus signal line DBUS. Of the two-stage inverter circuits 5 and 6 as their control inputs. The output of the latter stage is being supplied.

Reference numerals 17 and 18 denote the data bus signal line DB.
It is an input clocked inverter circuit connected correspondingly between the US and the input circuits 23, 24, and the control signals g, i are respectively supplied as control inputs thereof.

Reference numerals 19 and 20 denote clocked inverter circuits for output, which are connected between the output circuits 21 and 22 and the data bus signal line DBUS, respectively, and serve as their control inputs. The control signals 1 and n are supplied. Further, as at least one of the output circuits 21 and 22 (21 in this example), a type recognition signal generation circuit is provided. FIG. 2 shows a specific example of the type recognition signal generation circuit 21.

This type recognition signal generating circuit includes an input node of the output clocked inverter circuit 19 and two power supply nodes (power supply potential VDD node and ground potential VSS node).
The metal wiring 26 is connected to either one of the two.

In this case, the pattern of the metal wiring 26 is formed based on a wiring mask used for setting the type of circuit operation of the internal circuit of the IC. In other words, the metal wiring for setting the type of circuit operation of the internal circuit of the IC and the metal wiring 2 of the type recognition signal generation circuit
6 is formed of the same wiring layer. Next, a circuit operation related to type recognition in the IC having the above configuration will be described. (A) When both the first external input terminal 1 and the second external input terminal 2 are open.

The potential of the first external input terminal 1 is pulled up to a high level "H" by the pull-up resistor 3, the output a of the inverter circuit 5 is low level "L", and the output b of the inverter circuit 6 is "H". "become.

Similarly, the potential of the second external input terminal 2 is pulled up to a high level "H" by the pull-up resistor 4, the output c of the inverter circuit 7 is a low level "L", and the output d of the inverter circuit 8 is d. Becomes "H".

As a result, the outputs g, i, l, n of the four NOR circuits 9, 10, 11, 12 for the decoder are correspondingly "L", "L", "L", "H". ", The output clocked inverter circuits 20, 15 and 16 become operable, and the input clocked inverter circuits 13 and 1
4, 17, 18 and the output clocked inverter circuit 19 are in a non-operating state (the output is in a high impedance state).

Therefore, the output signal m of the output circuit 22 is the output clocked inverter circuit 20 and the data bus signal line D.
BUS, two-stage output clocked inverter circuit 15,
It is output to the outside from the external input / output terminal 25 via 16. (B) In the case where the first external input terminal 1 is open and “L” is applied to the second external input terminal 2.

The potential of the first external input terminal 1 is pulled up to "H" by the pull-up resistor 3, the output a of the inverter circuit 5 is low level "L", and the output b of the inverter circuit 6 is "H". Become.

On the other hand, "H" is supplied to the second external input terminal 2 through the pull-up resistor 4, but the impedance of the external input signal source is lower than that of the pull-up resistor 4. Then, the output becomes "L", the output c of the inverter circuit 7 becomes "H", and the output d of the inverter circuit 8 becomes "L".

Thus, the outputs g, i, l, n of the four NOR circuits 9, 10, 11, 12 for the decoder are correspondingly "L", "L", "H", "L". ", The output clocked inverter circuits 19, 15 and 16 become operable, and the input clocked inverter circuits 13 and 1
4, 17, 18 and the output clocked inverter circuit 20 are in a non-operating state (the output is in a high impedance state).

Therefore, the output signal (type recognition signal) k of the output circuit 21 for the type recognition signal generation circuit is the output clocked inverter circuit 19, the data bus signal line DBUS, 2
The signal is output to the outside from the external input / output terminal 25 via the output clocked inverter circuits 15 and 16 of the stages. (C) "L" is applied to the first external input terminal 1
When the external input terminal 2 of is open.

The first external input terminal 1 has a pull-up resistor 3
Although "H" is supplied via the input circuit, if the impedance of the external input signal source is lower than that of the pull-up resistor 3, it becomes "L", and the output a of the inverter circuit 5 is "H". The output b of the circuit 6 becomes "L".

On the other hand, the potential of the second external input terminal 2 is pulled up to "H" by the pull-up resistor 4,
The output c of the inverter circuit 7 becomes low level "L", and the output d of the inverter circuit 8 becomes "H".

Accordingly, the outputs g, i, l, n of the four NOR circuits 9, 10, 11, 12 for the decoder are correspondingly "L", "H", "L", "L". ", The input clocked inverter circuits 13, 14 and 18 become operable, and the output clocked inverter circuits 19 and 2 become
0, 15, 16 and the input clocked inverter circuit 17 are in a non-operating state (the output is in a high impedance state).

Therefore, the input signal input from the external input / output terminal 25 is a two-stage input clocked inverter circuit 1 for input.
3 and 14, the data bus signal line DBUS, and the input clocked inverter circuit 18, and input to the input circuit 24. (D) When “L” is applied to both the first external input terminal 1 and the second external input terminal 2.

The first external input terminal 1 has a pull-up resistor 3
Although "H" is supplied via the input circuit, if the impedance of the external input signal source is lower than that of the pull-up resistor 3, it becomes "L", and the output a of the inverter circuit 5 is "H". The output b of the circuit 6 becomes "L".

Similarly, "H" is supplied to the second external input terminal 2 through the pull-up resistor 4, but if the impedance of the external input signal source is lower than that of the pull-up resistor 4. The output c of the inverter circuit 7 becomes "H", and the output d of the inverter circuit 8 becomes "L".

As a result, the outputs g, i, l, n of the four NOR circuits 9, 10, 11, 12 for the decoder are correspondingly "H", "L", "L", "L". ", The input clocked inverter circuits 13, 14, 17 become operable, and the output clocked inverter circuits 19, 2,
0, 15, 16 and the input clocked inverter circuit 18 are in the non-operating state (the output is in the high impedance state).

Therefore, the input signal input from the external input / output terminal 25 is a two-stage input clocked inverter circuit 1 for input.
3, 14, the data bus signal line DBUS, and the input clocked inverter circuit 17 to input to the input circuit 23.

That is, according to the IC of the first embodiment, I
Type recognition signal generation circuit 21 for generating a type recognition signal k capable of electrically determining the type of the C chip outside the chip
Since it is provided on the IC chip, the type of the IC chip can be accurately determined in a short time.

Moreover, the metal wiring 26 of the type recognition signal generating circuit 21 can be patterned based on the same mask as the metal wiring mask used for determining the type of IC. Generation circuit 2
There is no need for a dedicated mask for forming 1.

As a second embodiment of the IC of the present invention,
A ROM in which the on / off state of the memory cell transistor is set according to the type of mask used to determine the ion implantation region during manufacturing, and a circuit in which the type of circuit operation is set by the data of this ROM A type recognition signal generation circuit may be provided to the IC included therein as in the first embodiment.

In the IC of the second embodiment, it is possible to form the transistors used in the type recognition signal generation circuit based on the mask used to form the memory cell transistors of the ROM. 3 and 4
Shows different concrete examples of the type recognition signal generating circuit provided in the IC of the second embodiment.

The type recognition signal generating circuit of FIG. 3 comprises a PMOS transistor TP and an NMOS transistor TN which are connected in series between the VDD node and the VSS node, and the gates of the both transistors have NOR gates for the decoder. Inverter circuit 31 for inverting one of the control signals output from the circuit (control signal l in this example)
Output signal is supplied, and the potential of the drain interconnection node (output node) of both transistors is supplied as a circuit operation type recognition signal k.

In the type recognition signal generation circuit of FIG. 3, when the control signal 1 is "L", the output of the inverter circuit 31 becomes "H", and the PMOS transistors TP and NMOS.
The transistor TN is turned off / on correspondingly, and the type recognition signal k becomes "L".

On the other hand, when the control signal 1 is "H", the output of the inverter circuit 31 becomes "L" and the PMO
The S transistor TP and the NMOS transistor TN are turned on / off correspondingly, and the type recognition signal k becomes "H".

Here, an AND type ROM of a system in which a plurality of NMOS transistors for memory cells are connected in series
A desired NMOS for a memory cell in an IC having a
When using a mask for ion-implanting P-type impurities so that the drain and source of the transistor are short-circuited (set to the ON state), the NMOS transistor TN of the type recognition signal generation circuit is set based on this mask. Once formed, it shorts between the VDD and VSS nodes. However, by setting the impedance of the PMOS transistor TP of the type recognition signal generation circuit above the impedance of the NMOS transistor TN, the type recognition signal k becomes "L".

When the type recognition signal generation circuit of FIG. 3 is provided as the output circuit 21 of FIG. 1, the type recognition signal k is output when the control signal 1 is "H" as described above. A clocked inverter circuit 19, a data bus signal line DBUS, and two stages of output clocked inverter circuits 15 and 16 are used to output from the external input / output terminal 25 to the outside.

The type recognition signal generating circuit of FIG. 4 comprises a PMOS transistor TP and an NMOS transistor TN which are connected in series between the VDD node and the VSS node, and the gates of the both transistors have NOR gates for the decoder. One of the control signals output from the circuit (control signal 1 in this example) is input, and the potential of the drain interconnection node (output node) of both transistors is supplied as the circuit operation type recognition signal k.

The operation of the type recognition signal generation circuit of FIG. 4 is basically the same as the operation of the type recognition signal generation circuit described above with reference to FIG. 3, but the significance level of the type recognition signal k is "H". Is different.

That is, when the control signal 1 is "L", P
The MOS transistor TP and the NMOS transistor TN are turned on / off correspondingly, and the type recognition signal k becomes "H". On the other hand, when the control signal 1 is "H", the PMOS transistor TP and the NMOS transistor TN are turned off / on correspondingly, and the type recognition signal k becomes "L".

Here, an AND type ROM of a system in which a plurality of PMOS transistors for memory cells are connected in series
A desired PMOS for a memory cell in an IC having
When using a mask for ion-implanting N-type impurities so that the drain and source of the transistor are short-circuited (set to the ON state), the PMOS transistor TP of the type recognition signal generation circuit is set based on this mask. Once formed, it shorts between the VDD and VSS nodes. However, the type recognition signal k becomes "H" by setting the impedance of the NMOS transistor TN of the type recognition signal generation circuit above the impedance of the PMOS transistor TP.

When the type recognition signal generating circuit of FIG. 4 is provided as the output circuit 21 of FIG. 1, when the control signal 1 is "H" as described above, the type recognition signal k is generated. Is an output clocked inverter circuit 19,
The data bus signal line DBUS is output to the outside from the external input / output terminal 25 via the two-stage output clocked inverter circuits 15 and 16.

[0052]

As described above, according to the IC of the present invention,
Since the type recognition signal generation circuit for generating the type recognition signal capable of electrically determining the type of the IC chip outside the chip is included, the type of the IC chip can be accurately determined in a short time.

Moreover, the type recognition signal generation circuit can be created based on the same mask as the mask used to determine the type of IC, and a dedicated mask for forming the type recognition signal generation circuit is required. Don't do that.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram showing a part of an IC according to a first embodiment of the present invention.

2 is a circuit diagram showing an example of a type recognition signal generation circuit in FIG.

FIG. 3 is a circuit diagram showing an example of a type recognition signal generation circuit provided in an IC according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a modification of the type recognition signal generation circuit of FIG.

FIG. 5 is a diagram showing an example of a ROM code number pattern for type recognition on a metal wiring mask used in manufacturing a conventional IC.

[Explanation of symbols]

1 ... 1st external input terminal, 2 ... 2nd external input terminal,
3, 4 ... Pull-up resistors, 5-8 ... Inverter circuit,
9-12 ... NOR circuit, 13, 14, 17, 18 ... Input clocked inverter circuit, 15, 16, 19, 20 ...
Output clocked inverter circuit, 21 ... Output circuit (type recognition signal generation circuit), 22 ... Output circuit, 23, 24 ...
Input circuit, 25 ... External input / output terminal, 26 ... Metal wiring of type recognition signal generating circuit, g, i, l, n ... Control signal, D
BUS ... data bus signal line, TP ... PMOS transistor, TN ... NMOS transistor.

Claims (4)

[Claims] 1. A circuit on an integrated circuit chip in which a type of circuit operation is set in accordance with a type of a wiring mask used for determining a wiring pattern for at least one layer at the time of manufacturing, and an external circuit of the integrated circuit chip. At least one data bus signal line connected to the input / output terminal, at least one input circuit connected to the data bus signal line via an input clocked inverter circuit, and the data bus signal At least one output circuit connected to the line through the output clocked inverter circuit, and for decoding the control signal input to control the input clocked inverter circuit and the output clocked inverter circuit A decoder circuit for generating a control signal, and at least one input node of the output clocked inverter circuit and two Characterized by comprising a type recognition signal generating circuit consisting of one and connecting the wiring of the power supply node. 2. The semiconductor integrated circuit according to claim 1, wherein the wiring of the type recognition signal generation circuit is patterned based on a wiring mask used for setting the type of the circuit operation. Semiconductor integrated circuit. 3. A MOS transistor for a memory cell is turned on / off according to the type of a mask formed on an integrated circuit chip and used for determining an ion implantation region during manufacturing.
A ROM in which the off state is set; a circuit in which the type of circuit operation is set by the data of this ROM; and at least one or more data bus signal lines connected to the external input / output terminals of the integrated circuit chip, At least one input circuit connected to the data bus signal line via an input clocked inverter circuit; and at least one input circuit connected to the data bus signal line via an output clocked inverter circuit Output circuit, a decoder circuit that decodes a control input to generate a control signal for supplying to the input clocked inverter circuit or the output clocked inverter circuit, and among the control signals output from the decoder circuit One input inverter circuit and a PMOS connected in series between the first power supply node and the second power supply node The output signal of the inverter circuit is input to each gate of both transistors, and the output potential of the drain interconnection node of both transistors is used as a type recognition signal of circuit operation for the output clocked inverter circuit. And a type recognition signal generating circuit supplied as an input of at least one of the above. 4. The semiconductor integrated circuit according to claim 2, wherein the transistor of the type recognition signal generation circuit is the RO.
ON / OFF based on the mask used to set the ON / OFF state of the MOS transistor for M memory cells
A semiconductor integrated circuit in which an off state is set.