JPH06167722A - Active matrix substrate and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] A polycrystalline silicon thin film transistor and an auxiliary capacitor can be formed in the same process, and by reducing the occurrence of parasitic capacitance and leaks, a bright display screen with good image quality is realized. To do. [Structure] The channel 2C of the thin film transistor is formed in self-alignment with the gate electrodes 4 and 6. That is, the source 2A and the drain 2B are formed by implanting impurities into the first semiconductor layer using the gate electrode semiconductor layer as a mask. Therefore, the ends of the gate electrodes 4 and 6 and the ends of the channel 2C are likely to coincide with each other, and the gate electrodes 4 and 6 and the source 2A are easily aligned.
The overlapping portion with and the overlapping portion between the gate electrodes 4 and 6 and the drain 2B are extremely small. Further, in terms of the configuration, by implanting an impurity into the first semiconductor layer, the first auxiliary capacitance electrode 2D that forms the auxiliary capacitance is formed simultaneously with the source 2A of the thin film transistor and the like, and in addition, the second auxiliary capacitance electrode is formed. 8B is formed simultaneously with the source wiring 8A or the gate wiring 10A. Therefore, the active matrix substrate can be manufactured without the need for a separate step of forming the auxiliary capacitance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate of a liquid crystal display device having a storage capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to improve the yield and reduce the thickness of liquid crystal display devices, technological development has been made to integrally form a display section and a drive circuit constituting the liquid crystal display device.
Since a driving circuit is required to have a high response speed, a polycrystalline silicon thin film transistor is usually used. In order to keep the manufacturing cost low, it is desirable to form the display unit and the drive circuit in the same process. Therefore, a polycrystalline silicon thin film transistor is used as the switching transistor of the display unit.

However, the polycrystalline silicon thin film transistor has a large leak current in a non-conducting state. Therefore, there is a problem that after the transistor is conductive and the liquid crystal portion is charged with electric charge, the transistor is turned off and then the electric charge held in the liquid crystal portion leaks. Since the gradation of the screen of a liquid crystal display device is determined by the amount of charge held in the liquid crystal portion,
The leakage of electric charge greatly affects the display performance, and the screen is not displayed normally. In order to solve such a problem, a capacitor is formed in parallel with the liquid crystal part as an auxiliary capacitor.

FIG. 23 shows an equivalent circuit of a basic structural unit corresponding to one picture element in a liquid crystal display device having a storage capacitor. As shown in the drawing, a thin film transistor 105, which is a switching element in the i-th row and the j-th column of the liquid crystal portion 104 for displaying, is formed at the intersection of the gate wiring 101 in the i-th row and the source wiring 103 in the j-th column. . Liquid crystal unit 104
Thin film transistor 105 and (i +
1) A storage capacitor 106 is formed between the gate wiring 102 of the first row.

An example of the simplest conventional manufacturing method of the active matrix substrate of the liquid crystal display device having the auxiliary capacitance as described above will be described with reference to FIGS.

First, as shown in FIG. 24A, a semiconductor layer 202 to be a source 207, a drain 208 and a channel 209 of a thin film transistor is formed on an insulating substrate 201.

Next, as shown in FIG. 24B, after covering the upper surface of the semiconductor layer 202 with a gate insulating film 203,
A refractory metal layer 204 to be the gate electrode 205 and the auxiliary capacitance electrode 206 is formed.

The refractory metal layer 204 is etched to form a gate electrode 205 and an auxiliary capacitance electrode 206 as shown in FIG. 24C, and then the source 207 of the semiconductor layer 202 is used with the gate electrode 205 as a mask. Impurity ions are implanted into the region and the drain 208 region. That is,
It uses a self-aligned method.

Next, the interlayer insulating film 2 is formed on the entire surface of the substrate 201.
10 to form a source 20 as shown in FIG.
7, a metal electrode 211 for making contact with 7, a metal electrode 212 for making contact with the drain 208, and a metal electrode (not shown) for making contact with the gate electrode 205 are formed.

Finally, as shown in FIG. 24E, a pixel electrode 213 made of a transparent conductive material such as ITO is formed.

A liquid crystal display device is obtained by arranging a counter substrate having a counter electrode formed thereon so as to face the active matrix substrate formed as described above, and enclosing liquid crystal between the two substrates.

In the active matrix substrate manufactured as described above, the auxiliary capacitance is the auxiliary capacitance electrode 2
An interlayer insulating film 210 is formed as a dielectric layer between 06 and the pixel electrode 213.

Another example of a method of manufacturing an active matrix substrate of a conventional liquid crystal display device having a storage capacitor is shown in FIG.
First, FIG. 25 (a) will be described based on (a) to (f).
As shown in, SiO ₂ film 302 on the insulating substrate 301
Is deposited on the SiO ₂ film 302, the first polycrystalline Si
Deposit the film. By forming a mask 305 made of a SiO ₂ film on the first polycrystalline Si film and doping the polycrystalline Si film, the first polycrystalline Si portion to be the channel 303 of the transistor and impurities are doped. And a first polycrystalline Si portion 304 is obtained.

Next, as shown in FIG. 25B, the impurity-doped first polycrystalline Si portion 304 is etched to form the source 306 and drain 30 of the transistor.
7 and the first auxiliary capacitance electrode 308 are formed.

Next, as shown in FIG. 25C, a gate insulating film 309 is formed on the upper surfaces of the channel 303, the source 306, and the drain 307, which are the first polycrystalline Si layer, and the first auxiliary film is formed. An insulating film 310 is formed on the upper surface of the capacitor electrode 308. Further, the second polycrystalline Si layer 311 is deposited on the entire surface of the substrate 301 in such a state.

Subsequently, as shown in FIG. 25D, the second polycrystalline Si layer 311 is patterned by photoetching, and the gate electrode 31 is formed on the gate insulating film 309.
2 is formed, and the second auxiliary capacitance electrode 313 is formed on the insulating film 310. After that, the substrate 3 in such a state
The whole surface of 01 is doped with impurities.

Next, as shown in FIG. 25E, an interlayer insulating film 314 is formed, and a metal electrode 315 for making contact with the source 306, a metal electrode 316 for making contact with the drain 307, and a gate electrode 312. A metal electrode (not shown) for making contact with the first auxiliary capacitance electrode 308 and a metal electrode 31 for making contact with the first auxiliary capacitance electrode 308.
Form 7.

Finally, as shown in FIG. 25F, a pixel electrode 318 made of a transparent conductive material such as ITO is formed.

The active matrix substrate formed as described above is provided with a counter substrate on which a counter electrode is formed so as to face it, and a liquid crystal is sealed between both substrates to form a liquid crystal display device.

In the active matrix substrate manufactured as described above, the auxiliary capacitance is formed by forming the insulating film 310 as a dielectric layer between the first auxiliary capacitance electrode 308 and the second auxiliary capacitance electrode 313. Has been done.

[0021]

Since the conventional active matrix substrate described with reference to FIG. 24 uses the self-alignment method, the gate electrode 205 and the source 2 are not used.
07 and the gate electrode 205 and the drain 2
There is almost no overlapping portion with 08, and there is an advantage that parasitic capacitance is unlikely to occur. However, since the interlayer insulating film 210 is used as the dielectric layer of the auxiliary capacitance, the thickness of the dielectric layer is about 5000 angstroms and the thickness of the dielectric layer is large. The capacitance becomes smaller, and the area of the auxiliary electrode electrode 206 must be increased in order to secure the required capacitance. as a result,
There is a problem that the aperture ratio of the picture element portion is reduced and the display screen becomes dark.

On the other hand, in another conventional active matrix substrate described with reference to FIG. 25, the insulating film 310, which is the dielectric layer of the auxiliary capacitance, can be made thin, so that the aperture ratio of the pixel portion does not decrease. However, as shown in FIGS.
After the formation of the drain 307 and the drain 307, a gate electrode 312 is formed as shown in FIGS. Therefore, due to misalignment of the etching mask used to form the gate electrode 312 and expansion / contraction of the substrate 301 due to heat treatment, the gap between the gate electrode 312 and the source 306 and between the gate electrode 312 and the drain 307.
There can be an overlap with. As a result, the gate electrode 312
Parasitic capacitance occurs in the overlapping portion of the gate electrode 312 and the drain 307 and the overlapping portion of the source 306 and the source 306. This parasitic capacitance has a problem that it adversely affects the charging of a liquid crystal with a screen signal and causes deterioration of image quality.

Further, in any of the active matrix substrates, electric field concentration occurs in a sharp portion around the lower electrodes 206 and 308 of the auxiliary capacitance, for example, a portion indicated by A in FIG. 25 (f). Further, the pointed portion is the insulating film 20.
Since it is a region where the coating properties of 3, 309 and 310 are likely to deteriorate, leakage and short circuits are likely to occur.

The present invention has been made to solve the above-mentioned problems of the prior art, and it is possible to form a polycrystalline silicon thin film transistor and an auxiliary capacitance in the same process, and to reduce the occurrence of parasitic capacitance and leakage. Therefore, it is an object of the present invention to provide an active matrix substrate which can realize a bright display screen with good image quality and a manufacturing method thereof.

[0025]

An active matrix substrate of the present invention includes an insulating substrate, a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to intersect each other, and two adjacent wirings. The pixel electrode formed in a portion surrounded by the source wiring and the two adjacent gate wirings is provided in the vicinity of the intersection of the source wiring and the gate wiring, and one is provided with an insulating film interposed therebetween. A thin film transistor, in which a gate electrode is formed by being electrically connected to the gate wiring, a channel is formed by self-aligning with the gate electrode on the other side, and a source and a drain are formed in the other part, is separated from the thin film transistor. And a first auxiliary capacitance electrode formed mainly in a portion other than the pixel electrode and made of the same material as the source and electrically connected to the pixel electrode, and a first auxiliary capacitance electrode. In between The auxiliary capacitance is formed so as to face each other with the edge film sandwiched therebetween, and the auxiliary capacitance is electrically connected to the gate line, and the second auxiliary capacitance electrode made of the same material as the source line is provided, whereby The purpose is achieved.

In another active matrix substrate of the present invention, an insulating substrate and a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to cross each other are adjacent to each other.
A pixel electrode formed in a portion surrounded by two source wirings and two adjacent gate wirings, and provided near an intersection of the source wiring and the gate wiring. And a thin film transistor in which a gate electrode is formed by being electrically connected to the gate wiring, a channel is formed on the other side by self-alignment with the gate electrode, and a source and a drain are formed in other portions, and the thin film transistor. Separate
A first auxiliary capacitance electrode that is mainly formed in a portion other than the pixel electrode and is made of the same material as the source and that is electrically connected to the pixel electrode, and the first auxiliary capacitance electrode, The auxiliary capacitance is formed so as to face each other with the insulating film interposed therebetween, and the second auxiliary capacitance electrode formed of a part of the gate wiring is provided, whereby the above object is achieved.

A covering member made of an insulating material for covering the side surfaces of the source, the channel and the drain and the side surface of the first auxiliary capacitance electrode may be further provided.

The method of manufacturing an active matrix substrate of the present invention comprises an insulating substrate, a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to intersect each other, and two adjacent source wirings. A pixel electrode formed in a portion surrounded by two adjacent gate wirings, a thin film transistor formed near an intersection of the source wiring and the gate wiring, and the thin film transistor are separated from each other, and A first auxiliary capacitance electrode mainly formed on a portion other than the pixel electrode, and a second auxiliary capacitance electrode facing each other with an insulating film interposed between the first auxiliary capacitance electrode and the second auxiliary capacitance electrode. A method for manufacturing an active matrix substrate, comprising: a transistor forming region and an auxiliary capacitance forming region on the substrate;
Forming a semiconductor layer, a first insulating film, and a second semiconductor layer in this order from the substrate side to form two island-shaped laminated bodies, and covering the laminated bodies on the substrate. Forming a third semiconductor layer, and a part of the second semiconductor layer and the third semiconductor layer.
Forming a semiconductor layer for a gate electrode by removing a part of the semiconductor layer, and implanting an impurity into the first semiconductor layer using the semiconductor layer for a gate electrode and the semiconductor layer for a gate electrode as a mask. Forming the gate electrode semiconductor layer as a gate electrode, and forming the first semiconductor layer as the source and drain of the transistor and the first auxiliary capacitance electrode,
A step of simultaneously forming the source line and the second auxiliary capacitance electrode on the substrate on which the source and the drain are formed; and a step of electrically connecting the second auxiliary capacitance electrode to the gate. It includes a step of forming a wiring and a step of electrically connecting to the first auxiliary capacitance electrode to form the pixel electrode, whereby the above object is achieved.

Another method of manufacturing an active matrix substrate of the present invention is an insulating substrate, and a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to intersect each other.
A pixel electrode formed in a portion surrounded by two adjacent source wirings and two adjacent gate wirings, a thin film transistor formed near an intersection of the source wiring and the gate wiring, and the thin film transistor And a first auxiliary capacitance electrode, which is formed mainly in a portion other than the pixel electrode, is opposed to the first auxiliary capacitance electrode with an insulating film interposed therebetween to form an auxiliary capacitance. A method of manufacturing an active matrix substrate including a second auxiliary capacitance electrode, comprising: a first semiconductor layer, a first insulating film, and a second insulating film in a transistor formation region and an auxiliary capacitance formation region on the substrate. Forming a semiconductor layer in this order from the substrate side to form two island-shaped laminated bodies; forming a third semiconductor layer on the substrate to cover the laminated bodies; Part of the semiconductor layer and one of the third semiconductor layers To form a semiconductor layer for a gate electrode, the semiconductor layer for a gate electrode, and the semiconductor layer for a gate electrode are used as a mask to inject an impurity into the first semiconductor layer to form a semiconductor for the gate electrode. Forming a layer as a gate electrode and the first semiconductor layer as a source and a drain of the transistor and the first auxiliary capacitance electrode; and on the substrate on which the source and the drain are formed,
Forming the gate line and the second auxiliary capacitance electrode at the same time, and electrically connecting to the first auxiliary capacitance electrode,
And a step of forming the picture element electrode, whereby the above object is achieved.

The method may further include a step of forming a covering member on the side surface of the laminate, the covering member covering the side surface.

[0031]

In the active matrix substrate and manufacturing method of the present invention, the channel of the thin film transistor is formed in self-alignment with the gate electrode. That is, the source and drain are formed by implanting impurities into the first semiconductor layer using the gate electrode semiconductor layer as a mask. Therefore, the end portion of the gate electrode and the end portion of the channel easily coincide with each other, and the overlapping portion between the gate electrode and the source and the overlapping portion between the gate electrode and the drain are extremely small.

Further, in terms of the structure, by implanting an impurity into the first semiconductor layer, a first auxiliary capacitance electrode forming an auxiliary capacitance is formed at the same time as the source of the thin film transistor, and in addition, a second auxiliary capacitance is formed. The electrode is formed at the same time as the source wiring or the gate wiring. Therefore, the active matrix substrate can be manufactured without the need for a separate step of forming the auxiliary capacitance.

When the side surface of the layer forming the source, drain and channel of the thin film transistor is further provided with a covering member made of an insulating material, the insulating property of this side surface portion is improved.

[0034]

EXAMPLES The present invention will be described below with reference to examples.

<First Embodiment> FIG. 1 is a plan view of a main portion of an active matrix substrate of a first embodiment of the present invention, and FIGS. 2 to 9 show a manufacturing process of the active matrix substrate of the present embodiment. It is sectional drawing shown. 2 to 9 are (a), (b) and (c), respectively, which are a sectional view taken along the line AA, a sectional view taken along the line BB and a sectional view taken along the line CC of FIG.

In this active matrix substrate, as shown in FIG. 1, a source wiring 8A and a gate wiring 10A to which an image signal is sent are laid vertically and horizontally on a glass substrate 1, and an adjacent source wiring 8A and an adjacent gate are connected. A picture element is formed in a portion surrounded by the wiring 10A. Source wiring 8
In the portion where A and the gate wiring 10A intersect, FIG.
The source 2A is connected to the source wiring 8A as shown in (b), and the gate wiring 10A as shown in FIG. 9 (c).
A thin film transistor is formed in which the lower layer gate electrode 4 is connected to the lower layer gate electrode 4 via the upper layer gate electrode 6. A pixel electrode 12 is connected to the drain 2B of this thin film transistor via a first metal wiring 10B as shown in FIG. 9B. The pixel electrode 12 has a second electrode as shown in FIG.
Part of the gate wiring 10 through the metal wiring 10C of
It is connected to the first auxiliary capacitance electrode 2D formed below A. Below the gate line 10A and above the first auxiliary capacitance electrode 2D, as shown in FIG. 9A, the gate line 10A is interposed with the first insulating film 3 and the silicon nitride film 6 interposed therebetween. Second auxiliary capacitance electrode 8B connected to
Are formed.

A method of manufacturing the liquid crystal display device having the above structure will be described.

First, the cleaned glass substrate 1 is set in the plasma CVD apparatus, and the temperature of the substrate 1 is set to 400-6.
The SiH ₄ gas, which is kept at 00 ° C. and diluted with H ₂ , is decomposed by heat and plasma to form an amorphous Si film having a film thickness of about 1000 Å on the substrate 1. Then, the deposited amorphous Si film is removed from the deposited amorphous Si film in a vacuum or an inert gas atmosphere.
Annealing is performed at 600 ° C. for 50 hours to obtain the polycrystalline Si film 2a shown in FIG. Further, subsequently, on the polycrystalline Si film 2a, a SiO ₂ film having a film thickness of about 1000 angstroms to be the first insulating film 3 is formed by an atmospheric pressure CVD apparatus.
The film 3a is formed. In the above steps, from the inside of the plasma CVD apparatus for depositing the polycrystalline Si film 2a and the SiO ₂ film 3a to the annealing furnace, and from the annealing furnace to the atmospheric pressure CV.
When the substrate 1 or the like is transferred to the D device, the substrate 1 or the like is not exposed to the atmosphere at this time because the substrate or the like is transferred through a load lock chamber in a vacuum or an inert gas atmosphere.

Next, on the SiO ₂ film 3a, a polycrystalline Si film 4a having a film thickness of about 1000 Å serving as the lower gate electrode 4 is formed by a low pressure CVD apparatus. FIG. 2 shows a state of manufacturing up to this point, in which a three-layer laminated film is formed on the substrate 1.

This three-layered film is simultaneously etched by a resist pattern formed in the shape of a portion for forming an auxiliary capacitor and a thin film transistor, and is processed into an island pattern as shown by hatching in FIG. 10 to form a transistor portion T1. The auxiliary capacitance portion S1 is formed. Reactive ion etching is used for this etching, and the island-shaped polycrystalline Si film 2a, SiO ₂ film 3a and polycrystalline S after etching are used.
Anisotropic etching is performed so that the side surface of the i film 4a is perpendicular to the surface of the substrate 1. In the above etching, as the etching gas, the polycrystalline Si films 2a, 4a are used.
A mixed gas of SF ₆ and CCl ₄ is used for the SiO ₂ film 3
CH ₃ gas is used for a.

Next, as shown in FIG. 4, an SiO 2 film having a thickness of about 5000 angstroms is formed on the entire surface of the substrate 1 including the island-shaped pattern made of the three laminated films by using a normal pressure CVD apparatus.
_{2 The} film 5a is formed. After that, anisotropic etching is performed by the reactive ion etching method to form the covering member 5, leaving the SiO ₂ film 5a only on the side surface of the island pattern, as shown in FIG.

Then, a polycrystalline Si film to be the upper gate electrode 6 is formed on the surface of the substrate 1 by a low pressure CVD apparatus to about 200.
Deposit with a thickness of 0 Å. After that, FIG.
Using the resist pattern formed in the shape of the upper layer gate electrode 6 as shown in FIG. 6, the pattern of the upper layer gate electrode 6 and the pattern of the lower layer gate electrode 4 are simultaneously formed by the reactive ion etching method as shown in FIG. Form.

After ion-implanting an element which becomes a predetermined impurity on the substrate 1 in such a state, activation annealing of the element is performed to form the polycrystalline Si films 4a and 6a and the polycrystalline Si film 2a. The upper layer gate electrode 6, the lower layer gate electrode 4, the source 2A, the drain 2B, and the first auxiliary capacitance electrode 2D are formed by using an n-type or p-type semiconductor to have a constant conductivity and low resistance. Here, the upper layer gate electrode 6 and the lower layer gate electrode 4 function as a mask for forming the channel 2C of the transistor.

Next, after depositing a silicon nitride film 7 having a film thickness of about 1000 angstroms on the substrate 1 in such a state using a plasma CVD apparatus, the source 2A and the source wiring 8A are formed on the silicon nitride film 7. A contact hole for connection is formed. Subsequently, Al containing 1% of Si
The film is deposited to a film thickness of about 3000 angstrom and patterned to form the source wiring 8A and the second auxiliary capacitance electrode 8B as shown in FIG.

[0045] Further, after the film thickness by using a plasma CVD device to deposit a SiO ₂ film 9 of approximately 4000 angstroms, the SiO ₂ film 9 such as shown in FIG. 8, upper gate electrode 6 and the second auxiliary capacitance Electrode 8B and gate wiring 10A
A contact hole for connecting the drain 2B and the metal wiring 10B,
A contact hole for connecting the first auxiliary capacitance electrode 2D and the second metal wiring 10C is formed. Subsequently, an Al film containing 1% of Si is deposited to a film thickness of about 3000 angstroms, and is patterned to form a gate wiring 10A, a first metal wiring 10B, and a second wiring as shown in FIG.
The metal wiring 10C is formed.

Then, after depositing a SiO ₂ film 11 having a film thickness of about 2000 angstroms using a plasma CVD apparatus, as shown in FIG. 9, the first metal wiring 10B and the second metal wiring 10B are formed on the SiO ₂ film 11. Wiring 10C and picture element electrode 12
A contact hole for connecting with is formed.

Finally, the transparent electrode 12 is formed with a film thickness of about 1000 Å using a sputtering apparatus as shown in FIGS.

After the above steps, a silicon nitride film, a polyimide film or the like is deposited as a protective film to form an active matrix substrate, which is bonded to a counter substrate to form a liquid crystal display device.

In the active matrix substrate formed as described above, as shown in FIG. 9 (a), the auxiliary capacitance includes the first auxiliary capacitance electrode 2D and the second auxiliary capacitance electrode 8B. In between, an auxiliary capacitance is formed with the first insulating film 3 and the silicon nitride film 6 as dielectric layers.

In the active matrix substrate of this embodiment, since the dielectric layer of the auxiliary capacitance can be formed thin, not only the aperture ratio of the picture element is not lowered, but also the self-alignment method is used, so that the gate electrode 4 is used. And the source 2A, and the overlap between the gate electrode 4 and the drain 2B are extremely small, and the adverse effect on the image quality due to the parasitic capacitance is eliminated.

Further, since the covering member 5 is formed on the side surface of the layer forming the source 2A, the drain 2B and the channel 2C and the side surface of the first auxiliary capacitance 2D, electric field concentration is less likely to occur, and leakage and short circuit occur. Can be reduced.

Further, since the polycrystalline silicon thin film transistor and the storage capacitor can be manufactured in the same process, it is possible to shorten the process time and the cost.

<Second Embodiment> FIG. 12 is a plan view of a main portion of an active matrix substrate according to a second embodiment of the present invention, and FIGS. 13 to 19 show a manufacturing process of the active matrix substrate according to the present embodiment. It is sectional drawing shown. 13A to FIG. 13A to FIG. 19B are a sectional view taken along the line AA, a sectional view taken along the line BB, and a sectional view taken along the line CC of FIG. 12, respectively.

This active matrix substrate is shown in FIG.
As shown in, the source wiring 30A and the gate wiring 28A to which the image signal is sent are vertically and horizontally arranged on the glass substrate 21, and the pixel is provided in a portion surrounded by the adjacent source wiring 30A and the adjacent gate wiring 28A. Has been formed. At the intersection of the source wiring 30A and the gate wiring 28A, the source 22A is connected to the source wiring 30A as shown in FIG. 19B, and the upper layer is formed on the gate wiring 28A as shown in FIG. 19C. A thin film transistor is formed in which the lower layer gate electrode 24 is connected via the gate electrode 26. In the drain 22B of this thin film transistor,
As shown in FIG. 19B, the pixel electrode 32 is connected via the first metal wiring 30B. The picture element electrode 32 is connected to the first auxiliary capacitance electrode 22D via the second metal wiring 30C as shown in FIG. 19 (a). A second auxiliary capacitance electrode 28B is formed on a part of the gate wiring 28A, and the second auxiliary capacitance electrode 28B and the first auxiliary capacitance electrode 22D are provided between the second auxiliary capacitance electrode 28B and the first auxiliary capacitance electrode 22D as shown in FIG. The first insulating film 23 and the silicon nitride film 26 overlap each other.

A method of manufacturing the liquid crystal display device having the above structure will be described.

First, the cleaned glass substrate 21 is set in the plasma CVD apparatus, and the temperature of the substrate 21 is set to 400.
The SiH ₄ gas diluted with H ₂ is decomposed by heat and plasma while being kept at ˜600 ° C. to form an amorphous Si film having a film thickness of about 1000 Å on the substrate 21. Subsequently, the deposited amorphous Si film is annealed at 600 ° C. for 50 hours in a vacuum or in an atmosphere of an inert gas to form a polycrystalline Si film 22a shown in FIG. Further subsequently, a SiO ₂ film 23a having a film thickness of about 1000 Å serving as the first insulating film 23 is formed on the polycrystalline Si film 22a by an atmospheric pressure CVD apparatus. In the above steps, when transferring the substrate 21 or the like from the plasma CVD apparatus for forming the polycrystalline Si film 22a and the SiO ₂ film 23a to the annealing furnace and from the annealing furnace to the atmospheric pressure CVD apparatus, a vacuum is used. Alternatively, the substrate 21 and the like are not exposed to the atmosphere at this time because the load lock chamber is placed in an inert gas atmosphere.

Next, low pressure CVD is performed on the SiO ₂ film 23a.
Depending on the device, the film thickness of the lower gate electrode 24 is about 100.
A polycrystalline Si film 24a of 0 angstrom is formed.
FIG. 13 shows a state in which the substrate 21 is manufactured up to this point.
A three-layer laminated film is formed on top.

This three-layered film is simultaneously etched by a resist pattern formed in the shape of a portion for forming an auxiliary capacitor and a thin film transistor, and processed into an island-shaped pattern as shown by hatching in FIG. The auxiliary capacitance portion S2 is formed. Reactive ion etching is used for this etching, and the side surfaces of the island-shaped polycrystalline Si film 22a, SiO ₂ film 23a, and polycrystalline Si film 24a after etching are different so as to be perpendicular to the surface of the substrate 21. Perform anisotropic etching. In the above etching, the etching gas is polycrystalline Si film 2
A mixed gas of SF ₆ and CCl ₄ is used for 2a and 24a,
CH ₃ gas is used for the SiO ₂ film 23a. Next, on the entire surface of the substrate 21 including the island-shaped pattern made of three laminated films,
As shown in FIG. 15, an SiO ₂ film 25a having a film thickness of about 5000 angstrom is formed by using an atmospheric pressure CVD apparatus. After that, by performing anisotropic etching by the reactive ion etching method, as shown in FIG. 16, the covering member 25 is formed while leaving the SiO ₂ film 25a only on the side surface of the island pattern.

Then, a polycrystalline Si film to be the upper gate electrode 26 is formed on the surface of the substrate 21 by a low pressure CVD apparatus to a thickness of about 2.
Deposit with a film thickness of 000 Å. Then, using a resist pattern formed in the shape of the upper gate electrode 26 as shown in FIG. 21, a pattern of the upper gate electrode 26 and a pattern of the lower gate electrode 24 are formed by reactive ion etching as shown in FIG. Are formed at the same time.

After the element which becomes a predetermined impurity is ion-implanted on the substrate 21 in such a state, activation anneal of the element is performed, so that the polycrystalline Si films 24 and 26 and the polycrystalline Si films 22A and 22B are formed. , 22C, n-type or p
Then, the upper layer gate electrode 26, the lower layer gate electrode 24, the source 22A, the drain 22B, and the first auxiliary capacitance electrode 22D are formed by using a type semiconductor to have a constant conductivity type and a low resistance. Here, the upper layer gate electrode 26 and the lower layer gate electrode 24 function as a mask for forming the channel 22C of the transistor. Up to this point, the manufacturing process is the same as that of the first embodiment. Next, after depositing a silicon nitride film 27 having a film thickness of about 500 angstroms on the substrate 21 in such a state by using a plasma CVD apparatus, as shown in FIG. 18, the upper layer gate electrode is formed on the silicon nitride film 27. A contact hole for connecting 26 and the gate wiring 28A is formed. Then, an Al film containing 1% of Si is applied to about 3000.
The second auxiliary capacitance electrode 28B is deposited with a film thickness of angstrom and patterned as shown by the diagonal lines in FIG.
A gate wiring 28A which also serves as the gate wiring is formed.

Further, after depositing a SiO ₂ film 29 having a film thickness of about 4000 angstroms using a plasma CVD apparatus, the source 22A and the source wiring 30A are formed on the SiO ₂ film 29 and the silicon nitride film 27 as shown in FIG. And a contact hole for connecting the drain 22B and the first metal wiring 30B, and a first auxiliary capacitance electrode 22D and the second metal wiring 30.
A contact hole for connecting with C is formed. Then, an Al film containing 1% of Si is deposited to a film thickness of about 3000 angstroms, and is patterned to form a film shown in FIG.
As shown in (a) and (b), the source wiring 30A, the first
The metal wiring 30B and the second metal wiring 30C are formed.

Then, after depositing a SiO ₂ film 31 having a film thickness of about 2000 angstroms using a plasma CVD apparatus, as shown in FIGS.
The first metal wiring 30B and the second metal wiring 3 on the ₂ film 31.
A contact hole for connecting 0C and the pixel electrode 32 is formed.

Finally, a sputtering device is used to form a transparent electrode 32 with a film thickness of about 1000 Å, as shown in FIGS.

After the above steps, a silicon nitride film, a polyimide film or the like is deposited as a protective film to form an active matrix substrate, which is then bonded to a counter substrate to form a liquid crystal display device.

In the active matrix substrate formed as described above, as shown in FIG.
The auxiliary capacitance has the first insulating film 23 and the silicon nitride film 26 as a dielectric layer between the first auxiliary capacitance electrode 22D and the second auxiliary capacitance electrode 28B which is a part of the gate wiring 28A. Has been formed.

Also in the active matrix substrate of the present embodiment, since the dielectric layer of the auxiliary capacitance can be formed thin, not only the aperture ratio of the picture element is not lowered, but also the self-alignment method is used, so that the gate electrode is used. 24 and source 22A
And the overlap between the gate electrode 24 and the drain 22B are extremely small, and the adverse effect on the image quality due to the parasitic capacitance is eliminated.

Furthermore, the side surfaces of the layers forming the source 22A, the drain 22B and the channel 22C and the first auxiliary capacitance 2
Since the covering member 25 is formed on the side surface of 2D, electric field concentration is less likely to occur, and the occurrence of leaks and short circuits can be reduced.

Further, since the polycrystalline silicon thin film transistor and the storage capacitor can be manufactured in the same process, the process time and the cost can be reduced.

[0069]

As is apparent from the above description, according to the active matrix substrate and the method of manufacturing the same of the present invention, the polycrystalline silicon thin film transistor and the auxiliary capacitor can be manufactured in the same process, which shortens the process time and reduces the cost. Is possible. Further, since the self-alignment method is used for manufacturing the thin film transistor, the parasitic capacitance of the thin film transistor becomes extremely small and the adverse effect on the image quality can be suppressed. Further, the side surface of the first auxiliary capacitance electrode and the side surface of the layer forming the source, drain, and channel of the thin film transistor are reinforced by the covering member so that the electric field concentration is likely to occur, and the occurrence of leakage and short circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view showing an active matrix substrate of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing one manufacturing process of the active matrix substrate shown in FIG.

FIG. 3 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 4 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 5 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 6 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 7 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 8 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

9 is a cross-sectional view of the active matrix substrate shown in FIG.

10 is a plan view showing an island-shaped pattern of the three-layered film shown in FIG.

11 is a plan view showing patterns of an upper layer gate electrode and a first auxiliary capacitance electrode of the active matrix substrate shown in FIG.

FIG. 12 is a plan view showing an active matrix substrate of a second embodiment of the present invention.

13 is a cross-sectional view showing one manufacturing process of the active matrix substrate shown in FIG.

FIG. 14 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 15 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

16 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 17 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

FIG. 18 is a cross-sectional view showing another manufacturing process of the active matrix substrate shown in FIG.

19 is a cross-sectional view of the active matrix substrate shown in FIG.

FIG. 20 is a view of the active matrix substrate 3 shown in FIG.
It is a top view which shows the island-shaped pattern of a laminated film.

21 is a plan view showing a pattern of an upper layer gate electrode of the active matrix substrate shown in FIG.

22 is a plan view showing patterns of gate wirings and second auxiliary capacitance electrodes of the active matrix substrate shown in FIG.

FIG. 23 is an equivalent circuit diagram of a basic structural unit corresponding to one picture element in a liquid crystal display device having a storage capacitor.

FIG. 24 is a cross-sectional view showing the manufacturing process of the conventional active matrix substrate.

FIG. 25 is a cross-sectional view showing the process of manufacturing another conventional active matrix substrate.

[Explanation of symbols]

 1, 21 Glass substrate 2A, 22A Source 2B, 22B Drain 2C, 22C Channel 2D, 22D First auxiliary capacitance electrode 3, 23 First insulating film 4, 24 Lower layer gate electrode 5, 25 Covering member 6, 26 Upper layer gate Electrode 8A, 30A Source wiring 10A, 28A Gate wiring 12, 32 Picture element electrode

Claims (6)

[Claims] 1. An insulating substrate, a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to intersect with each other, two adjacent source wirings, and two adjacent gate wirings. A pixel electrode formed in a surrounded portion and a gate electrode provided near an intersection of the source wiring and the gate wiring and electrically connected to the gate wiring on one side with an insulating film interposed therebetween. And a thin film transistor in which a channel is formed on the other side by self-alignment with the gate electrode, and a source and a drain are formed in another portion, and the thin film transistor is separated and mainly in a portion other than the pixel electrode. A first auxiliary capacitance electrode formed of the same material as the source and electrically connected to the pixel electrode, and opposed to the first auxiliary capacitance electrode with an insulating film interposed therebetween. To form a storage capacitor, It is electrically connected to the over preparative wiring, the active matrix substrate and a second auxiliary capacitor electrode made of the source wiring and the same material. 2. An insulating substrate, a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to intersect each other, two adjacent source wirings, and two adjacent gate wirings. A pixel electrode formed in a surrounded portion and a gate electrode provided near an intersection of the source wiring and the gate wiring and electrically connected to the gate wiring on one side with an insulating film interposed therebetween. And a thin film transistor in which a channel is formed on the other side by self-alignment with the gate electrode, and a source and a drain are formed in another portion, and the thin film transistor is separated and mainly in a portion other than the pixel electrode. A first auxiliary capacitance electrode formed of the same material as the source and electrically connected to the pixel electrode, and opposed to the first auxiliary capacitance electrode with an insulating film interposed therebetween. To form a storage capacitor, Active matrix substrate and a second auxiliary capacitance electrode formed of a part of the gate wiring. 3. The active matrix according to claim 1, further comprising a covering member made of an insulating material and covering side surfaces of the source, the channel and the drain and a side surface of the first auxiliary capacitance electrode. substrate. 4. An insulating substrate, a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to intersect with each other, and two adjacent source wirings and two adjacent gate wirings. A pixel electrode formed in a surrounded portion, a thin film transistor formed in the vicinity of an intersection of the source wiring and the gate wiring, and the thin film transistor are separated and mainly formed in a portion other than the pixel electrode. A method of manufacturing an active matrix substrate, comprising: a first auxiliary capacitance electrode that is formed and a second auxiliary capacitance electrode that faces the first auxiliary capacitance electrode with an insulating film interposed therebetween to form an auxiliary capacitance. A first semiconductor layer, a first insulating film, and a second semiconductor layer are formed in this order from the substrate side in the transistor formation region and the auxiliary capacitance formation region on the substrate to form two island-shaped regions. A step of forming a laminate of Forming a third semiconductor layer on the substrate covering the layered body, and removing a part of the second semiconductor layer and a part of the third semiconductor layer to form a gate electrode semiconductor layer. A step of forming the semiconductor layer for gate electrode, and an impurity is injected into the first semiconductor layer by using the semiconductor layer for gate electrode as a mask, and the semiconductor layer for gate electrode is used as a gate electrode, and the first semiconductor Forming a layer as the source and drain of the transistor and the first auxiliary capacitance electrode, and simultaneously forming the source wiring and the second auxiliary capacitance electrode on the substrate on which the source and the drain are formed. Forming step, electrically connecting to the second auxiliary capacitance electrode to form the gate wiring, and electrically connecting to the first auxiliary capacitance electrode to form the pixel electrode Active matrix substrate including the steps of Manufacturing method. 5. An insulating substrate, a plurality of source wirings and a plurality of gate wirings provided on the substrate so as to intersect with each other, two adjacent source wirings and two adjacent gate wirings. A pixel electrode formed in a surrounded portion, a thin film transistor formed in the vicinity of an intersection of the source wiring and the gate wiring, and the thin film transistor are separated and mainly formed in a portion other than the pixel electrode. A method of manufacturing an active matrix substrate, comprising: a first auxiliary capacitance electrode that is formed and a second auxiliary capacitance electrode that faces the first auxiliary capacitance electrode with an insulating film interposed therebetween to form an auxiliary capacitance. A first semiconductor layer, a first insulating film, and a second semiconductor layer are formed in this order from the substrate side in the transistor formation region and the auxiliary capacitance formation region on the substrate to form two island-shaped regions. A step of forming a laminate of Forming a third semiconductor layer on the substrate covering the layered body, and removing a part of the second semiconductor layer and a part of the third semiconductor layer to form a gate electrode semiconductor layer. A step of forming the semiconductor layer for gate electrode, and an impurity is injected into the first semiconductor layer by using the semiconductor layer for gate electrode as a mask, and the semiconductor layer for gate electrode is used as a gate electrode, and the first semiconductor Forming a layer as the source and drain of the transistor and the first auxiliary capacitance electrode, and simultaneously forming the gate wiring and the second auxiliary capacitance electrode on the substrate on which the source and the drain are formed. A method of manufacturing an active matrix substrate, comprising: a forming step; and a step of electrically connecting to the first auxiliary capacitance electrode to form the pixel electrode. 6. The method for manufacturing an active matrix substrate according to claim 4, further comprising a step of forming a covering member for covering the side surface of the laminated body.