JPH06149721A - Connection board recognizing device for computer system - Google Patents

Abstract

(57) [Abstract] [Purpose] It is intended to provide a connection board recognition device that can automatically recognize a peripheral board to be connected, which is used in a computer system that expands functions by connecting a peripheral board to a CPU board. It is to provide a connection board recognition device capable of automatically recognizing a peripheral board with a simple process and a simple configuration. [Structure] A dedicated signal 8 for detecting whether or not a peripheral board 4 is connected and a flag register 5 to which an address 7 is assigned for each bit are provided on the CPU board 3, and a dedicated signal 8 is provided for each bit of the flag register 5. The address 7 of the connected peripheral board 4 is specified by reflecting the state of the dedicated signal 8 and the data for identifying the connected peripheral board 4 is referred to the peripheral board 4 or the CPU board 3 by referring to this address 7. It is configured to read from the provided memory 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection board recognizing device used in a small computer system or the like in which various peripheral boards are connected to a CPU board so that the functions can be expanded. The present invention relates to a connection board recognition device capable of automatically recognizing and discriminating a peripheral board that has been created and obtaining information necessary for an interface or the like.

[0002]

2. Description of the Related Art Conventionally, an iPSB bus (Intel parallel system bus), which supports the interconnection function of Intel Multibus II, is known as a connection board recognition device of this type. In the iPSB bus, the CSM (central service module, function in the backplane slot 0 board) uses the signal of the bus arbitration ID (bus request level, 4 lines) at the time of system initialization, and the backplane (motherboard) A card slot ID is assigned to the agent (board) of each slot. This card slot ID becomes the identification number of each agent. The agent of each slot is always assigned a CSM individually when the system is initialized.
Must be taken in (memorized).

The card slot ID is stored in a register called an interconnection address held by the agent of each slot. The interconnection address consists of two parts, a card slot ID and a register number that stores vendor identification information, etc., the card slot ID is 5 bits, the register is 9 bits (512 register numbers can be used), and unused 2 It has a total of 16 bits.

In the operation for board identification, the agent of each slot reflects the card slot ID assigned by the CSM at system initialization in the card slot ID of the interconnection address. The CSM makes it possible to access the interconnection address by selecting the interconnection space from the four spaces of the interconnection space, the memory space, the I / O space, and the message space by the two address space identification numbers of the iPSB bus. The agent is identified by the card slot ID, and the information (register of the number shown in the interconnection address) of the individual agent of each slot is obtained.

[0005]

However, the present inventors have revealed that the above-mentioned technique has the following problems. That is, in the above-described conventional connection board recognition device, the CPU board side (referring to the system management function in the CPU board) accesses the peripheral board, confirms the presence or absence of connection, and then stores it in the peripheral board side. In order to obtain information such as the type of board being used, it is necessary to perform complicated processing such as switching the address space for access.

Therefore, in a system of a certain scale (workstation or the like) using a general-purpose bus, it is not so burdensome to mount the circuits and the like necessary for realizing the functions described above on the peripheral board. In equipment-embedded board computer systems where downsizing is important, circuits related to the system such as the interface between the CPU board and peripheral boards are minimized,
It is necessary to give priority to functions such as I / O.

The present invention has been made in view of the above circumstances, and corresponds to a device-incorporated computer system in which miniaturization is important, and therefore simplifies the processing necessary for automatic recognition, circuits, etc. It is an object of the present invention to provide a connection board recognition device capable of minimizing the number of connections. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the connection board recognition device of the present invention is
In a computer system configured by connecting a CPU board on which a CPU is mounted and a plurality of peripheral boards on which attached circuits are mounted, the identification information of the peripheral board is stored in a memory, and whether or not the peripheral board is connected is determined. The address of the connected peripheral board is individually detected and discriminated, and the identification information of the connected peripheral board is read from the memory by referring to this address.

The connected board recognition device of the present invention is configured in such a manner that a memory is provided on the CPU board, and that each peripheral board is provided with a memory to store the identification information of the peripheral board itself. You can

[0010]

The connected board recognition device of the present invention detects whether or not the peripheral board is connected and reflects it in the flag register or the like.
An address in which the information of the peripheral board is stored is assigned to each bit of this flag register, and the identification information stored in the memory is read by this address, that is, by referring to this address. Therefore, it is possible to easily obtain the identification information necessary for the interface or the like regarding the connected peripheral board without performing complicated processing and without providing a large-scale circuit.

Further, according to the present invention, each peripheral board is provided with a memory and the identification information of the peripheral board itself is recorded, so that the CPU board does not need a large memory and the memory capacity is large. Therefore, the restrictions imposed by can be reduced and great versatility can be obtained.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 show a connection board recognition device of a computer system according to an embodiment of the present invention, FIG. 1 is a schematic diagram of the computer system, and FIG. 2 is a schematic view of a connection state between a CPU board and peripheral boards. FIG. 3 is a block diagram schematically showing the relationship between each bit of the flag register and the ID number of each peripheral board.

In FIGS. 1, 2 and 3, 3 is a CP
C equipped with U3a and input / output circuit (I / O) 3b
PU boards, 4 ₀ to 4 _n is a peripheral circuit is included (hereinafter represented by reference character 4a) or the like is a peripheral board that is provided, and these CPU boards 3 and peripheral board 4 (hereinafter represented with no subscript number ) and it is assembled by stacking via the connector 1 ₁ to 1 _n so as to be parallel at a mutually appropriate intervals. As described below, each peripheral board 4
Indicates that the peripheral circuits 4a are connected to the connectors 1 ₀ to 1 _n (hereinafter,
(Represented by a number without a subscript) is connected to the input / output circuit 3b of the CPU board 3.

In this embodiment, a computer system having eight peripheral boards, that is, a computer system with n = 7 will be described in relation to the number of bits of a flag register which will be described later, but more peripheral boards are provided. The present invention can be applied to a computer system.

As shown in FIG. 2, the CPU board 3 includes a microprocessor (CPU) 3a and an input / output circuit (I / I).
O) 3b are connected to each other by a bus 11, and system buses 12 _{0 to} 12 ₇ (hereinafter represented by numbers without subscripts) are connected from the input / output circuit 3b to the peripheral circuit 4a of each peripheral board 4 respectively. Is routed through. As will be described later, these system buses 12 connect the input / output circuit 3b and the peripheral circuit 4a when the CPU board 3 and the peripheral board 4 are assembled and the connector 1 becomes conductive.

Further, the CPU board 3 is provided with eight signal lines 8 ₀ to 8 ₇ (hereinafter represented by numbers without suffixes) having resistances R _{0 to} R _n , and these signal lines 8 are connected to the system bus. It is routed in parallel with 12 toward each peripheral board 4 via the connector 1. In these signal lines 8, one end of the resistor R is connected to the power supply Vcc, the other end of the resistor R is connected to the input / output circuit 3b, and the other end of the resistor R is grounded in each peripheral board 4. These signal lines 8 are electrically connected between the CPU board 3 side part and the peripheral board 4 side part by the connection of the connector 1, and the power supply potential (high “H” level), the connector when the peripheral board 4 is not connected to the CPU board 3 When the peripheral board 4 is connected to the CPU board 3 by 1, it becomes the ground potential (low "L" level). The potential state of these signal lines 8 is read by the CPU 3a via the input / output circuit 3b.

The CPU 3a has a flag register 5 which reflects the potential state on the other end side of the resistance R of each signal line 8, and
The CPU board 3 is provided with a data memory 9 (see FIG. 3) for storing data regarding the peripheral board 4. As shown in FIG. 3, the flag register 5 has 8 bits corresponding to eight signal lines 8, that is, eight peripheral boards 4, and each bit has a predetermined address 7 (A,
B, ..., H) are assigned. In the flag register 5, the bits to which the addresses A, B, ..., H are assigned correspond to the signal lines 8 ₀ , 8 ₁ , ..., 8 _7, and the potential of the signal line 8 wired to each peripheral board 4 is set. The "H" level is represented by 0 and the "L" level is represented by 1, and in FIG.
It indicates that the peripheral board 4 corresponding to the bit of the address is connected.

The data memory 9 is composed of a non-volatile memory or the like, and the data of the peripheral board 4 (in this embodiment, respectively) corresponding to the areas designated by the addresses 7 (A, B, ..., H) described above. (ID number) is stored. In this embodiment, the data memory 9 stores the ID number in 8 bits. The number of signal lines 8 is 8 and the ID number is stored in the memory 9
In the computer system of this embodiment, which stores 8 bits in 8 bits, a maximum of 8 peripheral boards 8 can be recognized, and the required memory capacity is 1 byte for the flag register 5 and 8 bytes for the memory 9.

In this embodiment, since the peripheral board 4 is connected to the CPU board 3 by the connector 1, the potential of the corresponding signal line 8 becomes "L" level, for example, the peripheral boards 4 ₀ , 4 ₂ , 4 _{When 4} is connected, the signal lines 8 ₀ , 8 ₂ ,
8 ₄ becomes the “L” level, and as shown in FIG. 3, the corresponding bits of the flag register 5, that is, the bits to which the addresses 7 of A, C, and E are assigned reflect the levels of these signal lines 8. It becomes 1 ”. Therefore, the CPU on the CPU board 3 refers to the addresses A, C, E corresponding to the "1" bit of the flag register 5, and based on these addresses A, C, E, the memory 9 to the peripheral board 4 ₀ , 4 ₂ , 4
₄ ID numbers can be read.

As described above, in this embodiment, the signal line 8, the flag register 5 and the memory 9 are provided, and the signal line 8
The presence / absence of the connection of the peripheral board 4 is detected by this, and the potential of the signal line 8 is reflected in the bit of the flag register 5. Then, the address 7 assigned to each bit of the flag register 5 is referred to and the I of the peripheral board 4 is read from the memory 9.
The D number can be read. Therefore, no special circuit is required, and the I of the peripheral board 4 can be easily processed.
Can recognize D number. Incidentally, in the above-mentioned embodiment, the ID
Since the number is stored in 8 bits, 256 general-purpose boards can be registered in the memory 9.

FIG. 4 shows a connection board recognition device according to another embodiment of the present invention. In the following, the same parts as those in the above-described embodiment are designated by the same reference numerals, and the description and illustration thereof will be omitted.

In this embodiment, each peripheral board 4 ₀ , 4 ₁ ,
, 4 ₇ are assigned addresses 7 (A, B, ..., H) respectively to provide memories 9 ₀ , 9 ₁ , ..., 9 _7.
0 , 9 ₁ , ..., 9 ₇ are connected to the peripheral boards 4 ₀ , 4 ₁ ,
..., store the ID number of 4 ₇ . Then, in each bit of the flag register 5, each peripheral board 4 ₀ , 4 ₁ , ..., 4 ₇
Of memory 9 _0, 9 _1, ..., 9 ₇ can be specified address 7
(A, B, ..., H) are assigned.

Also in this embodiment, when the peripheral board 4 is connected, the signal line 8 becomes "L" level, and the bit corresponding to the peripheral board 4 of the flag register 5 becomes "1". Therefore, the CPU 3a causes the flag register 5 to read "1".
Peripheral board 4 with reference to address 7 corresponding to the bit
The ID number stored in the memory 9 is read out. And
In this embodiment, since each peripheral board 4 stores its own ID number, the CPU board 3 does not need a dedicated memory and can be assigned an ID number without being restricted by the memory capacity. , High versatility can be obtained.

In the embodiment described above, the peripheral board 4
Although the ID number is exemplified as the data relating to the above, it is possible to store other data relating to the I / O or access.

In the above-mentioned embodiment, the computer system in which the peripheral board and the CPU board are stacked and connected is exemplified, but the present invention is also applied to the one in which the CPU board and the peripheral board are connected in parallel to the mother board. can do. Further, in this aspect, the memory 9 can be provided on the motherboard.

[0026]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, according to the connection board recognition device of the computer system of the present invention, the presence or absence of connection of each peripheral board is individually detected to search the data address of the peripheral board, and the data of the peripheral board is obtained based on this data address. Since it is configured to read out, the information of the connection board can be obtained by a simple process without providing a complicated circuit, and it can be easily applied to a computer system that is required to be downsized.

In particular, the present invention is configured to record the data of the peripheral board itself on the peripheral board,
The restrictions on the data to be recorded can be reduced, and high versatility can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a connection board recognition device of a computer system according to an embodiment of the present invention.

FIG. 2 is a diagram schematically showing a connection state between a CPU board and peripheral boards of the same connection board recognition device.

FIG. 3 is a diagram schematically showing a data storage mode of the connection board recognition device.

FIG. 4 is a diagram schematically showing a data storage mode of a connection board recognition device of a computer system according to another embodiment of the present invention.

[Explanation of symbols]

 1 Connector 3 CPU Board 4 Peripheral Board 5 Flag Register 6 Address 7 Signal Line 9 Memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryoichi Sano 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Ltd. Musashi Factory

Claims (3)

[Claims] 1. A computer system configured by connecting a CPU board on which a CPU is mounted and a plurality of peripheral boards on which attached circuits are mounted, in which identification information of the peripheral board is stored in a memory and the peripheral board is also stored. The presence or absence of the connection of the peripheral board is individually detected to determine the address of the connected peripheral board, and the identification information of the connected peripheral board is read from the memory by referring to this address. Computer system connection board recognition device. 2. The connection board recognition device for a computer system according to claim 1, wherein the memory is provided on the CPU board. 3. The connection board recognition device for a computer system according to claim 1, wherein the memory is provided on the peripheral board.