JPH06103790A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Objective] To provide a flash memory with low current consumption and reduced erase time. [Structure] In the first erase cycle, four sub-arrays 1a, 1b, 1c and 1d each have four groups G.
1, G2, G3 and G4 are configured. Group G1, G
Erase pulses are sequentially applied to the sub-arrays 1a, 1b, 1c and 1d of 2, G3 and G4. In the second erase cycle, the two sub-arrays 1a and 1b form the group G1 and the two sub-arrays 1c and 1d form the group G2. First, the sub-arrays 1a, 1 that make up the group G1
The erase pulse is applied to b simultaneously, and then the erase pulse is applied to the sub-arrays 1c and 1d forming the group G2 at the same time. In the third and subsequent erase cycles, the four sub-arrays 1a, 1b, 1c and 1d form one group G1. Sub-arrays 1a, 1 forming the group G1
Erase pulses are simultaneously applied to b, 1c, and 1d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an electrically writable and erasable nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Semiconductor memory devices include volatile memories such as DRAM (dynamic random access memory) and SRAM (static random access memory), and non-volatile memories. The data stored in the volatile memory is
Everything disappears when the power is turned off. However, the data stored in the non-volatile memory does not disappear even when the power is turned off. A typical example of such a nonvolatile semiconductor memory device is PRO.
M (programmable read only)
memory). The PROM is a semiconductor memory device in which information can be written by the user. In this PROM, the written information can be electrically erased and the information can be rewritten any number of times.
erasable and programmable
There is a ROM). EEPROM capable of electrically erasing the stored data of all memory cells collectively
Is called flash memory.

FIG. 11 is a schematic block diagram showing the basic structure of a conventional flash memory. Referring to FIG.
The flash memory includes a memory array 1, a row decoder 4, a Y gate 2 and a column decoder 5.

The memory array 1 includes a plurality of memory cells MC arranged in a matrix in the row and column directions. Each memory cell MC is connected to corresponding bit line 30 and word line 50 in memory array 1. For each memory cell MC, a memory transistor capable of storing charges in the floating gate is used.

FIG. 12 shows a memory transistor structure.
FIG. Referring to FIG. 12, a memory transistor
Is the control gate 200 and the floating gate.
210 and the N-type region 2 formed on the P-type substrate 240
20 and 230 and an insulating layer 250. Floate
The swing gate 210 is an N-type region on the P-type substrate 240.
Insulating layer 2 so as to extend over 220 and N-type region 230.
Formed through 50. Control gate 200
Through the insulating layer 250 on the floating gate 210.
Formed. Control gate 200 and flow
Each of the starting gates 210 is made of polysilicon.
Is formed. The insulating layer 250 is SiO ₂Oxidation such as
Formed by a film. P-type substrate 240 and floating
The thickness of the oxide film 250 between the gate gate 210 and the gate gate 210 is usually 10
It is about 0Å and very thin. Control gate 200
Is connected to the corresponding word line 50 in FIG.
It One of the two N-type regions 220 is the MOS transistor.
The corresponding drain in FIG. 11 is used as the drain of the transistor.
Connected to the output line 30. The other N-type region 230
Is the source of this MOS transistor in FIG.
Connect to the source line 80 common to all memory cells MC
Will be continued. The P-type substrate 240 is grounded.

At the time of writing data, the control gate 2
00 and drain 220 are applied with a high voltage of about 12 V and about 6 V via the word line 50 and the bit line 30, respectively, while the source 230 is grounded via the source line 80. When a high voltage pulse is applied to the drain 220 and the source 230 is grounded, channel hot electrons are generated near the interface between the drain 220 and the P-type substrate 240. As a result, a current flows to the drain 220. On the other hand, the control gate 20
Since a high voltage pulse is applied to 0 as well, hot electrons are accelerated by the electric field from the control gate 200, and the floating gate 210 and the P-type substrate 240 are accelerated.
It is injected into the floating gate 210 through the thin oxide film 250 between.

The charges injected into the floating gate 210 cannot escape because the floating gate 210 is electrically insulated by the oxide film 250. Therefore, the electrons once injected into the floating gate 210 are accumulated in the floating gate 210 without flowing out of the floating gate 210 for a long time even after the power is turned off. The state where electrons are stored in the floating gate 210 corresponds to data “0”, and the state where electrons are not stored in the floating gate 210 corresponds to data “1”.
Therefore, the data stored in the memory cell MC is retained even after the power is turned off. Now, floating gate 21
When electrons are accumulated at 0, the electric field from the accumulated electrons causes the threshold value seen from the control gate to shift in the positive direction. Therefore, a negative polarity inversion layer is unlikely to occur in the channel region. Therefore, when electrons are accumulated in the floating gate 210, the gate voltage (threshold voltage of this transistor) required to generate a channel in this MOS transistor becomes the floating gate 2.
This is higher than the case where no electrons are stored in 10. In other words, the inversion layer does not occur in the channel region unless a voltage higher than that in the case where electrons are not accumulated in the floating gate 210 is applied to the control gate 200.

When the stored data is erased, a high voltage is applied to the source 230 via the source line 80, while
The control gate 200 is grounded via the word line 50. As a result, a high electric field with the source 230 on the high potential side is applied between the floating gate 210 and the source 230. As a result, a tunnel phenomenon occurs in the oxide film 250 that insulates the floating gate 210 and the source 230, and a current (tunnel current) that flows between the floating gate 210 and the source 230 occurs.
That is, the floating gate 210 to the source 23
Electrons flow out to 0 through the oxide film 250. As a result, the electrons accumulated in floating gate 210 are removed, and the threshold voltage of this MOS transistor is lowered. As shown in FIG. 11, since the source line 80 is commonly connected to the sources of the memory cells MC, the stored data of all the memory cells MC in the memory array 1 in FIG. 11 are erased collectively.

At the time of data reading, the control gate 2
00 and drain 220 respectively via the corresponding word line 50 and bit line 30 to the power supply voltage (typically 5
V) or a voltage relatively close thereto is applied, while
The source 230 is grounded via the source line 80. If electrons are not accumulated in the floating gate 210 (stored data is "1"), the threshold voltage of this MOS transistor is low, and therefore the control gate 20
A power supply voltage applied to 0 creates a channel between the source 230 and the drain 220. However, if electrons are accumulated in the floating gate 210 (if the stored data is “0”), the threshold voltage of this MOS transistor is high, so that even if the power supply voltage is applied to the control gate 200, the source 230 -No channel occurs between drains 220. Therefore, the MOS transistors forming the memory cell in which the stored data is "1" are turned on at the time of data reading, and the current flows from the corresponding bit line 30 to the source line 80. However, since the MOS transistor forming the memory cell in which the stored data is "0" is in the OFF state even during the data reading, the current flowing from the corresponding bit line 30 to the source line 80 does not occur. Therefore, at the time of data reading, the sense amplifier detects whether or not a current flows through the bit line corresponding to the memory cell from which data is to be read. Based on the result of this detection, it is determined whether the stored data is "1" or "0".

However, if the potential applied to the bit line 30 during data reading is too high, the floating gate 21
Since a high electric field is applied to the oxide film 250 between 0 and the drain 220, the electrons accumulated in the floating gate 210 escape to the drain 220 side. for that reason,
The potential applied to the bit line 30 is about 1 to 2V.
Therefore, the current flowing through the memory cell whose stored data is "1" at the time of data reading is small. Therefore, a current sense amplifier is used to detect this current.

Referring again to FIG. 11, address input terminals A0-AK receive externally applied address signals. The address signal is applied to the memory cell M in the memory array 1.
This is a signal instructing which of C is to read or write data. Address buffer 6
Applies the applied address signal to row decoder 4 and column decoder 5 by buffering it.

The input / output buffer 9 receives input data and output data.
Input / output terminal I / O for receiving force data ₀~ I / O_NConnected to
To be done. The input / output buffer 9 is an input / output terminal I / O₀~ I
/ O _NWrite data externally applied to the write circuit 7.
give. Further, the input / output buffer 9 includes the sense amplifier 8
The data output from the I / O terminal I is used as read data.
/ O₀~ I / O_NDerive to.

Write circuit 7 applies to Y gate 2 a voltage according to the write data applied from input / output buffer 9.
The sense amplifier 8 detects the output of the Y gate 2 and applies a signal voltage corresponding to the data “0” or “1” to the input / output buffer 9 as read data according to the detection result.

Row decoder 4 selects any one of word lines 50 in memory array 1 in response to an address signal from address buffer 6. The column decoder 5 selects one of the bit lines 30 in the memory array 1 in response to the address signal from the address buffer 6.

Control circuit 140 controls Y gate 2, column decoder 5, write circuit 7, address buffer 6, input / output buffer 9, and sense amplifier 8 so that they operate in accordance with each mode.

A high voltage V _PP from the outside is applied to the terminal T _PP . Supply voltage V _CC of the normal level from the external to the terminal T _CC
Is given. Switch circuit 400 includes high voltage V _PP and power supply voltage V _CC applied to terminals T _PP and T _CC , respectively.
Either one of them is selectively output to a predetermined circuit unit.

Switch circuit 400 is controlled by control circuit 140, and applies a high voltage V _PP from terminal T _PP to row decoder 4 during data writing. Further, switch circuit 400 is controlled by control circuit 140 to apply power supply voltage V _CC to row decoder 4 at the time of data reading. Further, the switch circuit 400 is controlled by the control circuit 140 to apply the high voltage V _PP to the source line switch 3 when erasing data.

At the time of data writing, Y gate 2 applies the voltage applied from write circuit 7 to the bit line selected by column decoder 5. Specifically, if the write data is "0", the Y gate 2 applies the high voltage V _PP to the selected bit line. If the write data is "1", the Y gate 2 holds the potential of the selected bit line at the ground potential. Row decoder 4 when writing data
_Applies V _PP from the high voltage switch circuit 400 to the selected word line. On the other hand, at the time of writing data, the source line switch 3 applies the ground potential to the source line 80. Therefore, if the write data is “0”, the floating gate of the memory transistor (selected memory transistor) located at the intersection of the word line selected by the row decoder 4 and the bit line selected by the column decoder 5. Only 210 is injected with hot electrons. However, if the write data is "1", the control gate 200 is not boosted in the selected memory transistor, so the floating gate 210
No electrons are injected into.

At the time of reading data, the row decoder 4
_Applies the power supply voltage V _CC from the switch circuit 400, which is lower than the high voltage V _PP , to the selected word line. At the time of data writing, Y gate 2 applies a low voltage of 1 to 2 V to the bit line selected by column decoder 5. On the other hand, when reading data, the source line switch 3
Applies the ground potential to the source line 80 as in the data writing. Therefore, if the storage data of the selected memory transistor is “0”, the drain 220 of the memory cell selected from the selected bit line to the source line 80,
Current flows through the channel region and the source 230. If the storage data of the selected memory transistor is "1", the selected memory transistor is 5V.
No current flows through the selected bit line because it is not turned on by a gate voltage of a certain degree. Well, Y gate 2
Applies a power supply voltage to the selected bit line and electrically connects only the selected bit line to the sense amplifier 8. As a result, the sense amplifier 8 can detect the presence / absence of a current flowing through the selected bit line.

At the time of erasing data, Y gate 2 keeps all bit lines 30 in memory array 1 open.
At the time of erasing data, the row decoder 4 applies the ground potential to all the word lines 50 in the memory array 1. At the time of erasing data, the source line switch 3 converts the high voltage V _PP from the switch circuit 400 into a pulse signal and applies it to the source line 80. Therefore, when erasing data,
In each of all the memory cells MC in the memory array 1, a tunnel phenomenon occurs, and the electrons accumulated in the floating gate 210 of the memory transistor whose stored data is “0” are removed from the floating gate 210. Therefore, at the end of data erasing, the storage data of all the memory cells MC in the memory array 1 becomes "1".

In the following description, it is assumed that the power supply potential and the ground potential correspond to logic levels "H" and "L", respectively.

By the way, when the gate voltage is 0 V in the N-channel MOS transistor, a phenomenon called band-to-band tunneling occurs in the overlapping region of the gate and the drain diffusion region. This phenomenon also occurs in the overlapping region of the gate and the source diffusion region when the source potential is high. The band-to-band tunneling occurs when the gate voltage is 0 V and the surfaces of the N-type drain diffusion region and the source diffusion region are in a deep depletion state. When the surface of these N-type diffusion regions is in a deep depletion state, the energy band bends sharply at the boundary between the oxide film under the gate and the substrate. Therefore, electrons in the valence band tunnel to the conduction band in the N-type diffusion region. The holes generated at this time flow to the grounded substrate, while the electrons tunneling to the conduction band gather in the N-type diffusion region. The current generated by the holes flowing into the substrate becomes the leak current of the N-channel MOS transistor. At the time of erasing data, since a high voltage is applied to the source 230 of the memory transistor and the control gate 200 is grounded, such band-to-band tunneling occurs.

Referring again to FIG. 12, the source 23 at the interface between the substrate 240 and the oxide film 250 during data erasing.
It is known that the band-to-band tunneling phenomenon occurs in the zero vicinity portion 260. Since the substrate 240 is grounded, the holes generated by this phenomenon flow as a leak current to the substrate 240 side, and the electrons tunneled to the electric conductor flow to the source 230 side together with the electrons extracted from the floating gate 210. Such a flash EPRO
Regarding the interband tunneling phenomenon in M. J. Chen et
al., "Subbreakd own drain leakage current in MOSFE
T, "IEEE ELectron Device lett., Vol.EDL-8, pp.515-51
7,1987. And H. Kume et al., "A FLASH-ERASE EEPROM
CELL WITH AN ASYMMETRIC SOURCE AND DRAIN STRUCTUR
E "IEEE Tech.Dig. Of IEDM1987, 25.8, pp. 560-563, etc. According to such literature, the leak current generated by the band-to-band tunneling phenomenon is caused by the source 23.
When the potential of 0 is about 10 V, it is about 10 ⁻⁸ A per memory transistor.

[0024]

In the case of a flash memory having a small capacity, the erase pulse is generally applied to all the memory cells at once. During erase, electrons are extracted from the floating gate, and at the same time, a high voltage is applied to the source and the control gate is grounded, so that an interband tunnel current flows. The band-to-band tunnel current is about several nA per memory cell. 16
In the case of a large-capacity flash memory such as M bit, the band-to-band tunnel current is 100 m in the entire memory array.
The current amount is A or more.

Therefore, a method of dividing the memory array into a plurality of blocks and sequentially applying an erase pulse to each block has been considered. This method is described in Japanese Patent Application No. 3-127873, which is a patent application related to the present application (not yet published at the time of filing of the present application). According to this method, the erase current is reduced but the erase time is increased.

An object of the present invention is to provide a non-volatile semiconductor memory device that consumes less current during the erase operation and reduces the erase operation time.

[0027]

A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array, a plurality of high voltage applying means, a detecting means, a group dividing means, an activating means and a controlling means.

The memory cell array includes a plurality of memory cells and is divided into a plurality of blocks. Each of the plurality of memory cells includes a field effect semiconductor element capable of electrically performing both data writing and data erasing.

A plurality of high voltage applying means are provided corresponding to a plurality of blocks, and a high voltage for erasing data is collectively applied to the memory cells included in the corresponding blocks. The detecting means detects a data erased state of a memory cell included in each of the plurality of blocks. The group dividing means divides the plurality of blocks into one or more groups.

The activation means selectively and simultaneously applies the high voltage to one or more blocks in each group in response to the detection result of the detection means, and sequentially applies the high voltage to the one or more groups. The erase cycle for activating the plurality of high voltage applying means is executed.

The control means controls the activation means so that the erase cycle is repeatedly executed until the detection result of the detection means indicates the completion of the data erase in the plurality of blocks, and the groups are assigned to each group in the second and subsequent erase cycles. The group partitioning means is controlled so that the number of blocks included in the group increases more than the number of blocks included in each group in the first erase cycle.

[0032]

In the nonvolatile semiconductor memory device according to the present invention, a high voltage is sequentially applied to one or more groups,
A high voltage is selectively and simultaneously applied to the blocks in each group. The number of blocks belonging to one group is small in the first erase cycle, and the number of blocks belonging to one group is increased in the second and subsequent erase cycles.

The erase current decreases as the erase operation of the memory cells in each block progresses. In the first erase cycle, where a large amount of erase current flows, the number of blocks in one group is reduced and the number of groups is increased. Thereby,
Current consumption is reduced.

In the second and subsequent erase cycles in which the erase current decreases, the number of blocks in one group is increased and the number of groups is decreased. Thereby, the erase time is shortened.

Thus, by efficiently applying the high voltage to the plurality of blocks, the current consumption is small and the erase period is shortened, and the relative erase operation efficiency is improved.

[0036]

EXAMPLE The erase current is determined by the total amount of tunnel current between the floating gate and the source and the band-to-band tunnel current. Further, these current values are affected by the electric field between the floating gate and the source and the electric field between the source and the substrate. The larger the potential difference is, the larger the current value is. However, in the case of erasing, the current value becomes lower as the erasing of the memory cell progresses because the direction is to pull out electrons from the floating gate and raise the potential of the floating gate. An embodiment will be described on the basis of this fact.

(1) Overall Configuration of Flash Memory of Embodiment FIG. 1 is a block diagram showing the overall configuration of a flash memory according to an embodiment of the present invention. FIG. 1 shows a portion of the flash memory mainly involved in the erase operation.

In this flash memory, the memory cell array is divided into four sub arrays 1a, 1b, 1c and 1d.

The sub-array 1a includes a plurality of memory cells MCa arranged in a matrix in a plurality of rows and a plurality of columns.
It includes a plurality of word lines 50a arranged along a plurality of rows and a plurality of bit lines 30a arranged along a plurality of columns.

The sources of the memory transistors forming each memory cell MCa are commonly connected to the source line 80a,
The control gate and drain are connected to the corresponding word line 50a and the corresponding bit line 30a, respectively.

Sub-array 1b similarly includes a plurality of memory cells MCb, a plurality of word lines 50b and a plurality of bit lines 30b. The sub-array 1c similarly includes a plurality of memory cells MCc, a plurality of word lines 50c and a plurality of bit lines 30c. Similarly, sub-array 1d includes a plurality of memory cells MCd, a plurality of word lines 50d and a plurality of bit lines 30d.

Memory cells MCa, MCb, MCc, MC
The structure of each d is similar to the structure shown in FIG. Therefore, also in the flash memory of this embodiment, a high-voltage pulse is applied to the source lines 80a, 80b, 80c, 80d and the word lines 50a, 50b, 50c,
Data can be erased by grounding 50d.

Corresponding to the four sub-arrays 1a-1d,
Four Y gates 2a to 2d, four row decoders 4a to
4d, 4 column decoders 5a to 5d, 4 sense amplifiers 8a to 8d, 4 verify / erase control circuits 1
7a to 17d and four erase voltage applying circuits 18a to 1
8d is provided.

Further, this flash memory includes an address buffer 6, an input / output buffer 9 and an address counter 1.
9, a switch circuit 20, a switch circuit 400, a high voltage pulse source 700 and a control circuit 800.

The address buffer 6 is an external address terminal A
0 to AK. Address buffer 6 takes in an address signal externally applied via external address terminals A0 to AK at the time of normal data writing and data reading, and applies it to switch circuit 20. In this embodiment, the address signal includes a row address signal indicating a row-direction address of the memory cell, a column address signal indicating a column-direction address of the memory cell, and a block address signal for selecting a sub-array.

The address counter 19 is activated in the data erase mode, generates an address signal by the count operation, and supplies it to the switch circuit 20.

Switch circuit 20 applies an address signal applied from address buffer 6 to row decoders 4a-4d and column decoders 5a-5d during normal data writing and data reading. In addition, the switch circuit 2
In the data erase mode, 0 applies the address signal given from the address counter 19 to the row decoders 4a to 4d and the column decoders 5a to 5d, and the lower 2 bits of the address signal are erase voltage applying circuits 18a to 18a.
give to d.

Row decoders 4a to 4d and column decoders 5a to 5d during normal data writing and data reading
5d, Y gates 2a to 2d and sense amplifiers 8a to 8
The operation of d is the same as the conventional one.

The input / output buffer 9 has an external input / output terminal I /
It is connected to O _{0 to} I / O _N. The input / output buffer 9 receives external input / output terminals I / O _{0 to} I / O during normal data writing.
Input data externally applied to _N is taken in, and at the time of normal data reading, the data read from sub arrays 1a to 1d are led to external input / output terminals I / O _{0 to} I / O _N.

In the data erasing mode, the erasing voltage applying circuits 18a to 18d operate in the sub-arrays 1a to 1d, respectively.
Erase cycles for applying erase pulses to the source lines 80a-80d inside the verify / erase control circuits 17a-17
An erase verify cycle in which d is erase verify for sub-arrays 1a to 1d is repeated.

The switch circuit 400 supplies the high voltage V _{PP supplied} from the terminal T _PP to the high voltage pulse source 700 in the erase cycle, and in the erase verify cycle,
Providing power supply voltage V _CC supplied from the terminal T _CC to the row decoder 4 a to 4 d.

In the erase cycle, high-voltage pulse source 700 converts high-voltage V _PP from switch circuit 400 into a high-voltage pulse having a short pulse width, and supplies it as an erase pulse to erase voltage applying circuits 18a-18d. Further, the high-voltage pulse source 700, in the erase verify cycle,
Outputs normal power supply voltage.

In the data erasing mode, the erasing voltage applying circuits 18a to 18d are supplied with the address signal of the lower 2 bits from the switch circuit 20. Erase voltage application circuit 18
Address signals / A0 and / A1 are applied to a, address signals A0 and / A1 are applied to the erase voltage applying circuit 18b, and address signal / A is applied to the erase voltage applying circuit 18c.
0, A1 are applied, and address signals A0, A1 are applied to the erase voltage applying circuit 18d. Address signal / A0
Is an inverted signal of the address signal A0,
A1 is an inverted signal of the address signal A1.

Verify / erase control circuits 17a to 17d
Applies reset signals Ra to Rd and detection signals ERSa to ERSd to the erase voltage applying circuits 18a to 18d, respectively, in the data erase mode.

The control circuit 800 generates a control signal for controlling each part of the flash memory. (2) Operation Specific to Flash Memory of Embodiment The operation of the erase cycle in the flash memory of FIG. 1 will be described with reference to FIGS. 2 and 3.

In the erase cycle, the erase voltage applying circuit 18
Erase pulses are applied to the source lines 80a to 80d in the sub-arrays 1a to 1d by a to 18d, respectively. As a result, the data in the plurality of memory cells in the sub arrays 1a to 1d are erased.

FIG. 2 is a flowchart showing in detail the erase pulse applying step in the erase cycle. Figure 3
It is a figure which shows grouping of sub-arrays 1a-1d.

In this embodiment, the sub-arrays 1a-1d are grouped differently depending on the number of erase cycles (step S30 in FIG. 2).

First erase cycle (step S in FIG. 2)
31), as shown in FIG.
b, 1c, and 1d are groups G1, G2, G3, respectively.
Configure G4. First, the erase voltage applying circuit 18a applies an erase pulse to the source line 80a in the sub-array 1a, and then the erase voltage applying circuit 18b applies an erase pulse to the source line 80b in the sub-array 1b.
Further, the erase voltage applying circuit 18c causes the sub-array 1c.
An erase pulse is applied to the source line 80c in the
The erase voltage applying circuit 18d applies an erase pulse to the source line 80d in the sub-array 1d.

In this way, the groups G1, G2, G3 are
The G4 sub-arrays 1a, 1b, 1c, 1d are sequentially erased collectively.

In this case, since the erase pulse is sequentially applied to the four groups of sub-arrays, the erase time becomes long, but the erase current flowing when each erase pulse is applied becomes small.

Second erase cycle (step S in FIG. 2)
32), as shown in FIG. 3, the sub-arrays 1a and 1b are
Form a group G1, and the sub-arrays 1c and 1d form a group G2. First, the erase voltage application circuit 18a,
Sub-arrays 1a forming a group G1 by 18b,
An erase pulse is simultaneously applied to the source lines 80a and 80b in 1b, and then an erase pulse is simultaneously applied to the source lines 80c and 80d in the sub-arrays 1c and 1d forming the group G2 by the erase voltage applying circuits 18c and 18d. .

As described above, first, the sub-arrays 1a and 1b in the group G1 are simultaneously erased simultaneously, and then the sub-arrays 1c and 1d in the group G2 are simultaneously erased simultaneously.

Erase Cycles from Third Time In FIG. 2 (step S33 in FIG. 2), the sub-arrays 1a, 1b, 1c,
1d constitutes the group G1. Erase voltage application circuit 18
Source line 8 in sub-arrays 1a, 1b, 1c, 1d forming group G1 by a, 18b, 18c, 18d
An erase pulse is simultaneously applied to 0a, 80b, 80c, and 80d.

In this way, the sub-arrays 1a, 1b, 1c and 1d in the group G1 are simultaneously erased.

In this case, since the erasing of the data in the memory cells in each sub array is progressing to some extent, the erasing current flowing in each sub array is small. Therefore, the current consumption is small even if the erase pulse is applied to the four sub-arrays at the same time. Further, since the erase pulse is simultaneously applied to the four sub-arrays 1a to 1d, the erase time is shortened.

In the second and subsequent erase cycles, the erase pulse is not applied to the sub-array in which there are no unerased memory cells.

(3) Detailed Description of Each Part FIG. 4 is a circuit diagram showing a detailed configuration of the address counter 19.

The address counter 19 includes an address generator 191, mask circuits 192 and 193, and an AND gate G.
1, G2, G3 and inverters G4, G5 are included. The mask circuit 192 includes OR gates G6 and G7, and the mask circuit 193 includes OR gates G8 and G9.

The address generator 191 responds to the increment signals applied to the increment terminals INC1, INC2, INC3 by address signals (A0), (A0).
1), A2, ..., An and their inverted signals (/ A
0), (/ A1), / A2, ..., / An are generated.

When the increment signal is applied to the increment terminal INC1, the address generator 191 increments the address signal with the address signal (A0) as the least significant bit. When an increment signal is given to the increment terminal INC2, the address generator 1
91 increments the address signal with the address signal A1 as the least significant bit. Increment terminal IN
When the increment signal is applied to C3, the address generator 191 increments the address signal with the address signal A2 as the least significant bit.

The address counter 19 is supplied with the increment signal INC and the mask signals M1 and M2 by the verify / erase control circuits 17 to 17d (FIG. 1).

FIG. 5 is a diagram showing a truth table of the address counter 19 of FIG. In the first erase cycle, the mask signals M1 and M2 both become "L". Thereby,
The increment signal INC is applied to the increment terminal INC1 of the address generator 191 via the AND gate G1. At this time, the increment terminal INC2,
The increment signal INC is not given to INC3. As a result, the address signals (A0), (A1), A2, ..., An are incremented in response to the increment signal INC.

Further, OR gates G6, G7, G8, G9
Are address signals (A0), (/ A0), (A1),
(/ A1) is the address signal A0, / A0, A
Output as 1, / A1. As a result, the erase voltage application circuits 18a, 18b, 18c, 18d shown in FIG. 1 are sequentially activated.

In the second erase cycle, the mask signal M
1 becomes "H", and the mask signal M2 becomes "L". As a result, the increment signal INC causes the AND gate G
It is given to the increment terminal INC2 of the address generation unit 191 via 2. At this time, the increment signal INC is not applied to the increment terminals INC1 and INC3. As a result, the address signals (A1), A2, ..., An are incremented in response to the increment signal INC.

The outputs of the OR gates G6 and G7 become "H", and the inverters G8 and G9 convert the address signals (A1) and (/ A1) into the address signals A1 and /, respectively.
Output as A1. As a result, first, the erase voltage application circuits 18a and 18b shown in FIG. 1 are simultaneously activated,
Next, the erase voltage application circuits 18c and 18d are simultaneously activated.

In the third and subsequent erase cycles, the mask signals M1 and M2 both become "H". As a result, the increment signal INC is applied to the increment terminal INC3 of the address generator 191 via the AND gate G3. At this time, the increment terminals INC1, INC
The increment signal INC is not given to 2. As a result, the address signals A2, ..., An are incremented in response to the increment signal INC.

Further, OR gates G6, G7, G8, G9
Output becomes "H". As a result, the erase voltage application circuits 18a, 18b, 18c and 18d shown in FIG. 1 are simultaneously activated.

FIG. 6 is a circuit diagram showing a detailed structure of the erase voltage application circuit 18a. Erase voltage application circuit 18b, 1
The configurations of 8c and 18d are similar to the configuration of FIG. 6 except that the applied address signals are different.

The erase voltage applying circuit 18a is composed of the latch circuit 3
00, AND gate 370, and high-voltage switch 500
including.

A detection signal ERSa is applied to the latch circuit 300 from the verify / erase control circuit 17a shown in FIG. When the detection signal ERSa is “0”, the data “1” is latched by the latch circuit 300 and is output to the first input terminal of the AND gate 370. This state indicates that there is an unerased memory cell in the corresponding sub-array 1a.

Further, the latch circuit 300 verifies / verifies
The latched data is reset to "0" in response to the reset signal Ra provided from the erase control circuit 17a.

Address signal / A0 is applied to the second input terminal of AND gate 370, and address signal / A1 is applied to the third input terminal.

The high-voltage switch 500 is a P-channel MOS
Includes transistors 320, 330, 350 and N-channel MOS transistors 310, 340, 360.

Transistors 330 and 340 are connected in series between output node NV of high-voltage pulse source 700 and the ground terminal, and form inverter INV1. Similarly, the transistors 350 and 360 are connected in series between the output node NV of the high voltage pulse source 700 and the ground terminal to form an inverter INV2.

The transistor 310 is the AND gate 37.
It is connected between the output terminal of 0 and the input node of the inverter INV1, and its gate is supplied with the power supply voltage V _CC (5V). The output node of the inverter INV1 is connected to the input node of the inverter INV2. Inverter I
The output node of NV2 is the source line 80 in the sub-array 1a.
connected to a.

The transistor 320 is a high voltage pulse source 70.
It is connected between the output node NV of 0 and the input node of the inverter INV1, and its gate is connected to the output node of the inverter INV1.

The transistor 310 is the transistor 33.
By keeping the gate voltages of 0 and 340 at the power supply voltage of 5 V or less, it is possible to prevent a high voltage from being applied to the transistors 330 and 340 and destroying them.

Next, the erase voltage application circuit 1 shown in FIG.
The operation of 8a will be described. When the detection signal ERSa becomes "0", the output voltage of the latch circuit 300 becomes "H". When the address signals / A0 and / A1 both become "H", AN
The output of the D gate 370 becomes "H". Thereby, the high voltage switch 500 is activated.

The transistor 310 is always conductive. Therefore, the transistor 340 in the inverter INV1 becomes conductive, and the output of the inverter INV1 becomes "L". Therefore, the transistor 350 in the inverter INV2 becomes conductive. As a result, the high voltage pulse applied from the high voltage pulse source 700 to the output node NV is applied to the source line 80a as an erase pulse.

When the reset signal Ra is applied, the data latched by the latch circuit 300 is reset. As a result, the output voltage of the latch circuit 300 becomes "L", and the output of the AND gate 370 also becomes "L". As a result, the high voltage switch 500 is disabled.

In this case, the transistor 330 in the inverter INV1 becomes conductive and the output of the inverter INV1 becomes "H". Therefore, the inverter INV2
The transistor 360 therein becomes conductive. as a result,
A ground potential (“L”) is applied to the source line 80a.

Thus, the erase pulse is applied from the high voltage switch 500 to the source line 80a only when the data "1" is set in the latch circuit 300 and the address signals / A0 and / A1 are both "H". .

7 to 9 are waveform diagrams showing the timing of the erase pulse applied to the sub-arrays 1a, 1b, 1c and 1d in the erase cycle. In the first erase cycle, as shown in FIG. 7, the sub arrays 1a, 1
Erase pulses are sequentially applied to b, 1c and 1d.

In the second erase cycle, as shown in FIG. 8, the erase pulse is first applied to the sub-arrays 1a and 1b at the same time, and then the erase pulse is applied to the sub-arrays 1c and 1d at the same time.

In the third and subsequent erase cycles, as shown in FIG. 9, the erase pulse is simultaneously applied to the sub-arrays 1a, 1b, 1c and 1d.

(4) Data Erase Mode Operation Next, the overall operation of the flash memory of FIG. 1 in the data erase mode will be described with reference to the flowchart of FIG.

First, at the beginning of the data erasing mode, the latch circuits 30 in all the erasing voltage applying circuits 18a to 18d.
Data "1" is set to 0 (step S1).

Then, at the beginning of the erase cycle, the count value of the address counter 19 is reset (step S2). In the erase cycle, as described in detail with reference to FIGS. 2 and 3, the four sub-arrays 1a to 1d are grouped according to the number of erase cycles.
An erase pulse is applied to each group (step S
3).

Next, verify / erase control circuits 17a ...
17d instructs the address counter 19 to increment the count value (step S4). As a result, the address signal generated by the address counter 19 is incremented. In steps S3 and S4, the address signal A2 generated from the address counter 19 is "H".
Is repeated (step S5). As a result, 1
In the second erase cycle, as shown in FIG. 7, erase pulses are sequentially applied to the sub-arrays 1a, 1b, 1c, 1d.

At the end of the erase cycle, the verify / erase control circuits 17a to 17d reset the count value of the address counter 19 (step S6), and the circuit operation for the erase verify cycle is started.

At the beginning of the erase verify cycle, the erase voltage applying circuits 18a to 1d are reset by the reset signals Ra to Rd output from the verify / erase control circuits 17a to 17d.
The latch circuit 300 in 8d is reset (step S7). Thereby, the source lines 80a-80d in the sub-arrays 1a-1d are grounded.

Verify / erase control circuits 17a to 17d
Are row decoders 4a-4d and column decoder 5a.
So that ~ 5d operates in the same way as during normal data reading,
Control these.

As a result, the row decoders 4a-4d are
In response to the address signal applied respectively to select one of the word lines in the sub-array 1 a to 1 d, it applies the power supply voltage V _CC supplied from the switch circuit 400. On the other hand, column decoders 5a-5d respond to address signals respectively applied to sub-arrays 1a-
One of a plurality of bit lines in 1d is selected, a voltage of "H" is applied to it, and the selected bit line is sense amplifier 8a via Y gates 2a to 2d.
Connect to ~ 8d.

In this way, data is simultaneously read from sub-arrays 1a to 1d, the read data is amplified by sense amplifiers 8a to 8d, and supplied to verify / erase control circuits 17a to 17d, respectively (step S8). .

Verify / erase control circuits 17a to 17d
Determines whether or not the data erasing is completed in the currently selected memory cell based on the read data provided from each of the sense amplifiers 8a to 8d (step S9).

If the read data is "0", it can be determined that the data erase is incomplete in the currently selected memory cell. For example, if the read data supplied from the sense amplifier 8a is "0", the verify / erase control circuit 17a outputs the detection signal ERSa of "0".
As a result, the latch circuit 3 in the erase voltage application circuit 18a
Data "1" is set to 00 (step S1
0).

If the read data is "1", it can be determined that data erasing has been completed in the currently selected memory cell. For example, if the read data supplied from sense amplifier 8a is "1", verify / erase control circuit 17a does not output detection signal ERSa.

After that, the verify / erase control circuit 17a
17d instruct the address counter 19 to increment the count value (step S11). As a result, the address signal generated by the address counter 19 is incremented.

The operations of steps S8 to S11 are repeated until the count value of the address counter 19 reaches the maximum value (step S12). As a result, the sub arrays 1a to 1
Erase verify is performed on all the memory cells in d.

In the erase verify cycle, when the verify / erase control circuits 17a to 17d detect that there is a memory cell having a data erase failure in the corresponding sub-arrays 1a to 1d, the erase voltage applying circuit 18 is present at that time.
Data "1" is set in each of the latch circuits 300 in a to 18d. The latch circuit 300 continues to hold this data “1” unless a reset signal is given.

Therefore, if at least one defective memory cell exists in each sub-array, data "1" is latched in the latch circuit 300 in the corresponding erase voltage applying circuit at the end of the erase verify cycle. .

On the other hand, if there is no memory cell having a defective data erase in a certain sub-array, the corresponding verify / erase control circuit does not output the detection signal of "0" even once in the erase verify cycle. Therefore,
At the end of the erase verify cycle, the data “0” is latched in the latch circuit 300 in the corresponding erase voltage applying circuit.

Thus, when the erase verify cycle is completed, the latch circuit 30 in the erase voltage applying circuit corresponding to the sub-array in which the memory cell having the data erase defect exists.
Data "1" is set only in 0.

If the data "1" is set in the latch circuit 300 of any of the erase voltage applying circuits 18a to 18d (step S13), the second erase cycle is executed (steps S2 to S6). In this case, as shown in FIG. 8, the erase pulse is applied to the sub-arrays 1a and 1b at the same time, and then the erase pulse is applied to the sub-arrays 1c and 1d at the same time.

However, when the data "0" is latched in the latch circuit 300 in any one of the erase voltage applying circuits, the erase pulse is not applied to the corresponding sub array.

When the second erase cycle is completed, an erase verify cycle is executed (steps S7 to S1).
2).

At the end of the erase verify cycle, the latch circuit 3 of any one of the erase voltage applying circuits 18a to 18d.
If the data "1" is latched in 00 (step S13), the third erase cycle is executed (steps S2 to S6). In this case, as shown in FIG. 9, the erase pulse is simultaneously applied to the sub-arrays 1a, 1b, 1c and 1d.

However, when the data "0" is latched in the latch circuit 300 in any one of the erase voltage applying circuits, the erase pulse is not applied to the corresponding sub array.

When the third erase cycle ends, an erase verify cycle is executed (steps S7 to S1).
2).

The erase cycle (steps S2 to S
6) and erase verify cycle (steps S7 to S)
12) is repeated until data "1" is not set in any of the latch circuits 300 of the four erase voltage applying circuits 18a to 18d (step S13).

In the above embodiment, the case where a high voltage pulse is applied to the source of a memory cell to erase data has been described. However, the present invention erases data by another method, for example, a memory cell is formed in a P well. The present invention is of course applicable to a flash memory in which a high voltage pulse is applied to the P well to erase data, and a high voltage pulse is applied to the control gate and drain to erase data.

[0123]

As described above, according to the present invention, in the first erase cycle in which a large amount of erase current flows, the number of blocks in each group is reduced and the number of groups is increased to reduce current consumption. To be done. In the second and subsequent erase cycles in which the erase current decreases, the erase time is shortened by increasing the number of blocks in each group and decreasing the number of groups.

Therefore, the current consumption is small and the erase time is shortened, and the erase operation can be efficiently performed as a whole.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a flash memory according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of an erase cycle of the flash memory of FIG.

FIG. 3 is a diagram for explaining grouping in an erase cycle of the flash memory of FIG.

4 is a circuit diagram showing a detailed configuration of an address counter included in the flash memory of FIG.

5 is a diagram showing a truth table of the address counter shown in FIG. 4;

6 is a circuit diagram showing a detailed configuration of an erase voltage application circuit included in the flash memory of FIG.

7 is a waveform diagram for explaining the operation of the erase voltage application circuit of FIG.

FIG. 8 is a waveform diagram for explaining the operation of the erase voltage application circuit of FIG.

9 is a waveform diagram for explaining the operation of the erase voltage application circuit of FIG.

10 is a flow chart for explaining the overall operation of the flash memory of FIG. 1 in a data erase mode.

FIG. 11 is a partial schematic block diagram of a conventional flash memory.

FIG. 12 is a cross-sectional view showing a structure of a memory cell of a flash memory.

[Explanation of symbols]

 1a to 1d Sub-array 2a to 2d Y gate 4a to 4d Row decoder 5a to 5d Column decoder 6 Address buffer 8a to 8d Sense amplifier 9 Input / output buffer 17a to 17d Verify / erase control circuit 18a to 18d Erase voltage application circuit 19 Address counter 20 Switch circuit 191 Address generator 192, 193 Mask circuit G1 to G3 AND gate G4, G5 Inverter G6 to G9 OR gate 400 Switch circuit 300 Latch circuit 370 AND gate 500 High voltage switch 700 High voltage pulse source 800 Control circuit The same in each figure The reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tomoji Futani 4-1-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Laboratory (72) Inventor Shinichi Kobayashi 4 Mizuhara, Itami City, Hyogo Prefecture 1-chome Mitsubishi Electric Corporation LSI Research Center

Claims (1)

[Claims] 1. A memory cell array including a plurality of memory cells, wherein the memory cell array is divided into a plurality of blocks, and each of the plurality of memory cells can electrically perform both data writing and data erasing. A plurality of high voltage applying means including a possible field effect semiconductor element, which are provided corresponding to the plurality of blocks and collectively apply a high voltage for data erasing to the memory cells included in the corresponding blocks. A detection unit for detecting a data erased state of a memory cell included in each of the plurality of blocks; a group division unit for dividing the plurality of blocks into one or more groups; and a detection result of the detection unit. A high voltage is selectively and simultaneously applied to one or more blocks in each group, and a high voltage is sequentially applied to the one or more groups. And an activating means for executing an erasing cycle for activating the plurality of high voltage applying means, and the erasing cycle is repeatedly executed until a detection result of the detecting means indicates completion of data erasing in the plurality of blocks. And the group dividing means so that the number of blocks included in each group in the second and subsequent erase cycles is greater than the number of blocks included in each group in the first erase cycle. The nonvolatile semiconductor memory device further comprising: a control unit that controls the.