JPH0583534A - Image enlarging device - Google Patents

Abstract

(57) [Abstract] [Purpose] When the N times expansion is performed, the write clock to the FIFO memory operates at N times or less the sampling frequency of the original image signal, and the expansion is performed with the relatively low speed FIFO memory and the clock generation circuit. An image enlarging device capable of operating is provided. [Structure] An original image signal is written in a first FIFO memory 1, and an intermediate image signal is taken out from the first FIFO memory 1 at a frequency lower than the frequency of the original image signal. This is written in the second FIFO memory 2 at a frequency lower than the frequency N times the frequency of the original image signal to the second FIFO memory 2, and is read from the second FIFO memory 2 at the frequency of the original image signal. Therefore, an element having a relatively low operating frequency can be used for the second FIFO memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic printing device such as a CRT display device, a printer, a copying machine or the like, which handles digital image signals, or other graphic display devices. It relates to the device.

[0002]

2. Description of the Related Art Conventionally, a raster type image signal is a typical one of the signal types handled in a digital image processing apparatus. The image signal in the raster format means that the image is divided into horizontal and vertical pixels, the pixel signals for one horizontal line are sent together, and then the signal for the next line is sent. It is a form that is sent in a simple form. On the side of the display device that receives this, images for each line that are sent one after another are displayed in order.

Enlarging when using a raster format image signal is one way to increase the pixel size at the time of display compared to the pixel size of the original image, but in this case the result is a rough picture. Become. To enlarge the image while keeping the pixel size of the original image equal to the pixel size at the time of display,
It must be considered to generate n or more pixels from n pixels of the original image. In other words, the pixel data is interpolated by some method to increase the number of pixels.

Conventionally, for interpolation expansion of an image by N times, the original image data is resampled with a clock N times the sampling frequency of the original image, and then the speed is converted to a desired sampling frequency. It has been known. Briefly, this is a method of outputting one pixel of the original image repeatedly N times, and will be described in detail with an example below.

FIG. 3 is a block diagram of a conventional example using this method.

The original image signal 15 is written in the FIFO memory 14 by the variable frequency write clock 18, and thereafter,
The configuration is such that the output clock 19 is used for reading. Here, the FIFO memory is an abbreviation for first-in first-out memory and is a first-in first-out storage device. If you read this after writing some data, you can read from the one you wrote earlier. Now, in order to enlarge the image data by 4 times in this configuration, if the sampling frequency of the original image is 10 MHz, the write clock 18 to the FIFO memory 14 is set to 40 MHz which is 4 times 10 MHz and the image data is stored in the FIFO memory 14. Write.

The data may be binary or multivalued. FIG. 4 shows a timing chart at this time. Focusing on one pixel of the original image,
Since the sampling cycle of the original image signal is 10 MHz, one pixel holds the same value for 100 ns. During this period, the write clock 18 has 40 MHz and thus has four rising edges. Since the data is written in the FIFO memory 14 at this rising edge timing, as a result, four data from one original pixel are generated and accumulated in the FIFO memory 14. If this is read from the FIFO memory 14 with the output clock 19 of 10 MHz, one to four original pixels can be generated. In FIG. 4, the original image 1
It is shown that four pixel data of the same d1 are generated in the output signal 16 from one pixel data d1 of 5.

The above is the operating principle of the method of re-sampling the original image data with the clock of N times.

In reality, since the length (memory capacity) of the FIFO memory is not infinite but has a limit, it is necessary to prevent the increased data from overflowing. In many cases, the raster format image signal has a pause period, which is used. The quiescent period is a period of time after the image signals for one line are sent together and before the signal for the next line arrives, and is usually provided at the request of the display device side. For example, in a television device, this corresponds to the horizontal blanking period, and in a laser printer, this corresponds to the invalid scanning period of the polygon scanner. FIG. 5 is a timing chart of the original image signal and the enlarged output signal in consideration of the pause period. The figure shows a two-fold enlargement of the original image. Due to the pause period, there is a grace period for reading the surplus data generated in the FIFO memory.

In the example taken up earlier, the increased number of pixels is simply the output of the pixels of the original image repeatedly. However, in this state, the increased number of steps is called a jaggy which is generated in a diagonal line of the enlarged image. The pattern is emphasized, which is not preferable in terms of visual sense. For this reason, it has been frequently performed conventionally to perform smoother interpolation by taking a weighted average of two adjacent pixels with a certain weight.

[0011]

However, in the above-described method using the N-fold clock, the clock generation circuit capable of generating the high-frequency write clock in proportion to the increase in the image signal speed and the increase in the enlargement ratio. And a high-speed operable FIFO memory capable of coping with the high-frequency write clock. A high-speed clock generation circuit and a FIFO memory are expensive, and a high-level mounting technology is required to operate the high-speed circuit.

The present invention has been made to solve the above-mentioned problems, and the clock for writing into the FIFO memory at the time of N times expansion is operated at N times or less the sampling frequency of the original image signal. , Relatively slow FIF
An image enlarging device capable of enlarging operation with an O memory and a clock generating circuit is provided.

[0013]

In order to achieve this object, an image enlarging apparatus of the present invention provides a first FIFO type storage means for inputting an original image signal and outputting an intermediate image signal, and an intermediate image signal for storing the intermediate image signal. Second FI for inputting and outputting a magnified image signal
FO type storage means, a read clock generation circuit for generating a read clock to be supplied to the first FIFO type storage means, and an expansion clock generation circuit for generating a write clock to be supplied to the second FIFO type storage means. is doing.

[0014]

In the image enlarging apparatus of the present invention having the above-mentioned structure, the original image signal input from the outside is temporarily stored in the first FIFO type storage means in synchronization with the original image signal synchronizing clock which is also input from the outside. It is written and then taken out as an intermediate image signal. The frequency of the read clock of the first FIFO type storage means is set lower than the frequency of the original image signal synchronizing clock, and the obtained intermediate image signal has one pixel longer than the original image signal. That is, data with the same number of pixels is output over a longer time than the original image signal. This time axis expansion is the time required to output the data of the number of input pixels at the speed of the intermediate image signal.
It is possible to extend to a point where the line interval of the image signal is not exceeded.

The intermediate image signal thus obtained is enlarged by the second FIFO type storage means in the same manner as in the prior art. That is, in the case of N-fold enlargement, the second FIFO is clocked with a clock N times the sampling frequency of the intermediate image signal.
It is written in the type storage means. Since the sampling frequency of the intermediate image signal is lower than the sampling frequency of the original image signal, the writing frequency of the second FIFO type storage means is lower than N times the sampling frequency of the original image signal. Thereafter, when the data is read from the second FIFO type storage means at the sampling frequency of the original image signal, a signal expanded N times is obtained.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an electrical block diagram of an image enlarging apparatus showing an embodiment of the present invention.

A first FIFO memory 1 for inputting an original image signal 3 input from the outside in synchronization with a synchronization clock 6 input from the outside and outputting an intermediate image signal 4, and an intermediate image signal 4 are input. Second FI for outputting enlarged image signal 5
It comprises a FO memory 2, a read clock generation circuit 10 for generating a read clock 7 to be supplied to the first FIFO memory 1, and a write clock generation circuit 11 for generating a write clock 8 to be supplied to the second FIFO memory 2. It is a composition.

The original image signal 3 supplied from the outside is written in the first FIFO memory 1 by the synchronous clock 6 supplied together with the original image signal 3. The intermediate image signal 4 is read from the first FIFO memory 1 by the read clock 7 generated by the read clock generation circuit 10. The intermediate image signal 4 is guided to the second FIFO memory 2 and is written in the second FIFO memory 2 by the write clock 8 generated by the write clock generation circuit 11. Second
Is read from the FIFO memory 2 by the output clock 9. Normally, the same clock as the synchronous clock 6 of the original image signal is used, but it is also possible to use clocks of different frequencies. Second FIFO memory 2
The data read from is output from the apparatus as an enlarged image signal 5.

The read clock 7 is set lower than the sampling frequency of the original image signal 3. When the image is enlarged N times, the write clock 8 generated by the write clock generation circuit 11 is controlled so that its frequency is N times that of the read clock 7.

FIG. 2 is a timing chart showing the time relationship between each signal and the clock. The horizontal synchronizing signal 13 is supplied from the outside together with the original image signal 3 so that the start of one line can be known. When the data of the first line is written in the first FIFO memory 1,
Reading from the first FIFO memory 1 has not yet taken place. At the same time that the data of the second line is written in the first FIFO memory 1, reading from the first FIFO memory 1 starts. That is, one line of data is the first FIF
When the data is accumulated in the O memory 1, the reading of the previous line is performed simultaneously with the writing of the next line. Similarly, in the second FIFO memory, one line of data is stored in the second FI.
After accumulating in the FO memory 2, the writing of the next line and the reading of the previous line are performed at the same time.

Here, the read clock 7 is set lower than the sampling frequency of the original image signal 3,
Think about how low you can go. Assuming that the cycle of one line (the cycle of the horizontal synchronizing signal 13) is T, the sampling frequency of the original image signal 4 is fo, the frequency of the read clock 7 is fr, and the number of pixels in one line is p, the original image signal 3
The rest period S of is expressed as S = T−p / fo. On the other hand, fr can be made small as long as p / fr <T is satisfied, that is, when p / fr <p / fo + S is transformed, fr satisfies fr> (p · fo) / (p + S · fo). It can be made small within the limit. According to this, 1
The smaller the number of pixels p in the line or the longer the rest period S of the original image signal 3, the slower fr can be.

In this way, the intermediate image signal 4 whose frequency has once been lowered is written in the second FIFO memory 2. When it is desired to expand N times, the frequency fr of the read clock 7
Is written to the second FIFO memory 2 at a clock of N times. Since the frequency of the intermediate image signal 4 is lower than the frequency of the original image signal 3, the writing frequency of the second FIFO memory 2 is lower than N times the frequency of the original image signal 3. That is, compared with the conventional example, the second FIFO memory 2
Can realize a circuit with a low operating frequency.

To give specific numerical values, one line period T = 574 μs, original image signal sampling frequency fo
= 10 MHz, and the number of pixels in one line p = 4677, the idle period S becomes 106.3 μs, but at this time, fr can be lowered to 8.148 MHz.
For example, if 4 times magnification is performed, in the conventional example, 40M
While a Hz clock is required, the present embodiment can operate with a write clock of 32.592 MHz.

After that, when the data is read from the second FIFO memory 2 at the frequency of the original image signal 3, a signal enlarged N times is obtained.

As described above, N times expansion can be performed by using only a clock that is lower than N times the frequency of the original image signal.

In addition, for practical use, each FI is set so that the number of pixels after expansion does not exceed the period of the horizontal synchronizing signal.
It is necessary to limit the number of write pixels and the number of read pixels to the FO memory. One method is to limit the number of pixels of the original image signal in advance, but in the present embodiment, the write / read section signal generation circuit 12 is provided. By connecting the section signal generated from this to the write enable and read enable of the first and second FIFO memories, only the necessary part of the image signal can be cut out and passed to the next circuit. When the number of pixels after enlargement exceeds the maximum number of horizontal pixels, a part of the input pixels is cut out and enlarged.

The present invention is not limited to the embodiments described in detail above, and modifications can be made without departing from the spirit of the invention.

For example, in this embodiment, the increased number of pixels is
Although the pixels of the original image are simply and repeatedly output, it is also possible to perform a smoother interpolation by taking a weighted average of two adjacent original image pixels with appropriate weights.

[0030]

As described in detail above, the image enlarging apparatus of the present invention, when enlarging an image N times, enlarges the image using a clock lower than N times the sampling frequency of the original image signal. You can Therefore, an element having a low operating frequency can be used for the FIFO memory, and the device can be provided at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of an example of the present invention.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a timing chart of a conventional example.

FIG. 5 is a timing chart of a conventional example.

[Explanation of symbols]

 1 1st FIFO memory 2 2nd FIFO memory 10 read clock generation circuit 11 write clock generation circuit

Claims (1)

[Claims] 1. In an image enlarging device for handling a raster-type digital image signal having a pause period, an original image signal input from the outside is input in synchronization with an original image signal synchronization clock input from the outside, and an intermediate First FIFO type storage means for outputting an image signal, second FIFO type storage means for inputting the intermediate image signal and outputting an enlarged image signal, and a read clock supplied to the first FIFO type storage means And a write clock generating circuit for generating a write clock to be supplied to the second FIFO type storage means, and a read clock generating circuit for generating the intermediate image signal from the first FIFO type storage means. The reading frequency is lower than the frequency of the original image signal synchronizing clock, and the second FIFO memory for expanding the image N times. It said intermediate image signal writing frequency to the image expansion device being characterized in that set lower than N times the frequency of the original image signal synchronization clock.