JPH0555418A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0555418A JPH0555418A JP3212185A JP21218591A JPH0555418A JP H0555418 A JPH0555418 A JP H0555418A JP 3212185 A JP3212185 A JP 3212185A JP 21218591 A JP21218591 A JP 21218591A JP H0555418 A JPH0555418 A JP H0555418A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- bumps
- integrated circuit
- circuit device
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】 (修正有)
【目的】フリップチップ接続方式の半導体集積回路装置
における半導体チップの放熱効率を向上させる。
【構成】この半導体集積回路装置は、半導体チップ1を
配線基板7に搭載してなる半導体集積回路装置であっ
て、半導体チップ1の能動領域4の面に半導体チップ1
の回路から独立した放熱用バンプ2bを設け、配線基板
7上に放熱用バンプ2bに対応させて放熱用パッド12
bを形成すると共に、放熱用バンプ2bを放熱用パッド
12bに当接させてなる。
(57) [Summary] (Modified) [Purpose] To improve the heat dissipation efficiency of a semiconductor chip in a flip-chip connection type semiconductor integrated circuit device. This semiconductor integrated circuit device is a semiconductor integrated circuit device in which a semiconductor chip 1 is mounted on a wiring board 7, and the semiconductor chip 1 is formed on the surface of an active region 4 of the semiconductor chip 1.
The heat radiation bumps 2b independent of the circuit of FIG. 2 are provided, and the heat radiation pads 12 are provided on the wiring board 7 in correspondence with the heat radiation bumps 2b.
While forming b, the heat dissipation bumps 2b are brought into contact with the heat dissipation pads 12b.
Description
【0001】[0001]
【産業上の利用分野】本発明は、フリップチップ接続方
式の半導体集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip connection type semiconductor integrated circuit device.
【0002】[0002]
【従来の技術】従来から半導体チップを配線基板に搭載
してなる半導体集積回路装置には、種々の接続方式が採
用されている。一般には、ワイヤボンデイングあるいは
TAB(Tape Automated Bonding)などの接続方式が用
いられている。2. Description of the Related Art Conventionally, various connection methods have been adopted for a semiconductor integrated circuit device in which a semiconductor chip is mounted on a wiring board. Generally, a connection method such as wire bonding or TAB (Tape Automated Bonding) is used.
【0003】ところで、これらの接続方式は、配線基板
上の半導体チップ配置部周辺に接続用のパッドを形成
し、このパッドと半導体チップ上に設けたパッドとをリ
ードで接続する形態をとっており、基板スペースを利用
する上では限界がある。By the way, these connection methods take a form in which a pad for connection is formed around the semiconductor chip arrangement portion on the wiring board and the pad and the pad provided on the semiconductor chip are connected by a lead. However, there is a limit in using the board space.
【0004】そこで、近年、半導体チップにバンプを設
け、配線基板に半導体チップを裏返した状態で搭載する
フリップチップ接続方式が注目されている。この接続方
式では、半導体チップ配置部の内側の基板スペースにパ
ッドを設けることができるので半導体チップを高密度に
搭載できる。また、この接続方式は、半導体チップに設
けるバンプを直径が 100μm 以下と小さく形成できるの
で、配線基板のパッド間隔を狭ピッチ化して半導体チッ
プの入出力端子数を増加させることも可能である。Therefore, in recent years, attention has been paid to a flip chip connection method in which bumps are provided on a semiconductor chip and the semiconductor chip is mounted on a wiring board in an inverted state. In this connection method, since the pads can be provided in the substrate space inside the semiconductor chip placement portion, the semiconductor chips can be mounted at high density. Also, with this connection method, since the bumps provided on the semiconductor chip can be formed with a small diameter of 100 μm or less, it is possible to increase the number of input / output terminals of the semiconductor chip by narrowing the pitch between the pads on the wiring board.
【0005】ここで、従来のフリップチップ接続方式の
半導体集積回路装置について図6(a)、図6(b)を
参照して説明する。A conventional flip-chip connection type semiconductor integrated circuit device will now be described with reference to FIGS. 6 (a) and 6 (b).
【0006】図6(a)は半導体チップのバンプを示す
平面図である。FIG. 6A is a plan view showing bumps of a semiconductor chip.
【0007】同図において、61は半導体チップであ
る。この半導体チップ61の一面には、半導体チップ6
1の縁部周辺に多くの入出力端子がバンプ62として形
成されている。このバンプ62は半導体チップ61の内
部の図示しない回路に接続されている。In the figure, reference numeral 61 is a semiconductor chip. The semiconductor chip 6 is formed on one surface of the semiconductor chip 61.
A large number of input / output terminals are formed as bumps 62 around the edge portion of 1. The bump 62 is connected to a circuit (not shown) inside the semiconductor chip 61.
【0008】図6(b)は上記半導体チップ61を配線
基板63上に搭載した状態を示す断面図である。同図に
示すように、配線基板63は、高熱伝導性の配線基板6
4とこの配線基板64上に形成した薄膜配線層65と、
この薄膜配線層65上に設けたパッド66とからなる。
薄膜配線層65の内層には、配線導体67が形成されて
おり、この配線導体67の一端が薄膜配線層65上部に
引き出されパッド66と接続されている。そして、この
配線基板63のパッド66に半導体チップ61のバンプ
62が当接されて半導体集積回路装置が構成されてい
る。FIG. 6B is a sectional view showing a state in which the semiconductor chip 61 is mounted on the wiring board 63. As shown in the figure, the wiring board 63 is a wiring board 6 having high thermal conductivity.
4 and a thin film wiring layer 65 formed on the wiring board 64,
The pad 66 is provided on the thin film wiring layer 65.
A wiring conductor 67 is formed in the inner layer of the thin film wiring layer 65, and one end of this wiring conductor 67 is drawn to the upper portion of the thin film wiring layer 65 and connected to the pad 66. Then, the bumps 62 of the semiconductor chip 61 are brought into contact with the pads 66 of the wiring board 63 to form a semiconductor integrated circuit device.
【0009】この半導体集積回路装置では、半導体チッ
プ61の熱は、半導体チップ61に形成されているバン
プ62を介して配線基板63に伝達される。例えば、半
導体チップ61で発生した熱は、半導体チップ61の周
辺部に形成した回路接続用バンプ62を経由して配線基
板63へ伝達される。In this semiconductor integrated circuit device, the heat of the semiconductor chip 61 is transferred to the wiring board 63 via the bumps 62 formed on the semiconductor chip 61. For example, the heat generated in the semiconductor chip 61 is transferred to the wiring board 63 via the circuit connecting bumps 62 formed in the peripheral portion of the semiconductor chip 61.
【0010】しかしながら、半導体チップ61に発生し
た熱をこのように放熱するのでは、放熱経路が限定され
ているため、熱抵抗が高く放熱効率が悪い。また、配線
基板63の薄膜配線層65には、電気的特性を優先して
熱伝導性の劣る有機材料、例えばポリイミドが用いられ
ることも少なくない。この薄膜配線層65のもつ熱抵抗
も放熱を阻害する要因になる。However, if the heat generated in the semiconductor chip 61 is dissipated in this way, the heat dissipation path is limited, so the heat resistance is high and the heat dissipation efficiency is poor. In addition, for the thin film wiring layer 65 of the wiring board 63, an organic material having poor thermal conductivity, such as polyimide, which gives priority to electrical characteristics, is often used. The thermal resistance of the thin film wiring layer 65 also becomes a factor that hinders heat dissipation.
【0011】[0011]
【発明が解決しようとする課題】このように上述した従
来のフリップチップ接続方式の半導体集積回路装置では
半導体チップの中央部で発生した熱は、半導体チップ縁
部周辺のバンプを経由して配線基板に伝えられるため熱
抵抗が高く放熱効率が悪い。As described above, in the conventional flip-chip connection type semiconductor integrated circuit device described above, the heat generated at the central portion of the semiconductor chip is passed through the bumps around the edge of the semiconductor chip to the wiring substrate. Therefore, the heat resistance is high and the heat dissipation efficiency is poor.
【0012】本発明はこのような課題を解決するために
なされたもので、フリップチップ接続方式により搭載し
た半導体チップが発生する熱を、配線基板に効率よく放
熱することのできる半導体集積回路装置を提供すること
を目的としている。The present invention has been made to solve the above problems, and provides a semiconductor integrated circuit device capable of efficiently radiating the heat generated by a semiconductor chip mounted by a flip chip connection method to a wiring board. It is intended to be provided.
【0013】[0013]
【課題を解決するための手段】この発明の半導体集積回
路装置は上記した目的を達成するために、バンプを有す
る半導体チップを、このバンプに対応させてパッドを形
成した配線基板に搭載してなる半導体集積回路装置にお
いて、前記半導体チップ中央部の能動領域面に電気信号
回路とは独立した放熱用バンプを設け、前記配線基板上
に該放熱用バンプに対応させてパッドを形成し互いに当
接させてなる。In order to achieve the above-mentioned object, the semiconductor integrated circuit device of the present invention has a semiconductor chip having bumps mounted on a wiring board having pads formed corresponding to the bumps. In a semiconductor integrated circuit device, a heat-releasing bump independent of an electric signal circuit is provided on the active region surface of the central part of the semiconductor chip, and pads are formed on the wiring board so as to correspond to the heat-releasing bumps and are brought into contact with each other. It becomes.
【0014】配線基板は高熱伝導性を有する材料を用い
て形成し、この配線基板上に配線層を形成する。この
際、バンプに対応させて配線層中にフィルドビアを形成
するか、あるいは絶縁層に無機材料を用いる。The wiring board is formed by using a material having high thermal conductivity, and a wiring layer is formed on this wiring board. At this time, a filled via is formed in the wiring layer corresponding to the bump, or an inorganic material is used for the insulating layer.
【0015】[0015]
【作用】本発明では、半導体チップの能動領域面に半導
体チップの回路から独立した放熱用バンプを設け、配線
基板上に放熱用バンプに対応させてパッドを形成して放
熱用バンプとを当接させている。According to the present invention, the heat radiation bumps independent of the semiconductor chip circuit are provided on the active area surface of the semiconductor chip, and pads are formed on the wiring board so as to correspond to the heat radiation bumps and contact the heat radiation bumps. I am letting you.
【0016】したがって、半導体チップで発生した熱は
配線基板へ最短距離で伝達されると共に、配線基板中の
熱の伝達は、熱伝導性の基板材料を用いることによって
改善される。さらに、配線層部分での熱抵抗も低減され
る。Therefore, the heat generated in the semiconductor chip is transferred to the wiring board in the shortest distance, and the transfer of heat in the wiring board is improved by using the heat conductive substrate material. Further, the thermal resistance in the wiring layer portion is also reduced.
【0017】この結果、半導体チップの放熱効率を向上
させることができる。As a result, the heat dissipation efficiency of the semiconductor chip can be improved.
【0018】[0018]
【実施例】以下、図面を参照して本発明の実施例につい
て詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【0019】図1は本発明の半導体集積回路装置に用い
られている半導体チップを示す平面図である。FIG. 1 is a plan view showing a semiconductor chip used in the semiconductor integrated circuit device of the present invention.
【0020】同図において、1は半導体チップである。
この半導体チップ1の一面には、その周辺部に沿って電
気的入出力端子用のバンプ2aが配置されている。ま
た、半導体チップ1の中央部の能動領域上に2次元アレ
イ状に放熱用バンプ2bが配置されている。これらのバ
ンプ2a、2bは、Pb/Sn系のはんだメッキにより
形成されている。In the figure, 1 is a semiconductor chip.
On one surface of the semiconductor chip 1, bumps 2a for electrical input / output terminals are arranged along the peripheral portion thereof. Further, the heat dissipation bumps 2b are arranged in a two-dimensional array on the active region at the center of the semiconductor chip 1. These bumps 2a and 2b are formed by Pb / Sn-based solder plating.
【0021】続いて、半導体チップ1の構成を図2を参
照して詳細に説明する。Next, the structure of the semiconductor chip 1 will be described in detail with reference to FIG.
【0022】図2は図1のA−A線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.
【0023】同図に示すように、半導体チップ1の表面
には、パッシベーション膜3が形成されている。このパ
ッシベーション膜3の内部には、半導体チップ1の能動
領域4上に、電源系あるいは信号系の回路が接続された
配線層5が形成されている。また、このパッシベーショ
ン膜3上には、配線層5に接続された電気的入出力端子
用のバンプ2aが形成されている。さらに、このパッシ
ベーション膜3上には、Cu導体からなるパッド6を介
して放熱用バンプ2bがバンプ2aとは独立して形成さ
れている。As shown in the figure, a passivation film 3 is formed on the surface of the semiconductor chip 1. Inside the passivation film 3, on the active region 4 of the semiconductor chip 1, a wiring layer 5 to which a power supply system or a signal system circuit is connected is formed. Further, on the passivation film 3, bumps 2a for electrical input / output terminals connected to the wiring layer 5 are formed. Further, on the passivation film 3, a heat radiation bump 2b is formed independently of the bump 2a via a pad 6 made of a Cu conductor.
【0024】次に、本発明の半導体集積回路装置の一実
施例を図3を参照して説明する。Next, an embodiment of the semiconductor integrated circuit device of the present invention will be described with reference to FIG.
【0025】図3は上記半導体チップ1をフリップチッ
プ接続方式により配線基板に搭載した状態を示す断面図
である。FIG. 3 is a sectional view showing a state in which the semiconductor chip 1 is mounted on a wiring board by a flip chip connection method.
【0026】同図において、7は配線基板である。この
配線基板7には、熱伝導性のよい材料としてシリコン
(熱伝導度:K、K=150W/m℃)、AlN(K=170W/m
℃)あるいはSiC(K=270W/m℃)などが用いられて
いる。この配線基板7の上面には、薄膜配線層8が形成
されている。この薄膜配線層8は、良好な電気的特性
(低誘電率)の得られるポリイミドなどの材料を用いて
形成された絶縁層10と、この絶縁層10内に形成され
た配線導体11とからなる。この配線導体11は銅やア
ルミニウムを主体として金属蒸着法あるいはスパッタ法
により着膜され、フォトリソグラフィーにより微細な配
線として形成されてる。なお、薄膜配線層8の絶縁層に
用いたポリイミドの熱伝導度:Kは、0.2W/m℃であり、
シリコン(K=150W/m℃)やSiO2 (K=1.4W/m℃)
と比較すると、シリコンとでは2桁、またSiO2 とで
は1桁程度、熱伝導度が悪い。In the figure, 7 is a wiring board. The wiring board 7 includes silicon (thermal conductivity: K, K = 150 W / m ° C.), AlN (K = 170 W / m) as a material having good thermal conductivity.
C.) or SiC (K = 270 W / m.degree. C.) or the like is used. A thin film wiring layer 8 is formed on the upper surface of the wiring board 7. The thin film wiring layer 8 is composed of an insulating layer 10 formed of a material such as polyimide that has good electrical characteristics (low dielectric constant), and a wiring conductor 11 formed in the insulating layer 10. .. The wiring conductor 11 is mainly composed of copper or aluminum and is deposited by a metal vapor deposition method or a sputtering method, and is formed as a fine wiring by photolithography. The thermal conductivity K of the polyimide used for the insulating layer of the thin film wiring layer 8 is 0.2 W / m ° C.,
Silicon (K = 150W / m ° C) and SiO 2 (K = 1.4W / m ° C)
In comparison with, the thermal conductivity is poor, that is, two digits for silicon and one digit for SiO 2 .
【0027】また、この薄膜配線層8の表面には、半導
体チップ1の各バンプ2a、2bに対応するパッド12
a、12bが形成されている。このうち、パッド12a
は回路接続用パッドであり配線導体11と接続されてい
る。パッド12bは放熱用のパッドである。さらに薄膜
配線層8の内層には、パッド12bより配線基板7に垂
直に接続するビア13が形成されている。このビア13
は、Cuメッキなどでビア開口部を埋めるようにした
“フィルドビア”を縦積みしたものが放熱上、最も好ま
しい。このように形成された配線基板7にフリップチッ
プ接続により半導体チップ1を搭載して半導体集積回路
装置が構成されている。なお、このフリップチップ接続
では、配線基板7のパッド12a、12bには、それぞ
れ対応する半導体チップ1のバンプ2a、2bが当接さ
れている。Further, on the surface of the thin film wiring layer 8, pads 12 corresponding to the bumps 2a and 2b of the semiconductor chip 1 are formed.
a and 12b are formed. Of these, the pad 12a
Is a circuit connection pad and is connected to the wiring conductor 11. The pad 12b is a heat dissipation pad. Further, a via 13 is formed in the inner layer of the thin film wiring layer 8 to connect the pad 12b to the wiring board 7 vertically. This via 13
In terms of heat dissipation, it is most preferable to vertically stack "filled vias" that fill the via openings with Cu plating or the like. A semiconductor integrated circuit device is configured by mounting the semiconductor chip 1 on the wiring board 7 thus formed by flip-chip connection. In this flip-chip connection, the bumps 2a and 2b of the corresponding semiconductor chip 1 are in contact with the pads 12a and 12b of the wiring board 7, respectively.
【0028】次に、この半導体集積回路装置の動作につ
いて説明する。Next, the operation of this semiconductor integrated circuit device will be described.
【0029】この半導体集積回路装置の配線基板7の回
路よりバンプ2aを介して半導体チップ1に電源・接地
電位などが供給されて信号の入出力が行われる。From the circuit of the wiring board 7 of this semiconductor integrated circuit device, power supply / ground potential is supplied to the semiconductor chip 1 via the bumps 2a to input / output signals.
【0030】この半導体チップ1の動作に伴い半導体チ
ップ1には熱が発生する。例えば、この半導体チップ1
の中央部で発生した熱は、バンプ2bより垂直に接続さ
れたビア13を通じて最短距離で配線基板7の放熱層9
に伝えられ放熱される。With the operation of the semiconductor chip 1, heat is generated in the semiconductor chip 1. For example, this semiconductor chip 1
The heat generated in the central part of the heat dissipation layer 9 of the wiring board 7 is shortest distance through the via 13 vertically connected to the bump 2b.
And is dissipated in heat.
【0031】ここで、図4を参照して本実施例のバンプ
面積に対する熱抵抗の変化について説明する。Here, the change in thermal resistance with respect to the bump area of this embodiment will be described with reference to FIG.
【0032】同図は、銅/ポリイミドで構成される薄膜
配線層8において、半導体チップ1の面積に対するバン
プ2bの占有面積比率を横軸にとり、半導体チップ1と
バンプ2bとの接合部より基板底面までの熱抵抗の変化
を縦軸にとったものである。本実施例では、10mm角の半
導体チップ1の面に、直径 100μm のバンプ2bを250
μm 間隔で25個×25個のアレイ状に形成している。この
場合、バンプ2bの占有面積は、約 5mm2 となり、10mm
角の半導体チップ1(面積: 100mm2 )に対するバンプ
2bの占有面積比率として 5% を得ることができる。In the figure, in the thin-film wiring layer 8 made of copper / polyimide, the abscissa represents the occupied area ratio of the bumps 2b to the area of the semiconductor chip 1, and the substrate bottom surface from the joint between the semiconductor chip 1 and the bump 2b. The vertical axis is the change in thermal resistance up to. In this embodiment, 250 bumps 2b having a diameter of 100 μm are formed on the surface of the semiconductor chip 1 of 10 mm square.
It is formed in an array of 25 × 25 at μm intervals. In this case, the occupied area of the bump 2b is about 5 mm 2 , which is 10 mm.
The occupied area ratio of the bumps 2b to the corner semiconductor chip 1 (area: 100 mm 2 ) can be obtained as 5%.
【0033】同図でバンプ2bの面積比率が 5% という
小さな面積比率のときの熱抵抗をみると、熱抵抗は、面
積比率が25% 以上のときに近い値までほぼ低下しており
実用的には問題のないレベルまで低減化されていること
がわかる。When looking at the thermal resistance when the area ratio of the bumps 2b is as small as 5% in the figure, the thermal resistance is practically reduced to a value close to that when the area ratio is 25% or more. It can be seen that it has been reduced to a level where there is no problem.
【0034】このように本実施例の半導体集積回路装置
によれば、薄膜配線層8の内層に銅やアルミニウムなど
の導体でビア13を形成したことで、たとえビア13の
断面積が小さくてもビア13を最短の熱伝達経路として
利用でき、薄膜配線層8の熱抵抗の影響を最小限にして
半導体チップ1からの放熱効率を向上させることができ
る。As described above, according to the semiconductor integrated circuit device of the present embodiment, since the via 13 is formed in the inner layer of the thin film wiring layer 8 with the conductor such as copper or aluminum, even if the cross-sectional area of the via 13 is small. The via 13 can be used as the shortest heat transfer path, the influence of the thermal resistance of the thin film wiring layer 8 can be minimized, and the efficiency of heat radiation from the semiconductor chip 1 can be improved.
【0035】また、放熱用バンプを設けたことにより、
半導体チップ1と配線基板7との機械的な接続強度も増
加させることができる。Further, since the heat radiation bumps are provided,
The mechanical connection strength between the semiconductor chip 1 and the wiring board 7 can also be increased.
【0036】なお、本実施例では、半導体チップの放熱
用バンプは、電気的入出力端子用のバンプと電気的に分
離されているが、配線基板上で信号系と異なる電源系の
接地電位などであれば、部分的に接続されていてもよ
い。In this embodiment, the heat radiation bumps of the semiconductor chip are electrically separated from the bumps for the electric input / output terminals, but the ground potential of the power supply system different from the signal system on the wiring board, etc. If so, it may be partially connected.
【0037】次に本発明の半導体集積回路装置の他の実
施例について図5に基づいて説明する。この実施例の半
導体チップ51は上記した実施例と同様に構成されてい
る。また配線基板52へのフリップチップ接続状態も上
記した実施例と同様である。同図に示すように、配線基
板51上には、薄膜配線層53が形成されており、この
薄膜配線層53には、例えば、SiO2 、Si3 N4 な
どの無機材料が用いられている。また、薄膜配線層53
の内層には、上記実施例でビアを形成していた領域を含
めて配線導体54が形成されている。Next, another embodiment of the semiconductor integrated circuit device of the present invention will be described with reference to FIG. The semiconductor chip 51 of this embodiment has the same structure as that of the above-described embodiments. The flip-chip connection state to the wiring board 52 is also the same as that of the above-mentioned embodiment. As shown in the figure, a thin film wiring layer 53 is formed on the wiring board 51, and the thin film wiring layer 53 is made of an inorganic material such as SiO 2 or Si 3 N 4 . .. In addition, the thin film wiring layer 53
In the inner layer, the wiring conductor 54 is formed including the region where the via is formed in the above embodiment.
【0038】この場合、SiO2 、Si3 N4 などの無
機材料の熱伝導度は、K=1.4W/m℃であり、半導体チッ
プ51で発生した熱は、放熱用バンプ55より薄膜配線
層53自身を通じて配線基板51へ伝達される。In this case, the thermal conductivity of the inorganic material such as SiO 2 and Si 3 N 4 is K = 1.4 W / m ° C., and the heat generated in the semiconductor chip 51 is generated from the bump 55 for heat dissipation in the thin film wiring layer. It is transmitted to the wiring board 51 through 53 itself.
【0039】この実施例によれば、薄膜配線層に無機材
料を用いることによって、無機材料の熱抵抗が低いこと
からビアを形成しなくても良好な放熱効果を得ることが
できる。また、ビアを形成しなくてもよいので、半導体
チップ51の直下の薄膜配線層53に、例えば配線導体
54を形成するなど薄膜配線層53を有効に利用するこ
とができる。According to this embodiment, by using an inorganic material for the thin film wiring layer, a good heat dissipation effect can be obtained without forming a via because the thermal resistance of the inorganic material is low. Further, since the via does not have to be formed, the thin film wiring layer 53 can be effectively used by forming the wiring conductor 54 on the thin film wiring layer 53 immediately below the semiconductor chip 51, for example.
【0040】なお、プラズマCVD法などによりAlN
(K=170W/m℃)など熱伝導度のよい無機材料を用いて
薄膜配線層を形成すれば、薄膜配線層の熱抵抗をいっそ
う低減化させることができる。さらに、薄膜配線層と配
線基板とにAlNを併用すれば、同一の材料で伝熱経路
を構成することができるので、熱膨張の差がなく半導体
集積回路装置の信頼性の点についても改善することがで
きる。AlN is formed by plasma CVD or the like.
If the thin film wiring layer is formed using an inorganic material having good thermal conductivity such as (K = 170 W / m ° C.), the thermal resistance of the thin film wiring layer can be further reduced. Furthermore, if AlN is used for both the thin film wiring layer and the wiring substrate, the heat transfer path can be formed of the same material, so that there is no difference in thermal expansion and the reliability of the semiconductor integrated circuit device is improved. be able to.
【0041】[0041]
【発明の効果】本発明の半導体集積回路装置によれば、
半導体チップから配線基板への放熱効率を向上させるこ
とができる。また、放熱用バンプを設けたことにより、
半導体チップと配線基板との機械的な接続強度も増強さ
せることができる。According to the semiconductor integrated circuit device of the present invention,
The heat radiation efficiency from the semiconductor chip to the wiring board can be improved. Also, by providing a heat dissipation bump,
The mechanical connection strength between the semiconductor chip and the wiring board can also be increased.
【図1】本発明の半導体集積回路装置に用いられる半導
体チップを示す平面図である。FIG. 1 is a plan view showing a semiconductor chip used in a semiconductor integrated circuit device of the present invention.
【図2】図1の断面図である。FIG. 2 is a cross-sectional view of FIG.
【図3】本発明の半導体集積回路装置の一実施例を示す
断面図である。FIG. 3 is a sectional view showing an embodiment of a semiconductor integrated circuit device of the present invention.
【図4】半導体チップにおけるバンプ面積に対する熱抵
抗の変化を示す図である。FIG. 4 is a diagram showing a change in thermal resistance with respect to a bump area in a semiconductor chip.
【図5】本発明の半導体集積回路装置の他の実施例の平
面図である。FIG. 5 is a plan view of another embodiment of the semiconductor integrated circuit device of the present invention.
【図6】(a)は従来の半導体チップを示す平面図であ
る。 (b)は従来の半導体集積回路装置を示す断面図であ
る。FIG. 6A is a plan view showing a conventional semiconductor chip. (B) is a sectional view showing a conventional semiconductor integrated circuit device.
1、51…………半導体チップ 2a………………入出力端子用バンプ 2b、55………放熱用バンプ 4…………………能動領域 7、52…………配線基板 12a、12b…パッド 1, 51 ………… Semiconductor chip 2a ……………… I / O terminal bumps 2b, 55 ………… Heat dissipation bumps 4 …………………… Active area 7, 52 ………… Wiring board 12a , 12b ... Pads
Claims (1)
ンプに対応させてパッドを形成した配線基板に搭載して
なる半導体集積回路装置において、 前記半導体チップの能動領域面に前記半導体チップの電
気信号回路から独立した放熱用バンプを設けてなること
を特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device in which a semiconductor chip having bumps is mounted on a wiring substrate having pads formed corresponding to the bumps, wherein an electric signal circuit of the semiconductor chip is provided on an active region surface of the semiconductor chip. A semiconductor integrated circuit device, characterized in that it is provided with a heat-releasing bump that is independent of the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3212185A JPH0555418A (en) | 1991-08-23 | 1991-08-23 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3212185A JPH0555418A (en) | 1991-08-23 | 1991-08-23 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555418A true JPH0555418A (en) | 1993-03-05 |
Family
ID=16618334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3212185A Pending JPH0555418A (en) | 1991-08-23 | 1991-08-23 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555418A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253520B2 (en) | 2001-10-11 | 2007-08-07 | Oki Electric Industry Co., Ltd. | CSP semiconductor device having signal and radiation bump groups |
| JP2012182400A (en) * | 2011-03-03 | 2012-09-20 | Ricoh Co Ltd | Heat dissipation device for integrated circuit, and electronic equipment |
| JP2014187410A (en) * | 1996-03-28 | 2014-10-02 | Intel Corp | Method for reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the board |
-
1991
- 1991-08-23 JP JP3212185A patent/JPH0555418A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014187410A (en) * | 1996-03-28 | 2014-10-02 | Intel Corp | Method for reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the board |
| US7253520B2 (en) | 2001-10-11 | 2007-08-07 | Oki Electric Industry Co., Ltd. | CSP semiconductor device having signal and radiation bump groups |
| JP2012182400A (en) * | 2011-03-03 | 2012-09-20 | Ricoh Co Ltd | Heat dissipation device for integrated circuit, and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5578525A (en) | Semiconductor device and a fabrication process thereof | |
| US7687896B2 (en) | Semiconductor device having a stacked chip structure | |
| EP0197089B1 (en) | Wafer-scale-integrated assembly | |
| US5475264A (en) | Arrangement having multilevel wiring structure used for electronic component module | |
| US20060237839A1 (en) | Apparatus for conducting heat in a flip-chip assembly | |
| US5130768A (en) | Compact, high-density packaging apparatus for high performance semiconductor devices | |
| US6131278A (en) | Metal substrate having an IC chip and carrier mounting | |
| JPH06314890A (en) | Three-dimensional package for high performance computer and structure thereof | |
| US20040046255A1 (en) | Chip package structure | |
| KR100357803B1 (en) | Method of fabricating multi-chip packages | |
| JP2003163310A (en) | High frequency semiconductor device | |
| US6890794B2 (en) | Flip chip with novel power and ground arrangement | |
| JP2001502845A (en) | RF power package with double grounding | |
| US5894166A (en) | Chip mounting scheme | |
| JPH0555418A (en) | Semiconductor integrated circuit device | |
| JP2903013B2 (en) | Circuit package including metal substrate and mounting method | |
| TWI733454B (en) | Electronic device, electronic package, and package substrate thereof | |
| JP2892687B2 (en) | Package for semiconductor device | |
| Adams et al. | High density interconnect for advanced VLSI packaging | |
| JP3735986B2 (en) | Multichip module and manufacturing method thereof | |
| JP2601640B2 (en) | Methods of making electrical conductor structures and large scale integrated circuits. | |
| JPH07193347A (en) | Wiring board | |
| JPH05251513A (en) | Semiconductor device | |
| JPS6041853B2 (en) | electronic circuit equipment | |
| JPH0377355A (en) | Heat-dissipating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20000620 |