JPH05327676A - Asynchronous signal synchronization circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A synchronization circuit that outputs an asynchronously input signal in synchronization with a synchronous clock in a digital transmission device or the like, and synchronizes an asynchronous input signal on the assumption that error recovery is performed by data retransmission. It is an object of the present invention to prevent an output signal from becoming uncertain when it is captured by a clock so that an asynchronous input signal can be converted into a synchronization signal without error. [Structure] A first D flip-prop 1 that receives an input signal Si with a synchronous clock CLK1, and a second D flip-prop 2 that receives an input signal Si with an inverted synchronous clock CLK2.
The selector 4 for selecting the output of the first or second D flip-flop 1, 2 according to the switching control signal CNT is compared with the change time of the input signal Si and the change time of the output selected by the selector, A control circuit 6 which outputs the switching control signal CNT to switch the output of the selector 4 when the change time approaches a predetermined time length or less, and a third output circuit which outputs the output of the selector 4 in synchronization with the synchronization clock CLK1. It has a configuration including a D-plip flop 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for outputting a signal input asynchronously in synchronization with a synchronous clock in a digital transmission device or the like.

[0002]

2. Description of the Related Art A digital transmission device or the like uses a synchronizing circuit which outputs a data signal input asynchronously in synchronization with a synchronous clock.

When the input asynchronous data is converted into synchronous data and transmitted, even if the nominal values of the transmission rates of the receiving side and the transmitting side (for example, 1.6 KHz and 4.8 KHz) are the same,
Strictly different, there will be bit remainders or omissions when converted.

The data transmission system to which the present invention is directed has a certain degree of bidirectional protocol and requests the data to be retransmitted when the received data has an error. In this way, when a protocol that can correct errors by resending is adopted, as a synchronization circuit that converts the input asynchronous signal into a synchronization signal and outputs it,
A method is adopted in which the output signal is synchronized with the synchronous clock by using the D flip-flop and holding the input signal again with the synchronous clock.

[0005]

In the above method, it is not necessary to set the format of the output data according to the asynchronous data that is input as in the case of start-stop synchronization, and the synchronization data can be transmitted in the optimum format on the transmission side. ..

However, when the changing point of the asynchronous input signal and the rising edge of the synchronous clock which captures this in the D flip-flop are close to each other, the output of the D-FF becomes uncertain,
The input data cannot be captured correctly, and a data error occurs in addition to a bit surplus and loss.

Then, due to the difference in the transmission speed between the input asynchronous data and the synchronized data to be transmitted, the rising edge of the synchronous clock and the transition point of the input data approach each other periodically,
Uncertainties in data acquisition occur periodically. For this reason, data bit remainders, missing bits, and errors occur periodically. Then, the smaller the difference in transmission rate between the receiving side (input side) and the transmitting side (output side), the longer the time in the uncertain region when it enters the uncertain region and the more data errors. In order to correct this, there is a problem that data transmission efficiency is deteriorated because retransmission is repeated.

The present invention has been made in view of the above problems, and is intended for a system that performs error recovery by data retransmission, and when an asynchronous input signal is taken in by a synchronous clock,
It is an object of the present invention to prevent output data from becoming uncertain and to convert an asynchronous input signal into a synchronized signal without error.

[0009]

FIG. 1 is a block diagram showing the principle of an asynchronous signal synchronizing circuit according to the present invention. The above-mentioned problem is, as shown in FIG. 1, in a synchronization circuit that outputs a signal that is input asynchronously with respect to the synchronization clock in synchronization with the synchronization clock, the first D flip-prop that takes in the input signal Si with the synchronization clock CLK1. 1, a second D flip-flop 2 that takes in the input signal Si with the inverted synchronous clock CLK2, a selector 4 that selects the output of the first or second D flip-flops 1 and 2 according to the switching control signal CNT, and an input Control for comparing the change time point of the signal Si with the change time point of the output selected by the selector and outputting the switching control signal CNT to switch the output of the selector 4 when both change time points approach a predetermined time length or less The asynchronous signal synchronizing circuit according to the present invention, which comprises a circuit 6 and a third D flip-flop 3 for outputting the output of the selector 4 in synchronization with a synchronous clock CLK1. It is solved by circuit.

[0010]

In the preceding stage where the third D flip-flop outputs the data at the timing of the synchronous clock, two D flip flops for taking in the asynchronous input data with the synchronous clock and the inverted synchronous clock are provided, and the selector selects the input data. Since the data fetched is selected by the clock farther from the change point, the fetch timing of the D flip-flop and the input data change point do not approach the predetermined time length or less, and the uncertainty of the data fetch can be prevented.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The asynchronous signal synchronizing circuit of the present invention will be described below with reference to the accompanying drawings. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is an operation timing chart of the embodiment. Note that the same reference numeral represents the same object throughout the drawings.

In FIG. 1, reference numerals 1, 2, and 3 are first, second, and third D flip-flops, 4 is a 2: 1 selector, 5 is an inverter, and 6 is a switching control circuit. The switching control circuit 6 includes four D-flip-flops 61, 62, 6
3, 64, an EX-OR gate 65, a delay circuit 66, and two inverters 67, 68.

First and second D flip-flops 1, 2
Is the asynchronous input signal Si input to the data terminal D,
Inverted synchronous clock CLK2 and synchronous clock C, respectively
It is held and output at the rising timing of LK1. One of the outputs of both flip-flops 1 and 2 is selected by the selector 4 controlled by the switching control signal CNT, and the third D
Input to the data terminal D of the flip-flop 3. The D flip-flop 3 latches this input at the rising timing of the synchronous clock CLK1 and outputs a synchronized output signal.
Output So.

The switching control circuit 6 monitors the time difference between the rising change time point of the signal output from the selector 4 and the rising change time point of the asynchronous input signal Si, and when the difference becomes equal to or less than a predetermined time T, the selector 4 is notified to the selector 4. Issue the switching control signal CNT,
The selector 4 is switched so as to selectively output the other input.

The D-FFs 61 and 62 of the switching control circuit have an asynchronous input signal Si at the clock terminal C and a selector 4 respectively.
And the output signal of
Output "H" from the output. When "L" is input to the reset terminal R, it is reset and the Q output becomes "L".

The outputs of the D-FFs 61 and 62 are exclusive-sumed by the EX-OR 65, the outputs thereof are branched into two, one of which is delayed by the time T by the delay circuit 66, and the other of which is inverted by the inverter 67. Then, it is applied to the data input terminal D and the clock terminal C of the D-FF 63, respectively. Also EX
The -OR output delay signal is inverted by the inverter 68 and input to the reset terminals R of the D-FFs 61 and 62.

The D-FF 64 has a D-FF at its clock terminal C.
The inverted Q output of the FF 63 is input, its own inverted Q output is latched at the rising edge of the FF 63, the Q output is inverted, and the Q output is supplied to the selection input of the selector 4 as the switching control signal CNT. Next, the operation will be described using the operation time chart of FIG.

The asynchronous input signal Si is composed of data D ₀ , D ₁ , D ₂ , D ₃ ... Inverted bit by bit, and the synchronous clock is an example in the case of being faster than the bit rate of the input signal. ..

First, it is assumed that the switching control signal CNT is "H" and the output of the second D-FF 2 is selected by the selector 4. The change timing of this output data is equal to the timing of the rising edge of the inverted synchronous clock CLK2. At t1, the input signal Si changes from "L" to "H", so the D-FF62 outputs "H", but the D-FF
61 is in the reset state and outputs "L", so EX-O
The output of R65 becomes "H". Therefore, the delay time T
After that, "H" is input to the data terminal of the D-FF 63 and the two D-FFs 61 and 62 are reset via the inverter 68, so that the output of the EX-OR 65 becomes "L". D
The -FF63 takes in "H" of the output of the delay circuit 66 at the fall of the output of the EX-OR (that is, the rise of the inverted output), and outputs "L" from the inverted Q output.

The same operation is performed at the timings t2 and t3 when the output of the selector 4 changes from "L" to "H". At this time, however, the difference from the rising change timing of the input signal Si is the delay time T.
Since it is larger, the D-FF63 continues to output "H".

In this way, the output of the selector 3 "L" →
Timing of change of "H" and "L" → "H" of input signal Si
When the difference between the change timings is larger than the time length T, the two D-FFs 61 and 62 are reset by the delayed output, and the output of the D-FF 63 continues at "L".

Therefore, the selector 4 has the second D-FF 2
Of the data D ₀₂ , D ₁₂ , D in synchronization with the synchronization clock CLK1.
_A synchronization signal So composed of ₂₂ is output. These data are accurately latched at a timing sufficiently far from the change point of the input signal, and there is no data error.

At the timing of t4, the rising edge of the selector output catches up with the "L" → "H" change point of the input signal Si, so that the two D-FFs 61 and 62 are simultaneously set within the time length T. Therefore, the EX-OR output falls without waiting for the reset of the D-FFs 61 and 62 by the delay circuit output. Then, the D-FF63 latches "L" of the delay circuit output at the rising edge of the inverted signal and outputs the inverted output of "L".
→ Change to "H". As a result, the switching control signal CNT, which is the Q output of D-FF64, changes from "H" to "L".
The output of the selector 4 is switched to the output of D-FF1 which latches the input data with the inverted synchronous clock CLK2. Thus, data input to subsequent D-FF3 is switched to output data D _21, D _31, D ₄₁ of the first D-FF1 which have taken up the input data at a sufficiently distant rising timing from the input data change point, Synchronous output of error-free output data D ₃₁ ... In addition, the output of the D-FF63 which becomes "H" at the timing t4 changes to "L" by the same operation as at the time of t1 at the next comparison timing t5,
Prepare for the next switching control.

As described above, according to the present invention, when the data used for output approaches the uncertain region, that is, when the change point of the asynchronous input signal and the capture timing approach, the data in the determined region, that is, the capture region, is immediately obtained. Timing 18
Since the data is switched to the 0 ° phase-shifted captured data, data bits may be left over or missing due to the original difference in transmission rate.However, even if the difference in transmission rate is small, frequent data errors occur due to continuation of uncertain areas. Can be prevented.

[0025]

As described above, according to the present invention,
Asynchronous / synchronous conversion can be performed without bit errors in a synchronization circuit used in a transmission system in which some bits are left out of synchronization and some are left out of synchronization, and data transmission efficiency can be reduced by reducing the number of retransmissions. There is an effect that can improve.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of an asynchronous signal synchronization circuit according to the present invention.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

FIG. 3 is an operation timing chart of the embodiment.

[Explanation of symbols]

1 ... 1st D flip-flop, 2 ... 2nd D flip-flop, 3 ... 3rd D flip-flop, 4 ... 2: 1
Selector, 5 ... Inverter, 6 ... Switching control circuit

Claims (1)

[Claims] 1. In a synchronizing circuit for outputting a signal input asynchronously with respect to a synchronous clock in synchronization with the synchronous clock, a first D which takes in an input signal (Si) with the synchronous clock (CLK1).
A flip-flop (1), a second D flip-flop (2) that takes in the input signal (Si) with an inverted synchronous clock (CLK2), and the first or second D flip-flop (according to the switching control signal (CNT). Selector (4) for selecting the output of (1, 2)
And the change time of the input signal (Si) and the change time of the output selected by the selector (4) are compared, and the switching control signal (CNT) is output when both change times approach the predetermined time length or less. A switching control circuit (6) for switching the output of the selector (4) and a third D-plip-flop (3) for outputting the output of the selector (4) in synchronization with the synchronous clock (CLK1). An asynchronous signal synchronization circuit characterized by the above.