JPH05283615A - Power supply wiring for semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] By changing the conventional layout method without changing the circuit, the inside of the LSI, that is, the LSI
By forming a bypass capacitor on the LSI chip side with respect to the conductor electrically connecting the chip to the outside of the LSI, noise generated in the power supply of the LSI is reduced. [Structure] V _CC power supplies 1a and 1b of two layers or more and two columns or more in order to effectively reduce noise generated in the power supply of the LSI.
In an LSI having the / GND wirings 2a and 2b, one V _CC power supply wiring 1a is arranged in the upper layer and the GND wiring is arranged in the lower layer,
In the adjacent column, GND the V _CC power supply wiring 1b in the lower layer
The wiring 2b is arranged in the upper layer. [Effect] Since the capacitance effectively formed inside the LSI chip acts as a bypass capacitance, noise generated in the power supply of the LSI can be reduced. Further, since the margin for malfunction can be increased, it is possible to operate the circuit configured on the LSI at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply wiring of a large scale integrated circuit including a large number of functions such as a processor, and is particularly effective for a high speed large scale semiconductor integrated circuit.

[0002]

2. Description of the Related Art A large-scale semiconductor integrated circuit (hereinafter referred to as an LSI) including a large number of functions such as a processor and a high-speed LSI
In order to operate the circuit at high speed, the delay time of the logic gate must be shortened. Therefore, the rise time and the fall time are shortened by increasing the driving power of the MOS transistor such as widening the gate width. .. As a result, the amount of current and the amount of change with time with respect to the current increase, and noise is generated in the power supply wiring, thereby reducing the margin for malfunction and causing a problem in high-speed operation of the LSI.

FIG. 2 shows the power supply wiring of the internal input / output circuit of the LSI. A is PMOSQ as a part of the internal circuit of LSI
1 and NMOS Q2 form an inverter. Bonding wires are used to connect the source of Q1 and the source of Q2 to an LSI external power supply, and to connect the drains of Q1 and Q2 to an LSI external circuit. , Lead pins and external circuit patterns are connected. The bonding wire, the lead pin, and the external circuit pattern have an inductance and a resistance component and are connected to the power source, GND, and an external circuit. Less than,
The inductances are L1, L2 and L3, and the resistance components are R1, R2 and R3. The charges flowing through L3 and R3 are accumulated in the load capacitance C _L. The voltage is controlled by the input terminal 10, the V _CC power supply terminal 11 is connected to the source of Q1 and the GND (V _SS ) power supply terminal 12 is connected to the source of Q2, and the drains of Q1 and Q2 are connected to the signal wiring. 9 is connected. In order to reduce the noise generated in the power supply wiring, the V _CC power supply terminal 11 and the G
A bypass capacitance C _B may be provided between the ND power supply terminal 12 and the ND power supply terminal 12. Below, the voltage of the input terminal 10 is L →
When the voltage at the connection terminal 13 between the drains of Q1 and Q2 and the address line is switched by H, and the above C _L occurs outside the chip such as wiring between LSIs when switched from H → L, that is, When Q1 and Q2 are drivers for the outside of the chip, and when C _L occurs on the same chip, that is, when Q1 and Q2 drive only the load inside the chip, the inverter depending on the presence or absence of C _B The flowing current and the noise generated by it will be described.

(I) When C _L Occurs Outside the Chip If C _B is not provided on the source side of Q1 and Q2, no current flows from C _B to the V _CC power supply terminal 11, and further No current flows from the source to C _B , and the above G
The current i ₃ flowing through the GND from the ND power supply terminal 12 through L2 and R2 is the sum of the current i ₁ and the current i ₂ . Therefore, noise is generated in the power supply wiring 1.

When C _B is provided, the current i ₅ is almost the same as the current i ₄ during the transient response, and the current i ₅ is
_{3 is} also almost the same as the current i ₂ . Therefore, although noise is generated in the power supply wiring 1, it is less than in the case where C _B is not provided.

(Ii) When C _L Occurs on the Same Chip When C _L occurs on the same chip, R ₃ and L ₃ are generally used.
Can be almost ignored with only the internal signal pattern, and GND14
Potential becomes substantially equal to the potential of the GND power supply terminal 12.

When C _B is not provided, as in the case where C _L is provided outside the chip, no current flows from C _B to the V _CC power supply terminal 11, and the current i ₃ is the current i _{3. Five}
Is equal to Therefore, noise is generated in the power supply wiring 1.

When the above C _B is provided, the current i ₅ is almost the same as the current i ₄ , so that the current i ₃ is almost zero. Therefore, almost no noise is generated in the power supply wiring 1. As described above, as the speed of the circuit increases, the amount of current and the amount of change over time of the current increase, and noise occurs in the power supply wiring 1. However, this noise may cause malfunction in other circuits. Therefore, it is necessary to reduce it. Since this noise is greatly affected by the inductance of a conductor such as a bonding wire or an LSI lead that electrically connects the LSI chip and the outside of the LSI, in order to reduce the noise generated in the power wiring of the LSI, The inductance must be reduced. However, in reality, since it is essentially difficult to reduce the inductance, the noise is reduced by inserting a bypass capacitance between the power supplies. Conventionally, the space for providing the bypass capacitance is arranged outside the LSI or inside the LSI cavity. However, since there is an inductance or a resistance between the capacitance and the chip outside the LSI or inside the LSI cavity, Noise reduction is a difficult problem.

FIG. 3 is a schematic view of a main part of a conventional power supply wiring and through hole layout. In FIG. 3A, G
The ND (V _SS ) wiring 2a is arranged in the upper layer of the GND (V _SS ) wiring 2b, and the left V _CC power supply wiring 1b is arranged in the lower layer of the V _CC power supply wiring 1a. V _CC power supply wiring 1a and 1b, G
The ND (V _SS ) wirings 2a and 2b are connected in through holes 3a and 3b in order to keep the potentials equal to each other, and although not shown in the drawing, power is supplied to the internal circuit by these wirings. Further, the V _CC power supply wiring and the GND (V _SS ) wiring are connected to the LSI external circuit section through a bonding wire or the like. Figure 3 (b)
A schematic view of a main part of a cross-sectional structure of the power supply wiring in XX ′ is shown in FIG. A combined capacitance 4 is formed between the V _CC power supply wirings 1a and 1b and the GND (V _SS ) wirings 2a and 2b. Although the composite capacitance 4 works as a bypass capacitance between the power supply and GND, only the side surface of the GND (V _SS ) wiring and the V _CC power supply wiring contributes to the capacitance, so that sufficient capacitance cannot be taken and the power supply is There is a problem that it is difficult to reduce the generated noise.

FIG. 4 is a schematic view of a main part of a layout of a ring-shaped power supply wiring in a conventional large scale integrated circuit. The V _CC power supply wirings 1 a and 1 b are supplied with a power supply voltage from the power supply bonding pad 15 and are supplied to the internal power supply wiring 8. Also,
The GND (V _SS ) wirings 2a and 2b supply the GND power supply voltage from the GND bonding pad 16, and further the internal G
The GND power supply voltage is supplied to the ND wiring 18. I
The signal in the / O region 19 is connected to the outside through the signal bonding pad 17 and is connected to the inside through the signal wiring 9. Conventionally, V _CC power supply wiring 1a,
Since the 1b and the GND wirings 2a and 2b have different columns in layout, it is necessary to pass the wiring connecting the inner wiring and the bonding pad so as to cross the outer wiring. Although not shown in the figure in particular, although a combined capacity occurs,
Since only the side surface of the wiring contributes to the capacitance, there is a problem that the capacitance is not stored and the noise generated in the power supply of the LSI cannot be reduced.

[0011]

SUMMARY OF THE INVENTION According to the present invention, the inside of an LSI, that is, the LSI chip and the outside of the LSI are electrically connected by changing the conventional layout method without changing the circuit. The purpose is to reduce the noise generated in the power supply of the LSI by forming a bypass capacitance on the chip side of the LSI with respect to the existing conductor.

[0012]

In order to effectively reduce the noise generated in the power supply wiring of the LSI, one V _CC power supply is used in an LSI having two or more layers of V _CC power supply / GND wiring. Place the wiring in the upper layer and the GND wiring in the lower layer,
In adjacent columns, the V _CC power supply wiring is arranged in the lower layer and the GND wiring is arranged in the upper layer.

[0013]

In an LSI having two or more layers and two or more columns of power / GND wiring, one V _CC power wiring is arranged in the upper layer and the GND wiring is arranged in the lower layer, and in the adjacent row, the power wiring is arranged in the lower layer and the GND wiring is arranged in the lower layer. By arranging in the upper layer, the wiring that has been conventionally used as the power supply wiring can be used as the capacitor, and therefore, the LSI chip can be made from a conductor that electrically connects the inside of the LSI, that is, the LSI chip and the outside of the LSI. By-pass capacitance can be formed on the side, and noise generated in the power supply of the LSI can be reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (a) is a schematic view of a main part of a layout of power supply wirings and through holes of the present invention. V _CC power supply wiring 1a
Is arranged in the upper layer of the GND (V _SS ) wiring 2a, and the V _CC power supply wiring 1b is arranged in the lower layer of the GND (V _SS ) wiring 2b. V
_CC power supply wirings 1a and 1b are connected by through holes 3b, and similarly GND (V _SS ) wirings 2a and 2b are connected by through holes 3a. V _CC power supply wiring 1a, 1
b and GND (V _SS ) wirings 2a and 2b are connected to the outside of the LSI through bonding wires or the like. FIG. 1B shows a schematic view of a main part of a cross-sectional structure of the power supply wiring in XX ′. A combined capacitance 4 is formed between the V _CC power supply wiring 1a and the GND (V _SS ) wiring 2a and between the V _CC power supply wiring 1b and the GND (V _SS ) wiring 2b. Since the combined capacitance 4 works as a bypass capacitance between the V _CC power supply and GND, it is possible to reduce noise generated in the power supply. Further, in FIG. 1A, V _CC is through through holes 3a and 3b.
Although the potentials of the power supply wirings 1a and 1b and the GND lines 2a and 2b are kept equal, this is not particularly limited. Further, in this embodiment, the number of layers and the number of columns are not limited to two layers and two columns, but three layers and two columns may be used. Further, the number of power supply layers is not limited, and it can be applied to power supply wiring of two or more layers.

In FIG. 1C, a bonding pad 6, an annular power supply wiring 7 and an internal power supply wiring 8 are formed on the LSI chip 5. The power supplied from the outside through the bonding pad is supplied to the ring-shaped power supply wiring 7 and is supplied to the internal circuit through the internal power supply wiring 8. In this embodiment, the circular power supply wiring 7 is shown in FIG.
And the cross-sectional structure of (b) are applied. The ring power supply wiring 7 has the structure shown in FIG. The present invention is applied to the ring-shaped power supply wiring because the current flowing through the ring-shaped power supply wiring 7 is large and requires a large area to form a large capacitance, and noise generated in the power supply from the outside is transmitted to the inside. This is because it serves to cancel. As a result, a bypass capacitor can be formed on the LSI chip side of the conductor that electrically connects the LSI chip and the outside of the LSI, and noise generated in the power source of the LSI can be reduced.

FIG. 5 is a schematic view of the main part of the layout of the ring-shaped power supply wiring in a large scale integrated circuit. V _CC power supply wiring 1
The a and 1b are supplied with V _CC power from the power supply bonding pad 15 and supplied to the internal power supply wiring 8. Also, GN
A GND power supply voltage is supplied from the GND bonding pad 16 to the D wirings 2 a and 2 b and is supplied to the internal GND wiring 18. The signal in the I / O area 19 is connected to the outside through the signal bonding pad 17,
It is connected to the inside through the signal wiring 9.

Conventionally, since the V _CC power supply wiring and the GND (V _SS ) wiring are in the same row, the wiring connecting the inner wiring and the bonding pad has to be passed through while crossing the outer wiring. Since different power supply wirings are overlapped, they can be connected as they are, and there is no need to cross them for wiring. In FIG. 5, through holes are used to connect the GND bonding pad 16 and the GND (V _SS ) wirings 2a and 2b, and the internal power supply wiring 8 and the V _CC power supply wirings 1a and 1b, but the wiring layers are the same. It is also possible to omit it. Further, even if not omitted, the positions of the through holes can be changed and arranged.

[0018]

Since the capacitor effectively formed inside the LSI chip functions as a bypass capacitor, noise generated in the power supply of the LSI can be reduced. In addition, since the margin for malfunction can be increased, the LSI
It is possible to operate the circuit configured above at high speed.

[Brief description of drawings]

FIG. 1 is a schematic view of a main part of a layout of a power supply wiring and a through hole according to the present invention in a semiconductor integrated circuit.

FIG. 2 is a schematic view of a part of an inverter and a part of a package connected to a power supply wiring of an internal input / output circuit of an LSI.

FIG. 3 is a schematic view of a main part of a conventional layout of power supply wiring and through holes.

FIG. 4 is a schematic view of a main part of a layout of a circular power supply wiring in a conventional large-scale integrated circuit.

FIG. 5 is a schematic view of a main part of a layout of ring-shaped power supply wiring in an LSI.

[Explanation of symbols]

1a, 1b ... _Vcc power supply wiring, 2a, 2b ... GND wiring, 3a, 3b ... through hole, 4 ... synthetic capacitance, 5
.... LSI chip, 6 ... Bonding pad, 7 ...
Ring power supply wiring, 8 ... Internal power supply wiring, 9 ... Signal wiring,
10 ... ・ Input terminal, 11 ・ ・ ・ ・ V _CC power supply terminal, 12 ・ ・ ・ ・ G
ND power supply terminal, connection terminal for drain of Q1 and Q2 and signal line, 14 ... GND, 15 ... Power supply bonding pad, 16 ... GND bonding pad,
17 ... Signal bonding pad, 18 ... Internal GN
D wiring, 19 ... I / O area, A ... Part of internal circuit of LSI

Claims (2)

[Claims] 1. A power supply wiring having two or more layers and two or more columns, wherein _Vcc power supply wiring is superposed on the upper layer and V _SS power supply wiring is superposed on the lower layer,
A semiconductor integrated circuit in which adjacent columns form a bypass capacitor by stacking the upper layer and the lower layer in reverse. 2. The semiconductor integrated circuit according to claim 1, wherein the power supply wiring is arranged so as to surround the periphery of the chip in a ring shape.