JPH05284526A - Error recovery circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] High-pass filtering is applied to the discontinuous portion (predetermined range between blocks), and the output is controlled to "0", thereby deteriorating the image quality when an error occurs. Can be suppressed to a minimum, and thus, when applied to a VTR, the reliability of the VTR can be increased, the redundancy for error correction can be reduced, and the recording density can be further increased. That is, it is possible to configure a digital VTR for high image quality long-time recording. A vertical and horizontal spatial concealment circuits 52 and 54, and a temporal concealment circuit 60, which obtains a plurality of interpolated value data related to the correlation of the data by subjecting the reproduced image data to a product-sum process, and an edge of the image data. The edge detection circuit 56 for detecting and the horizontal and vertical concealment circuits 52, 5
4 and selectors 53, 55, 5 which selectively output a plurality of interpolation value data from the time concealment circuit 60 based on the detection result from the edge detection circuit 56 and the error flag.
8, 61 and an adder circuit 57.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit suitable for being applied to a reproducing system such as a digital VTR such as a so-called digital 8 mm VTR.

[0002]

[Prior Art]

In recent years, a digital VTR for digitizing a color video signal and recording it on a recording medium such as a magnetic tape.
For this purpose, D1 format component type digital VTRs and D2 format composite type digital VTRs have been put to practical use. These digital VTRs recorded component signals or composite signals on magnetic tape without compression.

It has been considered to compress the information amount of the digital video signal by high efficiency encoding so that the amount of tape required for recording can be reduced and a small tape cassette can be used. Transform coding is known as one of high efficiency coding systems. The transform coding, particularly two-dimensional transform, divides image data into blocks of (8 × 8) pixels and performs orthogonal transform for each block. The conversion component (referred to as a coefficient) is divided into a high frequency component and a direct current component. Generally, since the direct current component is large and the high frequency component is small, the bit number is reduced as a whole by assigning an appropriate bit number to each coefficient. Recently, DCT (Discrete Cosine Transform) has been particularly attracting attention.

[0005]

By the way, since the DCT compresses video data and the like in block units, if there is an error in a block, it is processed in block units. When the block having the error is not used, the data of the block is not supplied to the IDCT. However, if the block with an error is not used, that block will be lost, so the previous block is
I was supplying it to CT.

Therefore, when an error occurs in a certain coefficient, if the processing by the IDCT is performed, for example, as shown in FIG.
As shown in, the originally straight line data becomes discontinuous between two broken lines bt, which causes a problem of image quality deterioration.

The present invention has been made in view of the above points, and it is possible to suppress the deterioration of image quality when an error occurs to a minimum. Therefore, when the present invention is applied to a VTR,
, An error correction circuit capable of increasing the reliability of data recording, reducing redundancy for error correction, and increasing recording density, that is, a digital VTR for high-quality long-time recording. Is what you are trying to do.

[0008]

The error correction circuit of the present invention, as shown in, for example, FIGS. 1 to 13, performs sum-of-products processing on reproduced video data to obtain a plurality of interpolated value data related to data correlation. The correction circuits 52, 54 and 60, the edge detection circuit 56 for detecting the edge of the video data, and the plurality of interpolation value data from the correction circuits 52, 54 and 60 are based on the detection result and the error signal from the edge detection circuit 56. Selection circuits 53, 55, 57, 58, 6 for selectively outputting
1 and 1.

[0009]

According to the present invention described above, the correction circuits 52 and 54 are provided.
And a plurality of interpolated value data from the edge detection circuit 5
Since the image data is selectively output based on the detection result and the error signal from No. 6, the image quality deterioration at the time of error occurrence can be suppressed to the minimum, and when applied to the VTR, the reliability of the VTR is reduced. It is possible to improve the quality, reduce the redundancy for error correction, and further increase the recording density, that is, a digital VTR for high-quality long-time recording.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the error correction circuit of the present invention will be described in detail below with reference to FIG.

First, an example of a VTR to which the error correction circuit of this embodiment is applied will be described with reference to FIG.

FIG. 2 shows a signal processing unit of a recording system and a reproducing system such as an 8 mm VTR. The digital luminance signal is supplied to the input terminal 1Y, and the digital color difference signals CR and CB are supplied to the input terminal 1C. In this case, the sampling frequency of each signal is 13.5MHz,
The frequency is 6.75 MHz, and the number of bits per sample is 8 bits. This (4: 2:
Data in the blanking period of the input video signal of 2) is removed, and only information in the effective area is recorded / reproduced. Further, although not shown, these input signals have the data order converted from the raster scan order to the block order by a block circuit.

In this example, one field is subdivided into a large number of blocks of (8 × 4) pixels. FIG. 3 shows the effective area and blocking of the luminance signal. Regarding the luminance signal Y,
Effective information of (720 pixels × 304 lines) shown in FIG. 3A is divided into (90 × 76) blocks as shown in FIG. 3B. The color difference signals CR and CB are shown in FIG.
The (45 × 76) block shown in FIG. 4B is formed from the valid information of one field of (pixel × 304 lines).

The blocked luminance signal and chrominance signal are DCT-converted by DCT conversion circuits 2Y and 2C, respectively. The coefficient data (for example, 1 sample, 12 bits) from each of the DCT conversion circuits 2Y and 2C is supplied to the shuffling circuits 3Y and 3C, respectively. The shuffling circuits 3Y and 3C are composed of, for example, field memories, and change the array of coefficient data. The shuffling circuits 3Y and 3C divide the coefficient data of each field into two along with the shuffling.

That is, in the shuffling circuits 3Y and 3C, as shown in FIG. 3C, the coefficient data Y'of the luminance data Y in one field is divided into two, that is, a shaded Ya and a shaded Yb. .. Each is (90 x 38)
It is a block. Similarly, as shown in FIG. 4C, color difference data CR in one field, coefficient data CR ′ in one field of CB, CB ′ are respectively divided into four pieces of coefficient data CRa of (45 × 38), CRb, C
Ba and CBb are formed.

Then, as shown in FIG. 5, coefficient data Y
a and the coefficient data CRa and CBa form recording data of 1/4 field, which is represented by Tk = 0 and Tk = 1, and similarly, from the coefficient data Yb and the coefficient data CRb and CBb, Tk = Recording data of 1/4 field is formed for each of 0 and Tk = 1. The recording data for this ¼ field is recorded as four tracks. In this example, 2
Double azimuth heads in which magnetic heads are closely arranged are arranged at an opposing interval of 180 °, two tracks are simultaneously formed on the magnetic field, and four tracks form one
Coefficient data for the luminance signal and the color difference signal for the field is recorded.

In this case, even if a clog is generated in one magnetic head, the coefficient block of the magnetic head is divided by alternately allocating the shaded parts of the coefficient data block and those not Coefficient blocks located above, below, to the left and right are reproduced by another magnetic head, and the coefficient data can be easily modified. The coefficient data of the shuffled result is output in the order of the coefficient data of the direct current component and the coefficient data of the alternating current component in the order of low order to high order. As an example, the shuffled coefficient data is output from the shuffling circuits 3Y and 3C in sync blocks (for example, 32 × 10 × 2 = 640 pieces of coefficient data), and the quantization circuit 4
It is supplied to Y and 4C. In the quantization circuits 4Y and 4C, 1
The 2-bit coefficient data is quantized to have a shorter n-bit length.

The outputs of the quantizing circuits 4Y and 4C are supplied to the variable length coding circuits 5Y and 5C, respectively, and are Huffman coded, for example. However, as will be described later, the coefficient of the DC component having a high degree of importance in the coefficient data is not Huffman coded. At the output of the variable length coding circuits 5Y and 5C, the coefficient data of the luminance signal and the coefficient data of the color difference signal are mixed alternately. This output data is supplied to the buffering circuits 6 and 7, respectively. The buffering circuit 6 makes the length of the sync block constant, and the buffering circuit 7 makes the amount of information for each track constant.

As described above, the shuffling circuits 3Y, 3
From C, a predetermined number (640) in sync block units
Coefficient data of is extracted. By the shuffling operation, variations in the amount of coefficient data of each block in one field are averaged. Therefore, the variable length coding circuit 5
The outputs of Y and 5C have considerably less variation in length, but there is still a difference in length, so the buffering circuit 6 makes the length of each sync block constant.

The buffering circuit 7 is a quantization circuit 4
By controlling the quantization step width in Y and 4C,
It is intended to make the amount of information per track constant. That is, by increasing the quantization step width,
The bit number n of the coefficient data becomes smaller, and conversely, by making the quantization step width smaller, the bit number n of the coefficient data becomes larger. The buffering circuit 7 is provided with a circuit for estimating the generated data amount of the current field from the data amount of the previous field, and the quantization step width is controlled according to the estimated generated data amount. In this example, the total length of the outputs of the variable length coding circuits 5Y and 5C is controlled to be (L × 171) or less on a track-by-track basis.

The output data of the buffering circuit 6 is supplied to the parity generation circuit 8 and undergoes error correction coding processing. As an example, as shown in FIG. 6, (160 × 1
71), the product code using the Reed-Solomon code is used for each recording data of one track. That is, the H parity of the Reed-Solomon code is formed for the coefficient data of each sync block in the horizontal direction, and the V parity of the Reed-Solomon code is formed for the coefficient data and the H parity of the vertical direction. Similar error correction coding is performed on coefficient data of other tracks.

The output of the parity generation circuit 8 is synchronous and I
The signal is supplied to the D addition circuit 9, and the sync signal and the ID code are added to each sync block. The output of the synchronization and ID addition circuit 9 is supplied to the encoder 10 for channel coding. Channel coding reduces the DC component of recorded data. Although the output data of the channel encoder 10 is not shown, the tape head system 11
Are supplied to the four magnetic heads, and two tracks are recorded on the magnetic tape.

The shuffling operation will be described with reference to FIG. Although FIG. 7 shows the shuffling operation for the coefficient data Y ′ of the luminance signal, the same operation is performed for the color difference signal. FIG. 7A shows the coefficient data of the (90 × 38) block shown in FIG. 2C, and the total number of coefficient data is (90 × 38 × 32 = 109,440). Since 640 coefficient data are included in one sync block, 17 sync blocks are included in one field.
It will be one. The horizontal position H (=
0-89) and its vertical position V (= 0-37) are defined. Further, as to 32 coefficient data in one block, a coefficient number C0 is defined as shown in FIG. 7B.
The coefficient data (C0 = 8) at the upper left corner is for the DC component, and in the following, the order is higher in the order of the zigzag scanning, that is, the coefficient data for the high frequency component.

Shuffling is a process in which the track number Tk, the sync number SY, and the coefficient number Cn are determined according to the following equations. Tk = [(C0 \ 16) + H + V] mod.2 SY = [9 * V + 67 * H + 171 * Cn) / 16] mod.171 Cn = [C0 + 8 + 4 * (C0 \ 16)] mod.171 where (C0 \ 16) means that 0 to 15 of C0 are set to 0 and 16 to 31 are set to 1.

According to the above equation, the track number of 0 or 1 is determined, the sync block number of 0 to 170 is determined, and the coefficient number Cn of 0 to 15 is determined. FIG. 7C shows
It shows a specific example of shuffling, and from the top (T
k = 0, SY = 0, C0 = 8), (Tk = 1, SY =
0, C0 = 8) and (Tk = 0, SY = 0, C0 = 1). As shown in FIG. 7C, (90
The coefficient data of the (× 38) block is divided into 10 areas each having a size of (9 × 38), and the coefficient data extracted from the DCT block shown in each area is included in the same sync block.

As shown in FIG. 7D, the shuffled results are output in the order from low order to high order. Figure 7D
The two pieces of data on the left side of are the luminance signal Y and the color difference signal C.
It shows the quantization level for each of. The next (10 × 2) data are coefficient data of DC components from 10 DCT blocks for each of Y and C. Further, the next (10 × 31 × 2) coefficient data is the AC component coefficient data from the 10 DCT blocks for each of Y and C. The DC component data is not subjected to variable length coding (specifically, Huffman coding), but the AC component coefficient data is Huffman coded. The 31 × 10 pieces of AC component coefficient data are arranged in order from a low order to a high order. As a result of this order, as described above, the bits of the coefficient data subjected to the processing for making the length of the sync block constant become those of higher-order coefficient data. Since the bits controlled by the excess and deficiency are affected by the error of other sync blocks, it is preferable to use high-order coefficient data that is less important than the DC component data.

The reproduced data from the tape head system 11 is supplied to the data reproducing circuit 22 through the channel encoding composite circuit 21. The reproduced data from the data reproducing circuit 22 is supplied to the inner code decoder 23. Decoder 2
In 3, error correction is performed using H parity in the horizontal direction. Then, in the next outer code decoder 24,
Error correction using vertical V parity is performed.
Data relating to the luminance signal in the error-corrected reproduction data from the decoder 24 is supplied to the variable length decoder 25Y, and data relating to the color difference signal therein is supplied to the decoder 25C. After the decoders 25Y and 25C, the processes separated by the luminance signal and the color difference signal are performed.
However, these processes are the same.

The variable-length code decoder 25Y and the inverse quantization circuit 26Y are coupled to each other, and the inverse quantization circuit 26Y converts the quantization level into a representative value. In this case, the decoder 2
Data supplied from 4 to the inverse quantization circuit 26Y is used to indicate the supplied quantization level. This representative value is supplied to the deshuffling circuit 27Y, and processing for returning the data array to the original order is performed contrary to the shuffling circuit 3Y of the recording system. The output of the deshuffling circuit 27Y is supplied to the error correction circuit 28Y.

The error correction circuit 28Y corrects an uncorrectable error (this is indicated by an error flag) by the decoders 23 and 24 with correct coefficient data included in other DCT blocks in the surroundings. By the shuffling and deshuffling processing, it is possible to prevent all coefficient data of a certain block from being erroneous, and prevent deterioration of image quality. Along with this, it is possible to reduce the possibility that an error is included in the coefficient data included in other surrounding coefficient blocks and having the same degree as the coefficient data to be modified. Therefore,
The error correction ability can be improved. The output data of the error correction circuit 28Y is supplied to the inverse conversion circuit 29Y. Luminance data restored from coefficient data is output terminal 3
Got 0Y. The error correction circuit 28Y and an error correction circuit described later will be described with reference to FIGS. 1 and 8 to 13.
Will be described later in detail.

As for the chrominance signal, similarly to the above-mentioned luminance signal, the variable length code decoder 25C and the inverse quantization circuit 26 are used.
C, deshuffling circuit 27C, error correction circuit 28
A C and inverse conversion circuit 29C is provided. Output terminal 30
The color difference data restored to C is obtained. Output terminal 30
Since the restored data obtained in Y and 30C are in the order of blocks, the order of the data is converted in the order of raster scanning by a block decomposition circuit (not shown).

Now, the above-mentioned error correction circuits 28Y and 2Y
8C is configured as shown in FIG. 1 in this example.

That is, in FIG. 1, 50 is an input terminal to which an error flag is supplied from the deshuffling circuit 27Y or 27C shown in FIG. 2, and 51 is a signal from the deshuffling circuit 27Y or 27C shown in FIG. Is an input terminal to which the deshuffled video data of is supplied. Error flags and video data from the deshuffling circuit 27Y or 27C are input to the selectors 61, 53, 55, 58, the vertical space concealment circuit 52, the horizontal space concealment circuit 54, and the motion detection circuit via these input terminals 50 and 51. 59 are supplied respectively.

The vertical space concealment circuit 52 performs error correction on the video data from the input terminal 51. Similarly, the lateral space concealment circuit 54 performs error correction on the video data from the input terminal 51. As described in FIG. 2, in the recording system, the video data is DCT.
(Discrete cosine transform) is processed. This DCT processing is intended to represent a block of n × m pixels by superimposing n × m two-dimensional cosine waves, as shown in FIG. 10, similarly to the Fourier series expansion.

FIG. 2 shows a plurality of orders of two-dimensional cosine waves represented by DCT. That is,
2B, 2C, and 2 from the cosine wave of FIG.
As shown by D, ..., FIG. 2I, FIG. 2J, FIG. 2K, ... Shows n × m two-dimensional cosine waves from 0th order to higher orders. A block of n × m pixels is expressed by superimposing these two-dimensional cosine waves.

As described with reference to FIG. 11, the loss of the two-dimensional wave due to an error causes a significant discontinuity at both ends of the block. To minimize this discontinuity,
Interpolate the data lost due to errors. Here, the discontinuity is defined as being represented by the size of the high-pass filter output before and after the boundary (the higher the high-pass filter output, the more discontinuous).

[0036]

[0037]

[Equation 1]

However, in order to use the equation 1, it is necessary that there is at least one error in one horizontal line. Therefore, it is necessary to prevent a plurality of errors from being included in one row or one column by shuffling and to prevent an error from being included in an adjacent block. However, as a characteristic of a cosine wave, even-order waves have the same sign at both ends, and odd-order waves have different signs at both ends. Therefore, even-order waves and odd-order waves have 1
If it is, concealing becomes possible by using it at the boundary on both sides. This method cannot be used for high frequency components of the original signal in principle. In the case of the nth-order DCT processing, it is effective for the coefficients from the 0th to the (n / 2-1) th. Thereby, two types of interpolated values can be obtained by independently utilizing the correlation in the horizontal direction and the correlation in the vertical direction.

FIG. 8 shows the configuration of these vertical and horizontal spatial concealment circuits 52 and 54.

In FIG. 8, reference numeral 70 denotes an IDCT (Inverse Discrete Cosine Transform) circuit, to which image data from the above-mentioned input terminal 51 is supplied. This video data is subjected to inverse discrete cosine transform processing in this IDCT 70 and supplied to the sum of products circuit 71. This sum-of-products circuit 71
Performs product-sum processing, that is, high-pass filtering processing on the video data from the IDCT 70 based on the coefficient data from the coefficient circuit 72. The outputs from the product-sum circuit 71 are supplied to the product-sum circuit 73 and the product-sum circuit 75, respectively. The video data supplied to the product-sum circuit 73 is processed by the coefficient circuit 74 in the product-sum circuit 73.
The sum of products is processed on the basis of the coefficient data, and this output is output as an interpolation value by the correlation of the left or the upper side through the output terminal 80 to the fixed contact 53a of the selector 53 or 55 shown in FIG.
Alternatively, it is supplied to 55a.

The video data supplied to the sum-of-products circuit 75 is subjected to sum-of-products processing on the basis of the coefficient data from the coefficient circuit 76 in the sum-of-products circuit 75, and the output is output terminal 82 as an interpolated value by the correlation on the right or the bottom. Through the fixed contact 53c or 55c of the selector 53 or 55 shown in FIG.

Reference numeral 77 is an adder circuit.
1 adds the interpolated values from the product-sum circuit 73 and the product-sum circuit 75, and the addition output is used as an interpolated value when there is an error in both even and odd numbers via the output terminal 81 and the selector 53 shown in FIG. Or 55 fixed contacts 53b or 55b
Supply to.

Returning to FIG. 1 again, the edge detection circuit 56 includes the image data subjected to the inverse discrete cosine transform processing by the IDCTs 70 of the vertical and horizontal concealment circuits 52 and 54 and the time concealment circuit 60 described later. So-called edge detection is performed based on the output, and the detection result is used as the fixed contact 53d of the selector 53, the fixed contact 55d of the selector 55, and the fixed contact 58 of the selector 58 described later.
supply to d respectively. Here, the edge refers to the original high frequency component of the boundary data of the video data.

The motion detection circuit 59 has an input terminal 51.
Image data from the video and a time concealment circuit 60 described later.
Output (1 field delay or 1 field M line delay 91 (see FIG. 9)), the motion detection is performed based on the video data.

Now, the edge and motion detection are processes for performing adaptive processing, and both of them have to be detected from a state including an error. Therefore, the motion detection has to be detected from the coefficient of DCT, In addition, the edge detection cannot be performed by performing processing across blocks.

In motion detection, the DCT coefficient interpolated by the method in the time concealment circuit 60 described later is calculated regardless of the presence or absence of an error in consideration of interlacing, and this D
The absolute value of the difference between the CT coefficient and the coefficient of the block to be concealed when there is no error is obtained, and the maximum value thereof is used as the motion index of the block.

Further, in the edge detection, as shown in FIG. 13, a secondary differential is obtained from three points at an end in a block, an average is obtained for each side, and the obtained average value is used as an edge index. That is, in this case, | -1 / 4x _m0 + 1 / 2x _m1
Obtain the average of -1/4 x _m2 |.

Based on the edges and motions thus obtained, for example, the 6 directions having the highest degree of correlation are determined, and the interpolated values obtained from them are adopted.

Further, as shown in FIG. 12, when the block b in which the error e exists is detected and the boundary portion p
In the case where the entire video data is composed of the white area p1 and the black area p2 with 3 in between, it is determined from the blocks in 6 directions adjacent to the block b having the error e currently detected or the blocks b in the upper, lower, left and right directions. The interpolated values are compared, and the values that are significantly different are canceled, that is, the detection result is not output to, for example, the selectors 53, 55, and 58.

The selector 53 outputs four outputs from the vertical space concealment circuit 52, that is, an interpolated value (vertical direction) by the correlation on the block supplied to the fixed contact 53a, and an even number supplied to the fixed contact 53b. And the odd-numbered interpolated value when there is an error (vertical direction) and the interpolated value (vertical direction) due to the correlation under the block supplied to the fixed contact 53c are input by the selector 53 to the input terminal 50.
Based on the error flag supplied via the movable contact 53
By e, it is selectively supplied to a fixed contact 58a of the selector 58 and an adding circuit 57 which will be described later.

On the other hand, the selector 55 outputs four outputs from the horizontal space concealing circuit 54, that is, an interpolation value (horizontal direction) according to the correlation on the left of the block supplied to the fixed contact 55a, and an even number supplied to the fixed contact 55b. The interpolated value (horizontal direction) when there is an error in any of the odd number and the odd number, and the interpolated value (horizontal direction) by the correlation on the right of the block supplied to the fixed contact 55c are input by the selector 55 to the input terminal 50.
Based on the error flag and the edge detection result supplied via the, the movable contact 55e selectively supplies the fixed contact 58a of the selector 58 and the adder circuit 57, which will be described later.

This adder circuit 57 includes selectors 53 and 5
5, the interpolation value and the edge detection result (the output signals in the vertical direction and the horizontal direction) are added, and the addition result is supplied to the fixed contact 58b of the selector 58.

The selector 58 has four outputs, namely, a vertical interpolation value supplied to the fixed contact 58a, vertical and horizontal addition outputs from the adder circuit 57 supplied to the fixed contact 58b, and a fixed contact. The horizontal interpolation value supplied to 58c is selectively supplied to the selector 61 based on the error flag and the edge detection result supplied via the input terminal 50.

The time concealment circuit 60 is, for example, a circuit for performing interpolation based on the previous field data. The effect of interlacing must be taken into account when using the data from the previous field. The image data [x _nm ] is interpolated with the image data [x ' _nm ] of the immediately preceding field.

For example, the image data [x _nm ] can be expressed by the following equations 2 and 3 depending on whether the field is odd or even.

[0056]

[Equation 2]

[0057]

[Equation 3]

By using the equations (2) and (3) and the definition equation of the DCT processing, it is possible to obtain the equation for obtaining the DCT coefficient to be concealed. These equations are shown in Equations 4 and 5 in the case of odd and even.

[0059]

[Equation 4]

[0060]

[Equation 5]

However, the DCT block size N × M, [d
_pm ] is an Nth-order DCT matrix, y _nm is a DCT coefficient to be obtained, y ′
_nm is the coefficient of the immediately preceding field, y'u _nm is the DCT coefficient of the block above [y ' _nm ], and y'd _nm is the DCT coefficient of the block below [y' _nm ].

The internal configuration of the time concealment circuit 60 is, for example, as shown in FIG. 9 in this FIG.
Reference numeral 0 is an input terminal to which the output signal from the selector 61 shown in FIG.
The output signal from 1 is supplied to the 1-field delay (or 1-field M line delay) 91.

The video data delayed by the 1-field delay 91 is supplied to the M-line delay 92 and the product-sum circuit 94, respectively. The M-line delay 92 further delays the video data from the 1-field delay 91 and then supplies it to the sum-of-products circuit 93. This sum of products circuit 93 is M
The data obtained by multiplying and summing the delayed output data from the line delay 92 is supplied to the adding circuit 95. Sum of products circuit 94
Supplies the sum of products of the video data from the 1-field delay 91 and supplies it to the adder circuit 95. This adder circuit 95
Supplies the added output obtained by adding the outputs from the sum-of-products circuits 93 and 94 to the selector 61 shown in FIG.

Returning to FIG. 1 again for explanation, the selector 6
1 is based on the error flag from the input terminal 50 and the output from the motion detection circuit 59, and the video data from the input terminal 51 and the vertical and horizontal space concealment circuit 5 from the selector 58.
Either of the outputs related to 2, 54 and the output from the time concealment circuit 60 described above is selectively supplied to the IDCT (Inverse Discrete Cosine Transform) circuit 29Y or 29C shown in FIG. 2 through the output terminal 62.

As described above, in this example, since the high-pass filtering process is performed on the discontinuous portion (predetermined range between blocks) and the output is controlled to be "0", an error occurs. Image quality deterioration at the time of occurrence can be suppressed to a minimum, so that when applied to a VTR, the VT
The reliability of R can be increased, the redundancy for error correction can be reduced, and the recording density can be increased, that is, a high-quality long-time recording digital VTR can be configured.

The above embodiment is an example of the present invention.
Of course, various other configurations can be adopted without departing from the scope of the present invention.

[0067]

According to the present invention described above, a plurality of interpolated value data from the correction circuit are selectively output based on the detection result from the edge detection circuit and the error signal. Image quality deterioration can be suppressed to a minimum, and when applied to a VTR, the VTR
There is an advantage that the reliability of the digital VTR can be improved, the redundancy for error correction can be reduced, and the recording density can be increased, that is, a high-quality long-time recording digital VTR can be configured.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an error correction circuit of the present invention.

FIG. 2 is a block diagram showing an example of a VTR to which the error correction circuit of the present invention is applied.

FIG. 3 is an explanatory diagram for explaining an embodiment of an error correction circuit of the present invention.

FIG. 4 is an explanatory diagram for explaining an embodiment of the error correction circuit of the present invention.

FIG. 5 is an explanatory diagram for explaining an embodiment of the error correction circuit of the present invention.

FIG. 6 is an explanatory diagram for explaining an embodiment of the error correction circuit of the present invention.

FIG. 7 is an explanatory diagram for explaining an embodiment of the error correction circuit of the present invention.

FIG. 8 is a configuration diagram showing a main part of an embodiment of an error correction circuit of the present invention.

FIG. 9 is a configuration diagram showing a main part of an embodiment of an error correction circuit of the present invention.

FIG. 10 is an explanatory diagram of an embodiment of the error correction circuit of the present invention.

FIG. 11 is an explanatory diagram of an embodiment of the error correction circuit of the present invention.

FIG. 12 is an explanatory diagram of an embodiment of the error correction circuit of the present invention.

FIG. 13 is an explanatory diagram of an embodiment of the error correction circuit of the present invention.

[Explanation of symbols]

 52 vertical space concealing circuit 53, 55, 58, 61 selector 54 horizontal space concealing circuit 56 edge detection circuit 57 adder circuit 59 motion detection circuit 60 time concealment circuit

Claims (1)

[Claims] 1. A retouching circuit for multiplying and summing reproduced video data to obtain a plurality of interpolated value data related to data correlation, an edge detection circuit for detecting an edge of the video data, and the retouching circuit. And a selection circuit for selectively outputting the plurality of interpolation value data based on the detection result and the error signal from the edge detection circuit.